root / hw / smbus.h @ aebcf56f
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1 | b5ea9327 | Anthony Liguori | #ifndef QEMU_SMBUS_H
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2 | b5ea9327 | Anthony Liguori | #define QEMU_SMBUS_H
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3 | b5ea9327 | Anthony Liguori | |
4 | 3fffc223 | ths | /*
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5 | 3fffc223 | ths | * QEMU SMBus API
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6 | 5fafdf24 | ths | *
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7 | 3fffc223 | ths | * Copyright (c) 2007 Arastra, Inc.
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8 | 5fafdf24 | ths | *
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9 | 3fffc223 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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10 | 3fffc223 | ths | * of this software and associated documentation files (the "Software"), to deal
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11 | 3fffc223 | ths | * in the Software without restriction, including without limitation the rights
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12 | 3fffc223 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 | 3fffc223 | ths | * copies of the Software, and to permit persons to whom the Software is
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14 | 3fffc223 | ths | * furnished to do so, subject to the following conditions:
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15 | 3fffc223 | ths | *
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16 | 3fffc223 | ths | * The above copyright notice and this permission notice shall be included in
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17 | 3fffc223 | ths | * all copies or substantial portions of the Software.
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18 | 3fffc223 | ths | *
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19 | 3fffc223 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 | 3fffc223 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 | 3fffc223 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 | 3fffc223 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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23 | 3fffc223 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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24 | 3fffc223 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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25 | 3fffc223 | ths | * THE SOFTWARE.
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26 | 3fffc223 | ths | */
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27 | 3fffc223 | ths | |
28 | 87ecb68b | pbrook | #include "i2c.h" |
29 | 3fffc223 | ths | |
30 | b5ea9327 | Anthony Liguori | #define TYPE_SMBUS_DEVICE "smbus-device" |
31 | b5ea9327 | Anthony Liguori | #define SMBUS_DEVICE(obj) \
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32 | b5ea9327 | Anthony Liguori | OBJECT_CHECK(SMBusDevice, (obj), TYPE_SMBUS_DEVICE) |
33 | b5ea9327 | Anthony Liguori | #define SMBUS_DEVICE_CLASS(klass) \
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34 | b5ea9327 | Anthony Liguori | OBJECT_CLASS_CHECK(SMBusDeviceClass, (klass), TYPE_SMBUS_DEVICE) |
35 | b5ea9327 | Anthony Liguori | #define SMBUS_DEVICE_GET_CLASS(obj) \
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36 | b5ea9327 | Anthony Liguori | OBJECT_GET_CLASS(SMBusDeviceClass, (obj), TYPE_SMBUS_DEVICE) |
37 | 1ea96673 | Paul Brook | |
38 | b5ea9327 | Anthony Liguori | typedef struct SMBusDeviceClass |
39 | b5ea9327 | Anthony Liguori | { |
40 | b5ea9327 | Anthony Liguori | I2CSlaveClass parent_class; |
41 | 81a322d4 | Gerd Hoffmann | int (*init)(SMBusDevice *dev);
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42 | 3fffc223 | ths | void (*quick_cmd)(SMBusDevice *dev, uint8_t read);
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43 | 3fffc223 | ths | void (*send_byte)(SMBusDevice *dev, uint8_t val);
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44 | 3fffc223 | ths | uint8_t (*receive_byte)(SMBusDevice *dev); |
45 | 0ff596d0 | pbrook | /* We can't distinguish between a word write and a block write with
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46 | 0ff596d0 | pbrook | length 1, so pass the whole data block including the length byte
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47 | 0ff596d0 | pbrook | (if present). The device is responsible figuring out what type of
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48 | 0ff596d0 | pbrook | command this is. */
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49 | 0ff596d0 | pbrook | void (*write_data)(SMBusDevice *dev, uint8_t cmd, uint8_t *buf, int len); |
50 | 3f582262 | balrog | /* Likewise we can't distinguish between different reads, or even know
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51 | 0ff596d0 | pbrook | the length of the read until the read is complete, so read data a
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52 | 0ff596d0 | pbrook | byte at a time. The device is responsible for adding the length
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53 | 0ff596d0 | pbrook | byte on block reads. */
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54 | 0ff596d0 | pbrook | uint8_t (*read_data)(SMBusDevice *dev, uint8_t cmd, int n);
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55 | b5ea9327 | Anthony Liguori | } SMBusDeviceClass; |
56 | 0ff596d0 | pbrook | |
57 | b5ea9327 | Anthony Liguori | struct SMBusDevice {
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58 | b5ea9327 | Anthony Liguori | /* The SMBus protocol is implemented on top of I2C. */
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59 | b5ea9327 | Anthony Liguori | I2CSlave i2c; |
60 | b5ea9327 | Anthony Liguori | |
61 | b5ea9327 | Anthony Liguori | /* Remaining fields for internal use only. */
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62 | b5ea9327 | Anthony Liguori | int mode;
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63 | b5ea9327 | Anthony Liguori | int data_len;
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64 | b5ea9327 | Anthony Liguori | uint8_t data_buf[34]; /* command + len + 32 bytes of data. */ |
65 | b5ea9327 | Anthony Liguori | uint8_t command; |
66 | b5ea9327 | Anthony Liguori | }; |
67 | b5ea9327 | Anthony Liguori | |
68 | 0ff596d0 | pbrook | /* Master device commands. */
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69 | 5b7f5327 | Juan Quintela | void smbus_quick_command(i2c_bus *bus, uint8_t addr, int read); |
70 | 5b7f5327 | Juan Quintela | uint8_t smbus_receive_byte(i2c_bus *bus, uint8_t addr); |
71 | 5b7f5327 | Juan Quintela | void smbus_send_byte(i2c_bus *bus, uint8_t addr, uint8_t data);
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72 | 5b7f5327 | Juan Quintela | uint8_t smbus_read_byte(i2c_bus *bus, uint8_t addr, uint8_t command); |
73 | 5b7f5327 | Juan Quintela | void smbus_write_byte(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t data);
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74 | 5b7f5327 | Juan Quintela | uint16_t smbus_read_word(i2c_bus *bus, uint8_t addr, uint8_t command); |
75 | 5b7f5327 | Juan Quintela | void smbus_write_word(i2c_bus *bus, uint8_t addr, uint8_t command, uint16_t data);
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76 | 5b7f5327 | Juan Quintela | int smbus_read_block(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t *data);
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77 | 5b7f5327 | Juan Quintela | void smbus_write_block(i2c_bus *bus, uint8_t addr, uint8_t command, uint8_t *data,
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78 | 0ff596d0 | pbrook | int len);
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79 | a88df0b9 | Isaku Yamahata | |
80 | a88df0b9 | Isaku Yamahata | void smbus_eeprom_init(i2c_bus *smbus, int nb_eeprom, |
81 | a88df0b9 | Isaku Yamahata | const uint8_t *eeprom_spd, int size); |
82 | b5ea9327 | Anthony Liguori | |
83 | b5ea9327 | Anthony Liguori | #endif |