root / hw / xilinx_zynq.c @ aebcf56f
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1 | e3260506 | Peter A. G. Crosthwaite | /*
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2 | e3260506 | Peter A. G. Crosthwaite | * Xilinx Zynq Baseboard System emulation.
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3 | e3260506 | Peter A. G. Crosthwaite | *
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4 | e3260506 | Peter A. G. Crosthwaite | * Copyright (c) 2010 Xilinx.
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5 | e3260506 | Peter A. G. Crosthwaite | * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
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6 | e3260506 | Peter A. G. Crosthwaite | * Copyright (c) 2012 Petalogix Pty Ltd.
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7 | e3260506 | Peter A. G. Crosthwaite | * Written by Haibing Ma
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8 | e3260506 | Peter A. G. Crosthwaite | *
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9 | e3260506 | Peter A. G. Crosthwaite | * This program is free software; you can redistribute it and/or
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10 | e3260506 | Peter A. G. Crosthwaite | * modify it under the terms of the GNU General Public License
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11 | e3260506 | Peter A. G. Crosthwaite | * as published by the Free Software Foundation; either version
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12 | e3260506 | Peter A. G. Crosthwaite | * 2 of the License, or (at your option) any later version.
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13 | e3260506 | Peter A. G. Crosthwaite | *
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14 | e3260506 | Peter A. G. Crosthwaite | * You should have received a copy of the GNU General Public License along
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15 | e3260506 | Peter A. G. Crosthwaite | * with this program; if not, see <http://www.gnu.org/licenses/>.
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16 | e3260506 | Peter A. G. Crosthwaite | */
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17 | e3260506 | Peter A. G. Crosthwaite | |
18 | e3260506 | Peter A. G. Crosthwaite | #include "sysbus.h" |
19 | e3260506 | Peter A. G. Crosthwaite | #include "arm-misc.h" |
20 | e3260506 | Peter A. G. Crosthwaite | #include "net.h" |
21 | e3260506 | Peter A. G. Crosthwaite | #include "exec-memory.h" |
22 | e3260506 | Peter A. G. Crosthwaite | #include "sysemu.h" |
23 | e3260506 | Peter A. G. Crosthwaite | #include "boards.h" |
24 | e3260506 | Peter A. G. Crosthwaite | #include "flash.h" |
25 | e3260506 | Peter A. G. Crosthwaite | #include "blockdev.h" |
26 | e3260506 | Peter A. G. Crosthwaite | #include "loader.h" |
27 | e3260506 | Peter A. G. Crosthwaite | |
28 | e3260506 | Peter A. G. Crosthwaite | #define FLASH_SIZE (64 * 1024 * 1024) |
29 | e3260506 | Peter A. G. Crosthwaite | #define FLASH_SECTOR_SIZE (128 * 1024) |
30 | e3260506 | Peter A. G. Crosthwaite | |
31 | e3260506 | Peter A. G. Crosthwaite | #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ |
32 | e3260506 | Peter A. G. Crosthwaite | |
33 | e3260506 | Peter A. G. Crosthwaite | static struct arm_boot_info zynq_binfo = {}; |
34 | e3260506 | Peter A. G. Crosthwaite | |
35 | e3260506 | Peter A. G. Crosthwaite | static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) |
36 | e3260506 | Peter A. G. Crosthwaite | { |
37 | e3260506 | Peter A. G. Crosthwaite | DeviceState *dev; |
38 | e3260506 | Peter A. G. Crosthwaite | SysBusDevice *s; |
39 | e3260506 | Peter A. G. Crosthwaite | |
40 | e3260506 | Peter A. G. Crosthwaite | qemu_check_nic_model(nd, "cadence_gem");
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41 | e3260506 | Peter A. G. Crosthwaite | dev = qdev_create(NULL, "cadence_gem"); |
42 | e3260506 | Peter A. G. Crosthwaite | qdev_set_nic_properties(dev, nd); |
43 | e3260506 | Peter A. G. Crosthwaite | qdev_init_nofail(dev); |
44 | e3260506 | Peter A. G. Crosthwaite | s = sysbus_from_qdev(dev); |
45 | e3260506 | Peter A. G. Crosthwaite | sysbus_mmio_map(s, 0, base);
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46 | e3260506 | Peter A. G. Crosthwaite | sysbus_connect_irq(s, 0, irq);
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47 | e3260506 | Peter A. G. Crosthwaite | } |
48 | e3260506 | Peter A. G. Crosthwaite | |
49 | e3260506 | Peter A. G. Crosthwaite | static void zynq_init(ram_addr_t ram_size, const char *boot_device, |
50 | e3260506 | Peter A. G. Crosthwaite | const char *kernel_filename, const char *kernel_cmdline, |
51 | e3260506 | Peter A. G. Crosthwaite | const char *initrd_filename, const char *cpu_model) |
52 | e3260506 | Peter A. G. Crosthwaite | { |
53 | 17c2f0bf | Andreas Färber | ARMCPU *cpu; |
54 | e3260506 | Peter A. G. Crosthwaite | MemoryRegion *address_space_mem = get_system_memory(); |
55 | e3260506 | Peter A. G. Crosthwaite | MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
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56 | e3260506 | Peter A. G. Crosthwaite | MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
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57 | e3260506 | Peter A. G. Crosthwaite | DeviceState *dev; |
58 | e3260506 | Peter A. G. Crosthwaite | SysBusDevice *busdev; |
59 | e3260506 | Peter A. G. Crosthwaite | qemu_irq *irqp; |
60 | e3260506 | Peter A. G. Crosthwaite | qemu_irq pic[64];
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61 | e3260506 | Peter A. G. Crosthwaite | NICInfo *nd; |
62 | e3260506 | Peter A. G. Crosthwaite | int n;
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63 | e3260506 | Peter A. G. Crosthwaite | qemu_irq cpu_irq; |
64 | e3260506 | Peter A. G. Crosthwaite | |
65 | e3260506 | Peter A. G. Crosthwaite | if (!cpu_model) {
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66 | e3260506 | Peter A. G. Crosthwaite | cpu_model = "cortex-a9";
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67 | e3260506 | Peter A. G. Crosthwaite | } |
68 | e3260506 | Peter A. G. Crosthwaite | |
69 | 17c2f0bf | Andreas Färber | cpu = cpu_arm_init(cpu_model); |
70 | 17c2f0bf | Andreas Färber | if (!cpu) {
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71 | e3260506 | Peter A. G. Crosthwaite | fprintf(stderr, "Unable to find CPU definition\n");
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72 | e3260506 | Peter A. G. Crosthwaite | exit(1);
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73 | e3260506 | Peter A. G. Crosthwaite | } |
74 | 4bd74661 | Andreas Färber | irqp = arm_pic_init_cpu(cpu); |
75 | e3260506 | Peter A. G. Crosthwaite | cpu_irq = irqp[ARM_PIC_CPU_IRQ]; |
76 | e3260506 | Peter A. G. Crosthwaite | |
77 | e3260506 | Peter A. G. Crosthwaite | /* max 2GB ram */
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78 | e3260506 | Peter A. G. Crosthwaite | if (ram_size > 0x80000000) { |
79 | e3260506 | Peter A. G. Crosthwaite | ram_size = 0x80000000;
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80 | e3260506 | Peter A. G. Crosthwaite | } |
81 | e3260506 | Peter A. G. Crosthwaite | |
82 | e3260506 | Peter A. G. Crosthwaite | /* DDR remapped to address zero. */
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83 | e3260506 | Peter A. G. Crosthwaite | memory_region_init_ram(ext_ram, "zynq.ext_ram", ram_size);
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84 | e3260506 | Peter A. G. Crosthwaite | vmstate_register_ram_global(ext_ram); |
85 | e3260506 | Peter A. G. Crosthwaite | memory_region_add_subregion(address_space_mem, 0, ext_ram);
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86 | e3260506 | Peter A. G. Crosthwaite | |
87 | e3260506 | Peter A. G. Crosthwaite | /* 256K of on-chip memory */
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88 | e3260506 | Peter A. G. Crosthwaite | memory_region_init_ram(ocm_ram, "zynq.ocm_ram", 256 << 10); |
89 | e3260506 | Peter A. G. Crosthwaite | vmstate_register_ram_global(ocm_ram); |
90 | e3260506 | Peter A. G. Crosthwaite | memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
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91 | e3260506 | Peter A. G. Crosthwaite | |
92 | e3260506 | Peter A. G. Crosthwaite | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
93 | e3260506 | Peter A. G. Crosthwaite | |
94 | e3260506 | Peter A. G. Crosthwaite | /* AMD */
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95 | e3260506 | Peter A. G. Crosthwaite | pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE, |
96 | e3260506 | Peter A. G. Crosthwaite | dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE,
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97 | e3260506 | Peter A. G. Crosthwaite | FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
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98 | e3260506 | Peter A. G. Crosthwaite | 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, |
99 | e3260506 | Peter A. G. Crosthwaite | 0);
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100 | e3260506 | Peter A. G. Crosthwaite | |
101 | e3260506 | Peter A. G. Crosthwaite | dev = qdev_create(NULL, "xilinx,zynq_slcr"); |
102 | e3260506 | Peter A. G. Crosthwaite | qdev_init_nofail(dev); |
103 | e3260506 | Peter A. G. Crosthwaite | sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xF8000000); |
104 | e3260506 | Peter A. G. Crosthwaite | |
105 | e3260506 | Peter A. G. Crosthwaite | dev = qdev_create(NULL, "a9mpcore_priv"); |
106 | e3260506 | Peter A. G. Crosthwaite | qdev_prop_set_uint32(dev, "num-cpu", 1); |
107 | e3260506 | Peter A. G. Crosthwaite | qdev_init_nofail(dev); |
108 | e3260506 | Peter A. G. Crosthwaite | busdev = sysbus_from_qdev(dev); |
109 | e3260506 | Peter A. G. Crosthwaite | sysbus_mmio_map(busdev, 0, 0xF8F00000); |
110 | e3260506 | Peter A. G. Crosthwaite | sysbus_connect_irq(busdev, 0, cpu_irq);
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111 | e3260506 | Peter A. G. Crosthwaite | |
112 | e3260506 | Peter A. G. Crosthwaite | for (n = 0; n < 64; n++) { |
113 | e3260506 | Peter A. G. Crosthwaite | pic[n] = qdev_get_gpio_in(dev, n); |
114 | e3260506 | Peter A. G. Crosthwaite | } |
115 | e3260506 | Peter A. G. Crosthwaite | |
116 | e3260506 | Peter A. G. Crosthwaite | sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]); |
117 | e3260506 | Peter A. G. Crosthwaite | sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]); |
118 | e3260506 | Peter A. G. Crosthwaite | |
119 | e3260506 | Peter A. G. Crosthwaite | sysbus_create_varargs("cadence_ttc", 0xF8001000, |
120 | e3260506 | Peter A. G. Crosthwaite | pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); |
121 | e3260506 | Peter A. G. Crosthwaite | sysbus_create_varargs("cadence_ttc", 0xF8002000, |
122 | e3260506 | Peter A. G. Crosthwaite | pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); |
123 | e3260506 | Peter A. G. Crosthwaite | |
124 | e3260506 | Peter A. G. Crosthwaite | for (n = 0; n < nb_nics; n++) { |
125 | e3260506 | Peter A. G. Crosthwaite | nd = &nd_table[n]; |
126 | e3260506 | Peter A. G. Crosthwaite | if (n == 0) { |
127 | e3260506 | Peter A. G. Crosthwaite | gem_init(nd, 0xE000B000, pic[54-IRQ_OFFSET]); |
128 | e3260506 | Peter A. G. Crosthwaite | } else if (n == 1) { |
129 | e3260506 | Peter A. G. Crosthwaite | gem_init(nd, 0xE000C000, pic[77-IRQ_OFFSET]); |
130 | e3260506 | Peter A. G. Crosthwaite | } |
131 | e3260506 | Peter A. G. Crosthwaite | } |
132 | e3260506 | Peter A. G. Crosthwaite | |
133 | e3260506 | Peter A. G. Crosthwaite | zynq_binfo.ram_size = ram_size; |
134 | e3260506 | Peter A. G. Crosthwaite | zynq_binfo.kernel_filename = kernel_filename; |
135 | e3260506 | Peter A. G. Crosthwaite | zynq_binfo.kernel_cmdline = kernel_cmdline; |
136 | e3260506 | Peter A. G. Crosthwaite | zynq_binfo.initrd_filename = initrd_filename; |
137 | e3260506 | Peter A. G. Crosthwaite | zynq_binfo.nb_cpus = 1;
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138 | e3260506 | Peter A. G. Crosthwaite | zynq_binfo.board_id = 0xd32;
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139 | e3260506 | Peter A. G. Crosthwaite | zynq_binfo.loader_start = 0;
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140 | 3aaa8dfa | Andreas Färber | arm_load_kernel(arm_env_get_cpu(first_cpu), &zynq_binfo); |
141 | e3260506 | Peter A. G. Crosthwaite | } |
142 | e3260506 | Peter A. G. Crosthwaite | |
143 | e3260506 | Peter A. G. Crosthwaite | static QEMUMachine zynq_machine = {
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144 | e3260506 | Peter A. G. Crosthwaite | .name = "xilinx-zynq-a9",
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145 | e3260506 | Peter A. G. Crosthwaite | .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
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146 | e3260506 | Peter A. G. Crosthwaite | .init = zynq_init, |
147 | e3260506 | Peter A. G. Crosthwaite | .use_scsi = 1,
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148 | e3260506 | Peter A. G. Crosthwaite | .max_cpus = 1,
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149 | e3260506 | Peter A. G. Crosthwaite | .no_sdcard = 1
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150 | e3260506 | Peter A. G. Crosthwaite | }; |
151 | e3260506 | Peter A. G. Crosthwaite | |
152 | e3260506 | Peter A. G. Crosthwaite | static void zynq_machine_init(void) |
153 | e3260506 | Peter A. G. Crosthwaite | { |
154 | e3260506 | Peter A. G. Crosthwaite | qemu_register_machine(&zynq_machine); |
155 | e3260506 | Peter A. G. Crosthwaite | } |
156 | e3260506 | Peter A. G. Crosthwaite | |
157 | e3260506 | Peter A. G. Crosthwaite | machine_init(zynq_machine_init); |