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#ifndef QEMU_HW_ESP_H
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#define QEMU_HW_ESP_H
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#include "scsi.h" |
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/* esp.c */
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#define ESP_MAX_DEVS 7 |
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typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len); |
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void esp_init(target_phys_addr_t espaddr, int it_shift, |
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ESPDMAMemoryReadWriteFunc dma_memory_read, |
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ESPDMAMemoryReadWriteFunc dma_memory_write, |
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void *dma_opaque, qemu_irq irq, qemu_irq *reset,
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qemu_irq *dma_enable); |
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#define ESP_REGS 16 |
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#define TI_BUFSZ 16 |
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typedef struct ESPState ESPState; |
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struct ESPState {
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uint8_t rregs[ESP_REGS]; |
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uint8_t wregs[ESP_REGS]; |
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qemu_irq irq; |
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uint8_t chip_id; |
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int32_t ti_size; |
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uint32_t ti_rptr, ti_wptr; |
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uint32_t status; |
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uint32_t dma; |
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uint8_t ti_buf[TI_BUFSZ]; |
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SCSIBus bus; |
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SCSIDevice *current_dev; |
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SCSIRequest *current_req; |
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uint8_t cmdbuf[TI_BUFSZ]; |
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uint32_t cmdlen; |
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uint32_t do_cmd; |
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/* The amount of data left in the current DMA transfer. */
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uint32_t dma_left; |
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/* The size of the current DMA transfer. Zero if no transfer is in
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progress. */
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uint32_t dma_counter; |
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int dma_enabled;
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uint32_t async_len; |
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uint8_t *async_buf; |
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ESPDMAMemoryReadWriteFunc dma_memory_read; |
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ESPDMAMemoryReadWriteFunc dma_memory_write; |
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void *dma_opaque;
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void (*dma_cb)(ESPState *s);
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}; |
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#define ESP_TCLO 0x0 |
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#define ESP_TCMID 0x1 |
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#define ESP_FIFO 0x2 |
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#define ESP_CMD 0x3 |
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#define ESP_RSTAT 0x4 |
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#define ESP_WBUSID 0x4 |
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#define ESP_RINTR 0x5 |
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#define ESP_WSEL 0x5 |
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#define ESP_RSEQ 0x6 |
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#define ESP_WSYNTP 0x6 |
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#define ESP_RFLAGS 0x7 |
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#define ESP_WSYNO 0x7 |
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#define ESP_CFG1 0x8 |
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#define ESP_RRES1 0x9 |
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#define ESP_WCCF 0x9 |
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#define ESP_RRES2 0xa |
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#define ESP_WTEST 0xa |
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#define ESP_CFG2 0xb |
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#define ESP_CFG3 0xc |
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#define ESP_RES3 0xd |
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#define ESP_TCHI 0xe |
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#define ESP_RES4 0xf |
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#define CMD_DMA 0x80 |
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#define CMD_CMD 0x7f |
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#define CMD_NOP 0x00 |
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#define CMD_FLUSH 0x01 |
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#define CMD_RESET 0x02 |
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#define CMD_BUSRESET 0x03 |
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#define CMD_TI 0x10 |
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#define CMD_ICCS 0x11 |
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#define CMD_MSGACC 0x12 |
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#define CMD_PAD 0x18 |
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#define CMD_SATN 0x1a |
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#define CMD_RSTATN 0x1b |
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#define CMD_SEL 0x41 |
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#define CMD_SELATN 0x42 |
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#define CMD_SELATNS 0x43 |
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#define CMD_ENSEL 0x44 |
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#define CMD_DISSEL 0x45 |
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#define STAT_DO 0x00 |
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#define STAT_DI 0x01 |
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#define STAT_CD 0x02 |
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#define STAT_ST 0x03 |
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#define STAT_MO 0x06 |
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#define STAT_MI 0x07 |
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#define STAT_PIO_MASK 0x06 |
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#define STAT_TC 0x10 |
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#define STAT_PE 0x20 |
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#define STAT_GE 0x40 |
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#define STAT_INT 0x80 |
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#define BUSID_DID 0x07 |
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#define INTR_FC 0x08 |
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#define INTR_BS 0x10 |
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#define INTR_DC 0x20 |
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#define INTR_RST 0x80 |
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#define SEQ_0 0x0 |
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#define SEQ_CD 0x4 |
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#define CFG1_RESREPT 0x40 |
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#define TCHI_FAS100A 0x4 |
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#define TCHI_AM53C974 0x12 |
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void esp_dma_enable(ESPState *s, int irq, int level); |
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void esp_request_cancelled(SCSIRequest *req);
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void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid);
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void esp_transfer_data(SCSIRequest *req, uint32_t len);
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void esp_hard_reset(ESPState *s);
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uint64_t esp_reg_read(ESPState *s, uint32_t saddr); |
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void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val);
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extern const VMStateDescription vmstate_esp; |
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#endif
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