root / target-arm / exec.h @ afc7df11
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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM execution defines
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 2c0262af | bellard | #include "dyngen-exec.h" |
21 | 2c0262af | bellard | |
22 | 2c0262af | bellard | register struct CPUARMState *env asm(AREG0); |
23 | 2c0262af | bellard | register uint32_t T0 asm(AREG1); |
24 | 2c0262af | bellard | register uint32_t T1 asm(AREG2); |
25 | 2c0262af | bellard | register uint32_t T2 asm(AREG3); |
26 | 2c0262af | bellard | |
27 | 2c0262af | bellard | #include "cpu.h" |
28 | 2c0262af | bellard | #include "exec-all.h" |
29 | 2c0262af | bellard | |
30 | 2c0262af | bellard | void cpu_lock(void); |
31 | 2c0262af | bellard | void cpu_unlock(void); |
32 | 2c0262af | bellard | void cpu_loop_exit(void); |
33 | 2c0262af | bellard | |
34 | 99c475ab | bellard | /* Implemented CPSR bits. */
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35 | 99c475ab | bellard | #define CACHED_CPSR_BITS 0xf8000000 |
36 | 2c0262af | bellard | static inline int compute_cpsr(void) |
37 | 2c0262af | bellard | { |
38 | 2c0262af | bellard | int ZF;
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39 | 2c0262af | bellard | ZF = (env->NZF == 0);
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40 | 2c0262af | bellard | return env->cpsr | (env->NZF & 0x80000000) | (ZF << 30) | |
41 | 99c475ab | bellard | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27); |
42 | 2c0262af | bellard | } |
43 | 0d1a29f9 | bellard | |
44 | 0d1a29f9 | bellard | static inline void env_to_regs(void) |
45 | 0d1a29f9 | bellard | { |
46 | 0d1a29f9 | bellard | } |
47 | 0d1a29f9 | bellard | |
48 | 0d1a29f9 | bellard | static inline void regs_to_env(void) |
49 | 0d1a29f9 | bellard | { |
50 | 0d1a29f9 | bellard | } |
51 | b8a9e8f1 | bellard | |
52 | b8a9e8f1 | bellard | int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
53 | b8a9e8f1 | bellard | int is_user, int is_softmmu); |