root / target-ppc / helper.c @ afc7df11
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1 | 79aceca5 | bellard | /*
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2 | 79aceca5 | bellard | * PPC emulation helpers for qemu.
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3 | 79aceca5 | bellard | *
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4 | 79aceca5 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | #include "exec.h" |
21 | 9a64fbe4 | bellard | |
22 | 9a64fbe4 | bellard | //#define DEBUG_MMU
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23 | 9a64fbe4 | bellard | //#define DEBUG_BATS
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24 | 9a64fbe4 | bellard | //#define DEBUG_EXCEPTIONS
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25 | 9a64fbe4 | bellard | |
26 | 9a64fbe4 | bellard | /*****************************************************************************/
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27 | 9a64fbe4 | bellard | /* PPC MMU emulation */
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28 | a541f297 | bellard | |
29 | 9a64fbe4 | bellard | /* Perform BAT hit & translation */
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30 | 9a64fbe4 | bellard | static int get_bat (CPUState *env, uint32_t *real, int *prot, |
31 | 9a64fbe4 | bellard | uint32_t virtual, int rw, int type) |
32 | 9a64fbe4 | bellard | { |
33 | 9a64fbe4 | bellard | uint32_t *BATlt, *BATut, *BATu, *BATl; |
34 | 9a64fbe4 | bellard | uint32_t base, BEPIl, BEPIu, bl; |
35 | 9a64fbe4 | bellard | int i;
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36 | 9a64fbe4 | bellard | int ret = -1; |
37 | 9a64fbe4 | bellard | |
38 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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39 | 9a64fbe4 | bellard | if (loglevel > 0) { |
40 | 9a64fbe4 | bellard | fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
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41 | 9a64fbe4 | bellard | type == ACCESS_CODE ? 'I' : 'D', virtual); |
42 | 9a64fbe4 | bellard | } |
43 | 9a64fbe4 | bellard | #endif
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44 | 9a64fbe4 | bellard | switch (type) {
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45 | 9a64fbe4 | bellard | case ACCESS_CODE:
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46 | 9a64fbe4 | bellard | BATlt = env->IBAT[1];
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47 | 9a64fbe4 | bellard | BATut = env->IBAT[0];
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48 | 9a64fbe4 | bellard | break;
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49 | 9a64fbe4 | bellard | default:
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50 | 9a64fbe4 | bellard | BATlt = env->DBAT[1];
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51 | 9a64fbe4 | bellard | BATut = env->DBAT[0];
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52 | 9a64fbe4 | bellard | break;
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53 | 9a64fbe4 | bellard | } |
54 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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55 | 9a64fbe4 | bellard | if (loglevel > 0) { |
56 | 9a64fbe4 | bellard | fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
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57 | 9a64fbe4 | bellard | type == ACCESS_CODE ? 'I' : 'D', virtual); |
58 | 9a64fbe4 | bellard | } |
59 | 9a64fbe4 | bellard | #endif
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60 | 9a64fbe4 | bellard | base = virtual & 0xFFFC0000;
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61 | 9a64fbe4 | bellard | for (i = 0; i < 4; i++) { |
62 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
63 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
64 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
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65 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
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66 | 9a64fbe4 | bellard | bl = (*BATu & 0x00001FFC) << 15; |
67 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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68 | 9a64fbe4 | bellard | if (loglevel > 0) { |
69 | 9a64fbe4 | bellard | fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
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70 | 9a64fbe4 | bellard | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
71 | 9a64fbe4 | bellard | *BATu, *BATl); |
72 | 9a64fbe4 | bellard | } |
73 | 9a64fbe4 | bellard | #endif
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74 | 9a64fbe4 | bellard | if ((virtual & 0xF0000000) == BEPIu && |
75 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
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76 | 9a64fbe4 | bellard | /* BAT matches */
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77 | 9a64fbe4 | bellard | if ((msr_pr == 0 && (*BATu & 0x00000002)) || |
78 | 9a64fbe4 | bellard | (msr_pr == 1 && (*BATu & 0x00000001))) { |
79 | 9a64fbe4 | bellard | /* Get physical address */
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80 | 9a64fbe4 | bellard | *real = (*BATl & 0xF0000000) |
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81 | 9a64fbe4 | bellard | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
82 | a541f297 | bellard | (virtual & 0x0001F000);
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83 | 9a64fbe4 | bellard | if (*BATl & 0x00000001) |
84 | 5f21aef2 | bellard | *prot = PAGE_READ; |
85 | 9a64fbe4 | bellard | if (*BATl & 0x00000002) |
86 | 5f21aef2 | bellard | *prot = PAGE_WRITE | PAGE_READ; |
87 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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88 | 9a64fbe4 | bellard | if (loglevel > 0) { |
89 | 9a64fbe4 | bellard | fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
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90 | 5f21aef2 | bellard | i, *real, *prot & PAGE_READ ? 'R' : '-', |
91 | 5f21aef2 | bellard | *prot & PAGE_WRITE ? 'W' : '-'); |
92 | 9a64fbe4 | bellard | } |
93 | 9a64fbe4 | bellard | #endif
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94 | 9a64fbe4 | bellard | ret = 0;
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95 | 9a64fbe4 | bellard | break;
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96 | 9a64fbe4 | bellard | } |
97 | 9a64fbe4 | bellard | } |
98 | 9a64fbe4 | bellard | } |
99 | 9a64fbe4 | bellard | if (ret < 0) { |
100 | 9a64fbe4 | bellard | #if defined (DEBUG_BATS)
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101 | 9a64fbe4 | bellard | printf("no BAT match for 0x%08x:\n", virtual);
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102 | 9a64fbe4 | bellard | for (i = 0; i < 4; i++) { |
103 | 9a64fbe4 | bellard | BATu = &BATut[i]; |
104 | 9a64fbe4 | bellard | BATl = &BATlt[i]; |
105 | 9a64fbe4 | bellard | BEPIu = *BATu & 0xF0000000;
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106 | 9a64fbe4 | bellard | BEPIl = *BATu & 0x0FFE0000;
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107 | 9a64fbe4 | bellard | bl = (*BATu & 0x00001FFC) << 15; |
108 | 9a64fbe4 | bellard | printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
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109 | 9a64fbe4 | bellard | "0x%08x 0x%08x 0x%08x\n",
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110 | 9a64fbe4 | bellard | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
111 | 9a64fbe4 | bellard | *BATu, *BATl, BEPIu, BEPIl, bl); |
112 | 9a64fbe4 | bellard | } |
113 | 9a64fbe4 | bellard | #endif
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114 | 9a64fbe4 | bellard | } |
115 | 9a64fbe4 | bellard | /* No hit */
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116 | 9a64fbe4 | bellard | return ret;
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117 | 9a64fbe4 | bellard | } |
118 | 9a64fbe4 | bellard | |
119 | 9a64fbe4 | bellard | /* PTE table lookup */
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120 | 9a64fbe4 | bellard | static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va, |
121 | 9a64fbe4 | bellard | int h, int key, int rw) |
122 | 9a64fbe4 | bellard | { |
123 | a541f297 | bellard | uint32_t pte0, pte1, keep = 0, access = 0; |
124 | 9a64fbe4 | bellard | int i, good = -1, store = 0; |
125 | 9a64fbe4 | bellard | int ret = -1; /* No entry found */ |
126 | 9a64fbe4 | bellard | |
127 | 9a64fbe4 | bellard | for (i = 0; i < 8; i++) { |
128 | 8df1cd07 | bellard | pte0 = ldl_phys(base + (i * 8));
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129 | 8df1cd07 | bellard | pte1 = ldl_phys(base + (i * 8) + 4); |
130 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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131 | a541f297 | bellard | if (loglevel > 0) { |
132 | a541f297 | bellard | fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
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133 | a541f297 | bellard | "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1, |
134 | a541f297 | bellard | pte0 >> 31, h, (pte0 >> 6) & 1, va); |
135 | a541f297 | bellard | } |
136 | 9a64fbe4 | bellard | #endif
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137 | 9a64fbe4 | bellard | /* Check validity and table match */
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138 | 9a64fbe4 | bellard | if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) { |
139 | 9a64fbe4 | bellard | /* Check vsid & api */
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140 | 9a64fbe4 | bellard | if ((pte0 & 0x7FFFFFBF) == va) { |
141 | 9a64fbe4 | bellard | if (good == -1) { |
142 | 9a64fbe4 | bellard | good = i; |
143 | 9a64fbe4 | bellard | keep = pte1; |
144 | 9a64fbe4 | bellard | } else {
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145 | 9a64fbe4 | bellard | /* All matches should have equal RPN, WIMG & PP */
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146 | 9a64fbe4 | bellard | if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) { |
147 | a541f297 | bellard | if (loglevel > 0) |
148 | a541f297 | bellard | fprintf(logfile, "Bad RPN/WIMG/PP\n");
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149 | 9a64fbe4 | bellard | return -1; |
150 | 9a64fbe4 | bellard | } |
151 | 9a64fbe4 | bellard | } |
152 | 9a64fbe4 | bellard | /* Check access rights */
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153 | 9a64fbe4 | bellard | if (key == 0) { |
154 | 5f21aef2 | bellard | access = PAGE_READ; |
155 | 9a64fbe4 | bellard | if ((pte1 & 0x00000003) != 0x3) |
156 | 5f21aef2 | bellard | access |= PAGE_WRITE; |
157 | 9a64fbe4 | bellard | } else {
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158 | 9a64fbe4 | bellard | switch (pte1 & 0x00000003) { |
159 | 9a64fbe4 | bellard | case 0x0: |
160 | a541f297 | bellard | access = 0;
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161 | 9a64fbe4 | bellard | break;
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162 | 9a64fbe4 | bellard | case 0x1: |
163 | 9a64fbe4 | bellard | case 0x3: |
164 | 5f21aef2 | bellard | access = PAGE_READ; |
165 | 9a64fbe4 | bellard | break;
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166 | 9a64fbe4 | bellard | case 0x2: |
167 | 5f21aef2 | bellard | access = PAGE_READ | PAGE_WRITE; |
168 | 9a64fbe4 | bellard | break;
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169 | 9a64fbe4 | bellard | } |
170 | 9a64fbe4 | bellard | } |
171 | a541f297 | bellard | if (ret < 0) { |
172 | 5f21aef2 | bellard | if ((rw == 0 && (access & PAGE_READ)) || |
173 | 5f21aef2 | bellard | (rw == 1 && (access & PAGE_WRITE))) {
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174 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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175 | a541f297 | bellard | if (loglevel > 0) |
176 | a541f297 | bellard | fprintf(logfile, "PTE access granted !\n");
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177 | 9a64fbe4 | bellard | #endif
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178 | 9a64fbe4 | bellard | good = i; |
179 | 9a64fbe4 | bellard | keep = pte1; |
180 | 9a64fbe4 | bellard | ret = 0;
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181 | a541f297 | bellard | } else {
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182 | a541f297 | bellard | /* Access right violation */
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183 | a541f297 | bellard | ret = -2;
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184 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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185 | a541f297 | bellard | if (loglevel > 0) |
186 | a541f297 | bellard | fprintf(logfile, "PTE access rejected\n");
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187 | 9a64fbe4 | bellard | #endif
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188 | 9a64fbe4 | bellard | } |
189 | a541f297 | bellard | *prot = access; |
190 | a541f297 | bellard | } |
191 | 9a64fbe4 | bellard | } |
192 | 9a64fbe4 | bellard | } |
193 | 9a64fbe4 | bellard | } |
194 | 9a64fbe4 | bellard | if (good != -1) { |
195 | 9a64fbe4 | bellard | *RPN = keep & 0xFFFFF000;
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196 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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197 | a541f297 | bellard | if (loglevel > 0) { |
198 | a541f297 | bellard | fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
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199 | 9a64fbe4 | bellard | *RPN, *prot, ret); |
200 | a541f297 | bellard | } |
201 | 9a64fbe4 | bellard | #endif
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202 | 9a64fbe4 | bellard | /* Update page flags */
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203 | 9a64fbe4 | bellard | if (!(keep & 0x00000100)) { |
204 | a541f297 | bellard | /* Access flag */
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205 | 9a64fbe4 | bellard | keep |= 0x00000100;
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206 | 9a64fbe4 | bellard | store = 1;
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207 | 9a64fbe4 | bellard | } |
208 | 9a64fbe4 | bellard | if (!(keep & 0x00000080)) { |
209 | a541f297 | bellard | if (rw && ret == 0) { |
210 | a541f297 | bellard | /* Change flag */
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211 | 9a64fbe4 | bellard | keep |= 0x00000080;
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212 | 9a64fbe4 | bellard | store = 1;
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213 | a541f297 | bellard | } else {
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214 | a541f297 | bellard | /* Force page fault for first write access */
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215 | 5f21aef2 | bellard | *prot &= ~PAGE_WRITE; |
216 | 9a64fbe4 | bellard | } |
217 | 9a64fbe4 | bellard | } |
218 | a541f297 | bellard | if (store) {
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219 | 8df1cd07 | bellard | stl_phys_notdirty(base + (good * 8) + 4, keep); |
220 | a541f297 | bellard | } |
221 | 9a64fbe4 | bellard | } |
222 | 9a64fbe4 | bellard | |
223 | 9a64fbe4 | bellard | return ret;
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224 | 79aceca5 | bellard | } |
225 | 79aceca5 | bellard | |
226 | 9a64fbe4 | bellard | static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask) |
227 | 79aceca5 | bellard | { |
228 | 9a64fbe4 | bellard | return (sdr1 & 0xFFFF0000) | (hash & mask); |
229 | 79aceca5 | bellard | } |
230 | 79aceca5 | bellard | |
231 | 9a64fbe4 | bellard | /* Perform segment based translation */
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232 | 9a64fbe4 | bellard | static int get_segment (CPUState *env, uint32_t *real, int *prot, |
233 | 9a64fbe4 | bellard | uint32_t virtual, int rw, int type) |
234 | 79aceca5 | bellard | { |
235 | 9a64fbe4 | bellard | uint32_t pg_addr, sdr, ptem, vsid, pgidx; |
236 | 9a64fbe4 | bellard | uint32_t hash, mask; |
237 | 9a64fbe4 | bellard | uint32_t sr; |
238 | 9a64fbe4 | bellard | int key;
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239 | 9a64fbe4 | bellard | int ret = -1, ret2; |
240 | 79aceca5 | bellard | |
241 | 9a64fbe4 | bellard | sr = env->sr[virtual >> 28];
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242 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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243 | a541f297 | bellard | if (loglevel > 0) { |
244 | a541f297 | bellard | fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
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245 | a541f297 | bellard | "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
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246 | a541f297 | bellard | virtual, virtual >> 28, sr, env->nip,
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247 | a541f297 | bellard | env->lr, msr_ir, msr_dr, msr_pr, rw, type); |
248 | a541f297 | bellard | } |
249 | 9a64fbe4 | bellard | #endif
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250 | a541f297 | bellard | key = (((sr & 0x20000000) && msr_pr == 1) || |
251 | a541f297 | bellard | ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0; |
252 | 9a64fbe4 | bellard | if ((sr & 0x80000000) == 0) { |
253 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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254 | a541f297 | bellard | if (loglevel > 0) |
255 | a541f297 | bellard | fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
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256 | a541f297 | bellard | key, sr & 0x10000000);
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257 | 9a64fbe4 | bellard | #endif
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258 | 9a64fbe4 | bellard | /* Check if instruction fetch is allowed, if needed */
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259 | 9a64fbe4 | bellard | if (type != ACCESS_CODE || (sr & 0x10000000) == 0) { |
260 | 9a64fbe4 | bellard | /* Page address translation */
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261 | 9a64fbe4 | bellard | vsid = sr & 0x00FFFFFF;
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262 | 9a64fbe4 | bellard | pgidx = (virtual >> 12) & 0xFFFF; |
263 | a541f297 | bellard | sdr = env->sdr1; |
264 | a541f297 | bellard | hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6; |
265 | 9a64fbe4 | bellard | mask = ((sdr & 0x000001FF) << 16) | 0xFFC0; |
266 | 9a64fbe4 | bellard | pg_addr = get_pgaddr(sdr, hash, mask); |
267 | 9a64fbe4 | bellard | ptem = (vsid << 7) | (pgidx >> 10); |
268 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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269 | a541f297 | bellard | if (loglevel > 0) { |
270 | a541f297 | bellard | fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
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271 | a541f297 | bellard | "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
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272 | a541f297 | bellard | pg_addr); |
273 | a541f297 | bellard | } |
274 | 9a64fbe4 | bellard | #endif
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275 | 9a64fbe4 | bellard | /* Primary table lookup */
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276 | 9a64fbe4 | bellard | ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
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277 | 9a64fbe4 | bellard | if (ret < 0) { |
278 | 9a64fbe4 | bellard | /* Secondary table lookup */
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279 | 9a64fbe4 | bellard | hash = (~hash) & 0x01FFFFC0;
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280 | 9a64fbe4 | bellard | pg_addr = get_pgaddr(sdr, hash, mask); |
281 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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282 | a541f297 | bellard | if (virtual != 0xEFFFFFFF && loglevel > 0) { |
283 | a541f297 | bellard | fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
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284 | a541f297 | bellard | "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
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285 | a541f297 | bellard | hash, pg_addr); |
286 | a541f297 | bellard | } |
287 | 9a64fbe4 | bellard | #endif
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288 | 9a64fbe4 | bellard | ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
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289 | 9a64fbe4 | bellard | if (ret2 != -1) |
290 | 9a64fbe4 | bellard | ret = ret2; |
291 | 9a64fbe4 | bellard | } |
292 | 9a64fbe4 | bellard | } else {
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293 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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294 | a541f297 | bellard | if (loglevel > 0) |
295 | a541f297 | bellard | fprintf(logfile, "No access allowed\n");
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296 | 9a64fbe4 | bellard | #endif
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297 | a541f297 | bellard | ret = -3;
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298 | 9a64fbe4 | bellard | } |
299 | 9a64fbe4 | bellard | } else {
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300 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
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301 | a541f297 | bellard | if (loglevel > 0) |
302 | a541f297 | bellard | fprintf(logfile, "direct store...\n");
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303 | 9a64fbe4 | bellard | #endif
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304 | 9a64fbe4 | bellard | /* Direct-store segment : absolutely *BUGGY* for now */
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305 | 9a64fbe4 | bellard | switch (type) {
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306 | 9a64fbe4 | bellard | case ACCESS_INT:
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307 | 9a64fbe4 | bellard | /* Integer load/store : only access allowed */
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308 | 9a64fbe4 | bellard | break;
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309 | 9a64fbe4 | bellard | case ACCESS_CODE:
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310 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
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311 | 9a64fbe4 | bellard | return -4; |
312 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
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313 | 9a64fbe4 | bellard | /* Floating point load/store */
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314 | 9a64fbe4 | bellard | return -4; |
315 | 9a64fbe4 | bellard | case ACCESS_RES:
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316 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
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317 | 9a64fbe4 | bellard | return -4; |
318 | 9a64fbe4 | bellard | case ACCESS_CACHE:
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319 | 9a64fbe4 | bellard | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
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320 | 9a64fbe4 | bellard | /* Should make the instruction do no-op.
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321 | 9a64fbe4 | bellard | * As it already do no-op, it's quite easy :-)
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322 | 9a64fbe4 | bellard | */
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323 | 9a64fbe4 | bellard | *real = virtual; |
324 | 9a64fbe4 | bellard | return 0; |
325 | 9a64fbe4 | bellard | case ACCESS_EXT:
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326 | 9a64fbe4 | bellard | /* eciwx or ecowx */
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327 | 9a64fbe4 | bellard | return -4; |
328 | 9a64fbe4 | bellard | default:
|
329 | 9a64fbe4 | bellard | if (logfile) {
|
330 | 9a64fbe4 | bellard | fprintf(logfile, "ERROR: instruction should not need "
|
331 | 9a64fbe4 | bellard | "address translation\n");
|
332 | 9a64fbe4 | bellard | } |
333 | 9a64fbe4 | bellard | printf("ERROR: instruction should not need "
|
334 | 9a64fbe4 | bellard | "address translation\n");
|
335 | 9a64fbe4 | bellard | return -4; |
336 | 9a64fbe4 | bellard | } |
337 | 9a64fbe4 | bellard | if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) { |
338 | 9a64fbe4 | bellard | *real = virtual; |
339 | 9a64fbe4 | bellard | ret = 2;
|
340 | 9a64fbe4 | bellard | } else {
|
341 | 9a64fbe4 | bellard | ret = -2;
|
342 | 9a64fbe4 | bellard | } |
343 | 79aceca5 | bellard | } |
344 | 9a64fbe4 | bellard | |
345 | 9a64fbe4 | bellard | return ret;
|
346 | 79aceca5 | bellard | } |
347 | 79aceca5 | bellard | |
348 | 9a64fbe4 | bellard | int get_physical_address (CPUState *env, uint32_t *physical, int *prot, |
349 | 9a64fbe4 | bellard | uint32_t address, int rw, int access_type) |
350 | 9a64fbe4 | bellard | { |
351 | 9a64fbe4 | bellard | int ret;
|
352 | 514fb8c1 | bellard | #if 0
|
353 | 9a64fbe4 | bellard | if (loglevel > 0) {
|
354 | 9a64fbe4 | bellard | fprintf(logfile, "%s\n", __func__);
|
355 | 9a64fbe4 | bellard | }
|
356 | 514fb8c1 | bellard | #endif
|
357 | 4b3686fa | bellard | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
358 | 4b3686fa | bellard | (access_type != ACCESS_CODE && msr_dr == 0)) {
|
359 | 9a64fbe4 | bellard | /* No address translation */
|
360 | a541f297 | bellard | *physical = address & ~0xFFF;
|
361 | 5f21aef2 | bellard | *prot = PAGE_READ | PAGE_WRITE; |
362 | 9a64fbe4 | bellard | ret = 0;
|
363 | 9a64fbe4 | bellard | } else {
|
364 | 9a64fbe4 | bellard | /* Try to find a BAT */
|
365 | 9a64fbe4 | bellard | ret = get_bat(env, physical, prot, address, rw, access_type); |
366 | 9a64fbe4 | bellard | if (ret < 0) { |
367 | 9a64fbe4 | bellard | /* We didn't match any BAT entry */
|
368 | 9a64fbe4 | bellard | ret = get_segment(env, physical, prot, address, rw, access_type); |
369 | 9a64fbe4 | bellard | } |
370 | 9a64fbe4 | bellard | } |
371 | 514fb8c1 | bellard | #if 0
|
372 | a541f297 | bellard | if (loglevel > 0) {
|
373 | a541f297 | bellard | fprintf(logfile, "%s address %08x => %08x\n",
|
374 | a541f297 | bellard | __func__, address, *physical);
|
375 | a541f297 | bellard | }
|
376 | 514fb8c1 | bellard | #endif
|
377 | 9a64fbe4 | bellard | return ret;
|
378 | 9a64fbe4 | bellard | } |
379 | 9a64fbe4 | bellard | |
380 | a6b025d3 | bellard | #if defined(CONFIG_USER_ONLY)
|
381 | a6b025d3 | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
382 | a6b025d3 | bellard | { |
383 | a6b025d3 | bellard | return addr;
|
384 | a6b025d3 | bellard | } |
385 | a6b025d3 | bellard | #else
|
386 | a6b025d3 | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
387 | a6b025d3 | bellard | { |
388 | a6b025d3 | bellard | uint32_t phys_addr; |
389 | a6b025d3 | bellard | int prot;
|
390 | a6b025d3 | bellard | |
391 | a6b025d3 | bellard | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
392 | a6b025d3 | bellard | return -1; |
393 | a6b025d3 | bellard | return phys_addr;
|
394 | a6b025d3 | bellard | } |
395 | a6b025d3 | bellard | #endif
|
396 | 9a64fbe4 | bellard | |
397 | 9a64fbe4 | bellard | #if !defined(CONFIG_USER_ONLY)
|
398 | 9a64fbe4 | bellard | |
399 | 9a64fbe4 | bellard | #define MMUSUFFIX _mmu
|
400 | 9a64fbe4 | bellard | #define GETPC() (__builtin_return_address(0)) |
401 | 9a64fbe4 | bellard | |
402 | 9a64fbe4 | bellard | #define SHIFT 0 |
403 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
404 | 9a64fbe4 | bellard | |
405 | 9a64fbe4 | bellard | #define SHIFT 1 |
406 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
407 | 9a64fbe4 | bellard | |
408 | 9a64fbe4 | bellard | #define SHIFT 2 |
409 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
410 | 9a64fbe4 | bellard | |
411 | 9a64fbe4 | bellard | #define SHIFT 3 |
412 | 9a64fbe4 | bellard | #include "softmmu_template.h" |
413 | 9a64fbe4 | bellard | |
414 | 9a64fbe4 | bellard | /* try to fill the TLB and return an exception if error. If retaddr is
|
415 | 9a64fbe4 | bellard | NULL, it means that the function was called in C code (i.e. not
|
416 | 9a64fbe4 | bellard | from generated code or from helper.c) */
|
417 | 9a64fbe4 | bellard | /* XXX: fix it to restore all registers */
|
418 | 0fa85d43 | bellard | void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr) |
419 | 9a64fbe4 | bellard | { |
420 | 9a64fbe4 | bellard | TranslationBlock *tb; |
421 | 9a64fbe4 | bellard | CPUState *saved_env; |
422 | a541f297 | bellard | unsigned long pc; |
423 | a541f297 | bellard | int ret;
|
424 | 9a64fbe4 | bellard | |
425 | 9a64fbe4 | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
426 | 9a64fbe4 | bellard | generated code */
|
427 | 9a64fbe4 | bellard | saved_env = env; |
428 | 9a64fbe4 | bellard | env = cpu_single_env; |
429 | b769d8fe | bellard | #if 0
|
430 | 9a64fbe4 | bellard | {
|
431 | 9a64fbe4 | bellard | unsigned long tlb_addrr, tlb_addrw;
|
432 | 9a64fbe4 | bellard | int index;
|
433 | 9a64fbe4 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
434 | 9a64fbe4 | bellard | tlb_addrr = env->tlb_read[is_user][index].address;
|
435 | 9a64fbe4 | bellard | tlb_addrw = env->tlb_write[is_user][index].address;
|
436 | 4b3686fa | bellard | if (loglevel) {
|
437 | 4b3686fa | bellard | fprintf(logfile,
|
438 | 4b3686fa | bellard | "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
|
439 | 9a64fbe4 | bellard | "(0x%08lx 0x%08lx)\n", __func__, env,
|
440 | 9a64fbe4 | bellard | &env->tlb_read[is_user][index], index, addr,
|
441 | 9a64fbe4 | bellard | tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
442 | 9a64fbe4 | bellard | tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
443 | 4b3686fa | bellard | }
|
444 | 9a64fbe4 | bellard | }
|
445 | b769d8fe | bellard | #endif
|
446 | a541f297 | bellard | ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
447 | 9a64fbe4 | bellard | if (ret) {
|
448 | 9a64fbe4 | bellard | if (retaddr) {
|
449 | 9a64fbe4 | bellard | /* now we have a real cpu fault */
|
450 | 9a64fbe4 | bellard | pc = (unsigned long)retaddr; |
451 | 9a64fbe4 | bellard | tb = tb_find_pc(pc); |
452 | 9a64fbe4 | bellard | if (tb) {
|
453 | 9a64fbe4 | bellard | /* the PC is inside the translated code. It means that we have
|
454 | 9a64fbe4 | bellard | a virtual CPU fault */
|
455 | b324e814 | bellard | cpu_restore_state(tb, env, pc, NULL);
|
456 | 9a64fbe4 | bellard | } |
457 | 9a64fbe4 | bellard | } |
458 | 9fddaa0c | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
459 | 9a64fbe4 | bellard | } |
460 | b769d8fe | bellard | #if 0
|
461 | 9a64fbe4 | bellard | {
|
462 | 9a64fbe4 | bellard | unsigned long tlb_addrr, tlb_addrw;
|
463 | 9a64fbe4 | bellard | int index;
|
464 | 9a64fbe4 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
465 | 9a64fbe4 | bellard | tlb_addrr = env->tlb_read[is_user][index].address;
|
466 | 9a64fbe4 | bellard | tlb_addrw = env->tlb_write[is_user][index].address;
|
467 | 9a64fbe4 | bellard | printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
|
468 | 9a64fbe4 | bellard | "(0x%08lx 0x%08lx)\n", __func__, env,
|
469 | 9a64fbe4 | bellard | &env->tlb_read[is_user][index], index, addr,
|
470 | 9a64fbe4 | bellard | tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
|
471 | 9a64fbe4 | bellard | tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
|
472 | 9a64fbe4 | bellard | }
|
473 | b769d8fe | bellard | #endif
|
474 | 9a64fbe4 | bellard | env = saved_env; |
475 | 9a64fbe4 | bellard | } |
476 | 9a64fbe4 | bellard | |
477 | a541f297 | bellard | void cpu_ppc_init_mmu(CPUState *env)
|
478 | 9a64fbe4 | bellard | { |
479 | 9a64fbe4 | bellard | /* Nothing to do: all translation are disabled */
|
480 | 9a64fbe4 | bellard | } |
481 | 9a64fbe4 | bellard | #endif
|
482 | 9a64fbe4 | bellard | |
483 | 9a64fbe4 | bellard | /* Perform address translation */
|
484 | 9a64fbe4 | bellard | int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, |
485 | a541f297 | bellard | int is_user, int is_softmmu) |
486 | 9a64fbe4 | bellard | { |
487 | 9a64fbe4 | bellard | uint32_t physical; |
488 | 9a64fbe4 | bellard | int prot;
|
489 | 9a64fbe4 | bellard | int exception = 0, error_code = 0; |
490 | a541f297 | bellard | int access_type;
|
491 | 9a64fbe4 | bellard | int ret = 0; |
492 | 9a64fbe4 | bellard | |
493 | b769d8fe | bellard | if (rw == 2) { |
494 | b769d8fe | bellard | /* code access */
|
495 | b769d8fe | bellard | rw = 0;
|
496 | b769d8fe | bellard | access_type = ACCESS_CODE; |
497 | b769d8fe | bellard | } else {
|
498 | b769d8fe | bellard | /* data access */
|
499 | b769d8fe | bellard | /* XXX: put correct access by using cpu_restore_state()
|
500 | b769d8fe | bellard | correctly */
|
501 | b769d8fe | bellard | access_type = ACCESS_INT; |
502 | b769d8fe | bellard | // access_type = env->access_type;
|
503 | b769d8fe | bellard | } |
504 | 9a64fbe4 | bellard | if (env->user_mode_only) {
|
505 | 9a64fbe4 | bellard | /* user mode only emulation */
|
506 | 1ef59d0a | bellard | ret = -2;
|
507 | 9a64fbe4 | bellard | goto do_fault;
|
508 | 9a64fbe4 | bellard | } |
509 | 9a64fbe4 | bellard | ret = get_physical_address(env, &physical, &prot, |
510 | 9a64fbe4 | bellard | address, rw, access_type); |
511 | 9a64fbe4 | bellard | if (ret == 0) { |
512 | a541f297 | bellard | ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
|
513 | a541f297 | bellard | is_user, is_softmmu); |
514 | 9a64fbe4 | bellard | } else if (ret < 0) { |
515 | 9a64fbe4 | bellard | do_fault:
|
516 | 9a64fbe4 | bellard | #if defined (DEBUG_MMU)
|
517 | a541f297 | bellard | if (loglevel > 0) |
518 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
519 | 9a64fbe4 | bellard | #endif
|
520 | 9a64fbe4 | bellard | if (access_type == ACCESS_CODE) {
|
521 | 9a64fbe4 | bellard | exception = EXCP_ISI; |
522 | 9a64fbe4 | bellard | switch (ret) {
|
523 | 9a64fbe4 | bellard | case -1: |
524 | 9a64fbe4 | bellard | /* No matches in page tables */
|
525 | 9a64fbe4 | bellard | error_code = EXCP_ISI_TRANSLATE; |
526 | 9a64fbe4 | bellard | break;
|
527 | 9a64fbe4 | bellard | case -2: |
528 | 9a64fbe4 | bellard | /* Access rights violation */
|
529 | 9a64fbe4 | bellard | error_code = EXCP_ISI_PROT; |
530 | 9a64fbe4 | bellard | break;
|
531 | 9a64fbe4 | bellard | case -3: |
532 | a541f297 | bellard | /* No execute protection violation */
|
533 | 9a64fbe4 | bellard | error_code = EXCP_ISI_NOEXEC; |
534 | 9a64fbe4 | bellard | break;
|
535 | 9a64fbe4 | bellard | case -4: |
536 | 9a64fbe4 | bellard | /* Direct store exception */
|
537 | 9a64fbe4 | bellard | /* No code fetch is allowed in direct-store areas */
|
538 | a541f297 | bellard | error_code = EXCP_ISI_DIRECT; |
539 | 9a64fbe4 | bellard | break;
|
540 | 9a64fbe4 | bellard | } |
541 | 9a64fbe4 | bellard | } else {
|
542 | 9a64fbe4 | bellard | exception = EXCP_DSI; |
543 | 9a64fbe4 | bellard | switch (ret) {
|
544 | 9a64fbe4 | bellard | case -1: |
545 | 9a64fbe4 | bellard | /* No matches in page tables */
|
546 | 9a64fbe4 | bellard | error_code = EXCP_DSI_TRANSLATE; |
547 | 9a64fbe4 | bellard | break;
|
548 | 9a64fbe4 | bellard | case -2: |
549 | 9a64fbe4 | bellard | /* Access rights violation */
|
550 | 9a64fbe4 | bellard | error_code = EXCP_DSI_PROT; |
551 | 9a64fbe4 | bellard | break;
|
552 | 9a64fbe4 | bellard | case -4: |
553 | 9a64fbe4 | bellard | /* Direct store exception */
|
554 | 9a64fbe4 | bellard | switch (access_type) {
|
555 | 9a64fbe4 | bellard | case ACCESS_FLOAT:
|
556 | 9a64fbe4 | bellard | /* Floating point load/store */
|
557 | 9a64fbe4 | bellard | exception = EXCP_ALIGN; |
558 | 9a64fbe4 | bellard | error_code = EXCP_ALIGN_FP; |
559 | 9a64fbe4 | bellard | break;
|
560 | 9a64fbe4 | bellard | case ACCESS_RES:
|
561 | 9a64fbe4 | bellard | /* lwarx, ldarx or srwcx. */
|
562 | 9a64fbe4 | bellard | exception = EXCP_DSI; |
563 | 9a64fbe4 | bellard | error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT; |
564 | 9a64fbe4 | bellard | break;
|
565 | 9a64fbe4 | bellard | case ACCESS_EXT:
|
566 | 9a64fbe4 | bellard | /* eciwx or ecowx */
|
567 | 9a64fbe4 | bellard | exception = EXCP_DSI; |
568 | a541f297 | bellard | error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT | |
569 | a541f297 | bellard | EXCP_DSI_ECXW; |
570 | 9a64fbe4 | bellard | break;
|
571 | 9a64fbe4 | bellard | default:
|
572 | a541f297 | bellard | printf("DSI: invalid exception (%d)\n", ret);
|
573 | 9a64fbe4 | bellard | exception = EXCP_PROGRAM; |
574 | 9a64fbe4 | bellard | error_code = EXCP_INVAL | EXCP_INVAL_INVAL; |
575 | 9a64fbe4 | bellard | break;
|
576 | 9a64fbe4 | bellard | } |
577 | 9a64fbe4 | bellard | } |
578 | 9a64fbe4 | bellard | if (rw)
|
579 | 9a64fbe4 | bellard | error_code |= EXCP_DSI_STORE; |
580 | a541f297 | bellard | /* Store fault address */
|
581 | a541f297 | bellard | env->spr[DAR] = address; |
582 | 9a64fbe4 | bellard | } |
583 | 9a64fbe4 | bellard | #if 0
|
584 | 9a64fbe4 | bellard | printf("%s: set exception to %d %02x\n",
|
585 | 9a64fbe4 | bellard | __func__, exception, error_code);
|
586 | 9a64fbe4 | bellard | #endif
|
587 | 9a64fbe4 | bellard | env->exception_index = exception; |
588 | 9a64fbe4 | bellard | env->error_code = error_code; |
589 | 9a64fbe4 | bellard | ret = 1;
|
590 | 9a64fbe4 | bellard | } |
591 | 9a64fbe4 | bellard | return ret;
|
592 | 9a64fbe4 | bellard | } |
593 | 9a64fbe4 | bellard | |
594 | a541f297 | bellard | uint32_t _load_xer (CPUState *env) |
595 | 79aceca5 | bellard | { |
596 | 79aceca5 | bellard | return (xer_so << XER_SO) |
|
597 | 79aceca5 | bellard | (xer_ov << XER_OV) | |
598 | 79aceca5 | bellard | (xer_ca << XER_CA) | |
599 | 79aceca5 | bellard | (xer_bc << XER_BC); |
600 | 79aceca5 | bellard | } |
601 | 79aceca5 | bellard | |
602 | a541f297 | bellard | void _store_xer (CPUState *env, uint32_t value)
|
603 | 79aceca5 | bellard | { |
604 | 79aceca5 | bellard | xer_so = (value >> XER_SO) & 0x01;
|
605 | 79aceca5 | bellard | xer_ov = (value >> XER_OV) & 0x01;
|
606 | 79aceca5 | bellard | xer_ca = (value >> XER_CA) & 0x01;
|
607 | 79aceca5 | bellard | xer_bc = (value >> XER_BC) & 0x1f;
|
608 | 79aceca5 | bellard | } |
609 | 79aceca5 | bellard | |
610 | a541f297 | bellard | uint32_t _load_msr (CPUState *env) |
611 | 79aceca5 | bellard | { |
612 | 79aceca5 | bellard | return (msr_pow << MSR_POW) |
|
613 | 79aceca5 | bellard | (msr_ile << MSR_ILE) | |
614 | 79aceca5 | bellard | (msr_ee << MSR_EE) | |
615 | 79aceca5 | bellard | (msr_pr << MSR_PR) | |
616 | 79aceca5 | bellard | (msr_fp << MSR_FP) | |
617 | 79aceca5 | bellard | (msr_me << MSR_ME) | |
618 | 79aceca5 | bellard | (msr_fe0 << MSR_FE0) | |
619 | 79aceca5 | bellard | (msr_se << MSR_SE) | |
620 | 79aceca5 | bellard | (msr_be << MSR_BE) | |
621 | 79aceca5 | bellard | (msr_fe1 << MSR_FE1) | |
622 | 79aceca5 | bellard | (msr_ip << MSR_IP) | |
623 | 79aceca5 | bellard | (msr_ir << MSR_IR) | |
624 | 79aceca5 | bellard | (msr_dr << MSR_DR) | |
625 | 79aceca5 | bellard | (msr_ri << MSR_RI) | |
626 | 79aceca5 | bellard | (msr_le << MSR_LE); |
627 | 79aceca5 | bellard | } |
628 | 79aceca5 | bellard | |
629 | a541f297 | bellard | void _store_msr (CPUState *env, uint32_t value)
|
630 | 79aceca5 | bellard | { |
631 | 4b3686fa | bellard | #if 0 // TRY
|
632 | 1ef59d0a | bellard | if (((value >> MSR_IR) & 0x01) != msr_ir ||
|
633 | 4b3686fa | bellard | ((value >> MSR_DR) & 0x01) != msr_dr)
|
634 | 4b3686fa | bellard | {
|
635 | a541f297 | bellard | /* Flush all tlb when changing translation mode or privilege level */
|
636 | 1ef59d0a | bellard | tlb_flush(env, 1);
|
637 | a541f297 | bellard | }
|
638 | 4b3686fa | bellard | #endif
|
639 | 9a64fbe4 | bellard | msr_pow = (value >> MSR_POW) & 0x03;
|
640 | 9a64fbe4 | bellard | msr_ile = (value >> MSR_ILE) & 0x01;
|
641 | 9a64fbe4 | bellard | msr_ee = (value >> MSR_EE) & 0x01;
|
642 | 9a64fbe4 | bellard | msr_pr = (value >> MSR_PR) & 0x01;
|
643 | 9a64fbe4 | bellard | msr_fp = (value >> MSR_FP) & 0x01;
|
644 | 9a64fbe4 | bellard | msr_me = (value >> MSR_ME) & 0x01;
|
645 | 9a64fbe4 | bellard | msr_fe0 = (value >> MSR_FE0) & 0x01;
|
646 | 9a64fbe4 | bellard | msr_se = (value >> MSR_SE) & 0x01;
|
647 | 9a64fbe4 | bellard | msr_be = (value >> MSR_BE) & 0x01;
|
648 | 9a64fbe4 | bellard | msr_fe1 = (value >> MSR_FE1) & 0x01;
|
649 | 9a64fbe4 | bellard | msr_ip = (value >> MSR_IP) & 0x01;
|
650 | 9a64fbe4 | bellard | msr_ir = (value >> MSR_IR) & 0x01;
|
651 | 9a64fbe4 | bellard | msr_dr = (value >> MSR_DR) & 0x01;
|
652 | 9a64fbe4 | bellard | msr_ri = (value >> MSR_RI) & 0x01;
|
653 | 9a64fbe4 | bellard | msr_le = (value >> MSR_LE) & 0x01;
|
654 | 18fba28c | bellard | /* XXX: should enter PM state if msr_pow has been set */
|
655 | 79aceca5 | bellard | } |
656 | 79aceca5 | bellard | |
657 | 18fba28c | bellard | #if defined (CONFIG_USER_ONLY)
|
658 | 9a64fbe4 | bellard | void do_interrupt (CPUState *env)
|
659 | 79aceca5 | bellard | { |
660 | 18fba28c | bellard | env->exception_index = -1;
|
661 | 18fba28c | bellard | } |
662 | 9a64fbe4 | bellard | #else
|
663 | 18fba28c | bellard | void do_interrupt (CPUState *env)
|
664 | 18fba28c | bellard | { |
665 | 9a64fbe4 | bellard | uint32_t msr; |
666 | 18fba28c | bellard | int excp;
|
667 | 79aceca5 | bellard | |
668 | 18fba28c | bellard | excp = env->exception_index; |
669 | a541f297 | bellard | msr = _load_msr(env); |
670 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
671 | a541f297 | bellard | if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) |
672 | 9a64fbe4 | bellard | { |
673 | 9a64fbe4 | bellard | if (loglevel > 0) { |
674 | 9a64fbe4 | bellard | fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
675 | 9a64fbe4 | bellard | env->nip, excp << 8, env->error_code);
|
676 | b769d8fe | bellard | } |
677 | a541f297 | bellard | if (loglevel > 0) |
678 | 7fe48483 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
679 | 79aceca5 | bellard | } |
680 | 9a64fbe4 | bellard | #endif
|
681 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
682 | b769d8fe | bellard | fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
|
683 | b769d8fe | bellard | env->nip, excp << 8, env->error_code);
|
684 | b769d8fe | bellard | } |
685 | 9a64fbe4 | bellard | /* Generate informations in save/restore registers */
|
686 | 9a64fbe4 | bellard | switch (excp) {
|
687 | 9a64fbe4 | bellard | case EXCP_NONE:
|
688 | 9a64fbe4 | bellard | /* Do nothing */
|
689 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
690 | 9a64fbe4 | bellard | printf("%s: escape EXCP_NONE\n", __func__);
|
691 | 9a64fbe4 | bellard | #endif
|
692 | 9a64fbe4 | bellard | return;
|
693 | 9a64fbe4 | bellard | case EXCP_RESET:
|
694 | 9a64fbe4 | bellard | if (msr_ip)
|
695 | 9a64fbe4 | bellard | excp += 0xFFC00;
|
696 | 9a64fbe4 | bellard | goto store_next;
|
697 | 9a64fbe4 | bellard | case EXCP_MACHINE_CHECK:
|
698 | 9a64fbe4 | bellard | if (msr_me == 0) { |
699 | 4b3686fa | bellard | cpu_abort(env, "Machine check exception while not allowed\n");
|
700 | 79aceca5 | bellard | } |
701 | 9a64fbe4 | bellard | msr_me = 0;
|
702 | 9a64fbe4 | bellard | break;
|
703 | 9a64fbe4 | bellard | case EXCP_DSI:
|
704 | 9a64fbe4 | bellard | /* Store exception cause */
|
705 | 9a64fbe4 | bellard | /* data location address has been stored
|
706 | 9a64fbe4 | bellard | * when the fault has been detected
|
707 | 9a64fbe4 | bellard | */
|
708 | a541f297 | bellard | msr &= ~0xFFFF0000;
|
709 | a541f297 | bellard | env->spr[DSISR] = 0;
|
710 | a541f297 | bellard | if (env->error_code & EXCP_DSI_TRANSLATE)
|
711 | a541f297 | bellard | env->spr[DSISR] |= 0x40000000;
|
712 | a541f297 | bellard | else if (env->error_code & EXCP_DSI_PROT) |
713 | a541f297 | bellard | env->spr[DSISR] |= 0x08000000;
|
714 | a541f297 | bellard | else if (env->error_code & EXCP_DSI_NOTSUP) { |
715 | a541f297 | bellard | env->spr[DSISR] |= 0x80000000;
|
716 | a541f297 | bellard | if (env->error_code & EXCP_DSI_DIRECT)
|
717 | a541f297 | bellard | env->spr[DSISR] |= 0x04000000;
|
718 | a541f297 | bellard | } |
719 | a541f297 | bellard | if (env->error_code & EXCP_DSI_STORE)
|
720 | a541f297 | bellard | env->spr[DSISR] |= 0x02000000;
|
721 | a541f297 | bellard | if ((env->error_code & 0xF) == EXCP_DSI_DABR) |
722 | a541f297 | bellard | env->spr[DSISR] |= 0x00400000;
|
723 | a541f297 | bellard | if (env->error_code & EXCP_DSI_ECXW)
|
724 | a541f297 | bellard | env->spr[DSISR] |= 0x00100000;
|
725 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
726 | a541f297 | bellard | if (loglevel) {
|
727 | a541f297 | bellard | fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
|
728 | a541f297 | bellard | env->spr[DSISR], env->spr[DAR]); |
729 | a541f297 | bellard | } else {
|
730 | a541f297 | bellard | printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
|
731 | a541f297 | bellard | env->spr[DSISR], env->spr[DAR], env->nip); |
732 | a541f297 | bellard | } |
733 | a541f297 | bellard | #endif
|
734 | a541f297 | bellard | goto store_next;
|
735 | 9a64fbe4 | bellard | case EXCP_ISI:
|
736 | 9a64fbe4 | bellard | /* Store exception cause */
|
737 | a541f297 | bellard | msr &= ~0xFFFF0000;
|
738 | 9a64fbe4 | bellard | if (env->error_code == EXCP_ISI_TRANSLATE)
|
739 | 9a64fbe4 | bellard | msr |= 0x40000000;
|
740 | 9a64fbe4 | bellard | else if (env->error_code == EXCP_ISI_NOEXEC || |
741 | a541f297 | bellard | env->error_code == EXCP_ISI_GUARD || |
742 | a541f297 | bellard | env->error_code == EXCP_ISI_DIRECT) |
743 | 9a64fbe4 | bellard | msr |= 0x10000000;
|
744 | 9a64fbe4 | bellard | else
|
745 | 9a64fbe4 | bellard | msr |= 0x08000000;
|
746 | a541f297 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
747 | a541f297 | bellard | if (loglevel) {
|
748 | a541f297 | bellard | fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
|
749 | a541f297 | bellard | msr, env->nip); |
750 | a541f297 | bellard | } else {
|
751 | a541f297 | bellard | printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
|
752 | a541f297 | bellard | msr, env->nip, env->spr[V_TBL]); |
753 | a541f297 | bellard | } |
754 | a541f297 | bellard | #endif
|
755 | 9a64fbe4 | bellard | goto store_next;
|
756 | 9a64fbe4 | bellard | case EXCP_EXTERNAL:
|
757 | 9a64fbe4 | bellard | if (msr_ee == 0) { |
758 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
759 | 9a64fbe4 | bellard | if (loglevel > 0) { |
760 | 9a64fbe4 | bellard | fprintf(logfile, "Skipping hardware interrupt\n");
|
761 | 79aceca5 | bellard | } |
762 | 9a64fbe4 | bellard | #endif
|
763 | a541f297 | bellard | /* Requeue it */
|
764 | 9fddaa0c | bellard | do_raise_exception(EXCP_EXTERNAL); |
765 | 9a64fbe4 | bellard | return;
|
766 | 79aceca5 | bellard | } |
767 | 9a64fbe4 | bellard | goto store_next;
|
768 | 9a64fbe4 | bellard | case EXCP_ALIGN:
|
769 | 9a64fbe4 | bellard | /* Store exception cause */
|
770 | 9a64fbe4 | bellard | /* Get rS/rD and rA from faulting opcode */
|
771 | 9a64fbe4 | bellard | env->spr[DSISR] |= |
772 | 0fa85d43 | bellard | (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
773 | 9a64fbe4 | bellard | /* data location address has been stored
|
774 | 9a64fbe4 | bellard | * when the fault has been detected
|
775 | 9a64fbe4 | bellard | */
|
776 | 9a64fbe4 | bellard | goto store_current;
|
777 | 9a64fbe4 | bellard | case EXCP_PROGRAM:
|
778 | 9a64fbe4 | bellard | msr &= ~0xFFFF0000;
|
779 | 9a64fbe4 | bellard | switch (env->error_code & ~0xF) { |
780 | 9a64fbe4 | bellard | case EXCP_FP:
|
781 | 9a64fbe4 | bellard | if (msr_fe0 == 0 && msr_fe1 == 0) { |
782 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
783 | 9a64fbe4 | bellard | printf("Ignore floating point exception\n");
|
784 | 9a64fbe4 | bellard | #endif
|
785 | 9a64fbe4 | bellard | return;
|
786 | 79aceca5 | bellard | } |
787 | 9a64fbe4 | bellard | msr |= 0x00100000;
|
788 | 9a64fbe4 | bellard | /* Set FX */
|
789 | 9a64fbe4 | bellard | env->fpscr[7] |= 0x8; |
790 | 9a64fbe4 | bellard | /* Finally, update FEX */
|
791 | 9a64fbe4 | bellard | if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) & |
792 | 9a64fbe4 | bellard | ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3))) |
793 | 9a64fbe4 | bellard | env->fpscr[7] |= 0x4; |
794 | 9a64fbe4 | bellard | break;
|
795 | 9a64fbe4 | bellard | case EXCP_INVAL:
|
796 | 4b3686fa | bellard | // printf("Invalid instruction at 0x%08x\n", env->nip);
|
797 | 9a64fbe4 | bellard | msr |= 0x00080000;
|
798 | 9a64fbe4 | bellard | break;
|
799 | 9a64fbe4 | bellard | case EXCP_PRIV:
|
800 | 9a64fbe4 | bellard | msr |= 0x00040000;
|
801 | 9a64fbe4 | bellard | break;
|
802 | 9a64fbe4 | bellard | case EXCP_TRAP:
|
803 | 9a64fbe4 | bellard | msr |= 0x00020000;
|
804 | 9a64fbe4 | bellard | break;
|
805 | 9a64fbe4 | bellard | default:
|
806 | 9a64fbe4 | bellard | /* Should never occur */
|
807 | 9a64fbe4 | bellard | break;
|
808 | 79aceca5 | bellard | } |
809 | 9a64fbe4 | bellard | msr |= 0x00010000;
|
810 | 9a64fbe4 | bellard | goto store_current;
|
811 | 9a64fbe4 | bellard | case EXCP_NO_FP:
|
812 | 9a64fbe4 | bellard | goto store_current;
|
813 | 9a64fbe4 | bellard | case EXCP_DECR:
|
814 | 9a64fbe4 | bellard | if (msr_ee == 0) { |
815 | 9a64fbe4 | bellard | /* Requeue it */
|
816 | 9fddaa0c | bellard | do_raise_exception(EXCP_DECR); |
817 | 9a64fbe4 | bellard | return;
|
818 | 9a64fbe4 | bellard | } |
819 | 9a64fbe4 | bellard | goto store_next;
|
820 | 9a64fbe4 | bellard | case EXCP_SYSCALL:
|
821 | b769d8fe | bellard | if (loglevel & CPU_LOG_INT) {
|
822 | b769d8fe | bellard | fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
823 | b769d8fe | bellard | env->gpr[0], env->gpr[3], env->gpr[4], |
824 | b769d8fe | bellard | env->gpr[5], env->gpr[6]); |
825 | b769d8fe | bellard | if (env->gpr[0] == 4 && env->gpr[3] == 1) { |
826 | b769d8fe | bellard | int len, addr, i;
|
827 | b769d8fe | bellard | uint8_t c; |
828 | b769d8fe | bellard | |
829 | b769d8fe | bellard | fprintf(logfile, "write: ");
|
830 | b769d8fe | bellard | addr = env->gpr[4];
|
831 | b769d8fe | bellard | len = env->gpr[5];
|
832 | b769d8fe | bellard | if (len > 64) |
833 | b769d8fe | bellard | len = 64;
|
834 | b769d8fe | bellard | for(i = 0; i < len; i++) { |
835 | b769d8fe | bellard | c = 0;
|
836 | b769d8fe | bellard | cpu_memory_rw_debug(env, addr + i, &c, 1, 0); |
837 | b769d8fe | bellard | if (c < 32 || c > 126) |
838 | b769d8fe | bellard | c = '.';
|
839 | b769d8fe | bellard | fprintf(logfile, "%c", c);
|
840 | b769d8fe | bellard | } |
841 | b769d8fe | bellard | fprintf(logfile, "\n");
|
842 | b769d8fe | bellard | } |
843 | b769d8fe | bellard | } |
844 | 9a64fbe4 | bellard | goto store_next;
|
845 | 9a64fbe4 | bellard | case EXCP_TRACE:
|
846 | 9a64fbe4 | bellard | goto store_next;
|
847 | 9a64fbe4 | bellard | case EXCP_FP_ASSIST:
|
848 | 9a64fbe4 | bellard | goto store_next;
|
849 | 9a64fbe4 | bellard | case EXCP_MTMSR:
|
850 | 9a64fbe4 | bellard | /* Nothing to do */
|
851 | 9a64fbe4 | bellard | return;
|
852 | 9a64fbe4 | bellard | case EXCP_BRANCH:
|
853 | 9a64fbe4 | bellard | /* Nothing to do */
|
854 | 9a64fbe4 | bellard | return;
|
855 | 9a64fbe4 | bellard | case EXCP_RFI:
|
856 | 9a64fbe4 | bellard | /* Restore user-mode state */
|
857 | a541f297 | bellard | tb_flush(env); |
858 | 9a64fbe4 | bellard | #if defined (DEBUG_EXCEPTIONS)
|
859 | a541f297 | bellard | if (msr_pr == 1) |
860 | a541f297 | bellard | printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
|
861 | 9a64fbe4 | bellard | #endif
|
862 | 9a64fbe4 | bellard | return;
|
863 | 9a64fbe4 | bellard | store_current:
|
864 | 9a64fbe4 | bellard | /* SRR0 is set to current instruction */
|
865 | 9a64fbe4 | bellard | env->spr[SRR0] = (uint32_t)env->nip - 4;
|
866 | 9a64fbe4 | bellard | break;
|
867 | 9a64fbe4 | bellard | store_next:
|
868 | 9a64fbe4 | bellard | /* SRR0 is set to next instruction */
|
869 | 9a64fbe4 | bellard | env->spr[SRR0] = (uint32_t)env->nip; |
870 | 9a64fbe4 | bellard | break;
|
871 | 9a64fbe4 | bellard | } |
872 | 9a64fbe4 | bellard | env->spr[SRR1] = msr; |
873 | 9a64fbe4 | bellard | /* reload MSR with correct bits */
|
874 | 9a64fbe4 | bellard | msr_pow = 0;
|
875 | 9a64fbe4 | bellard | msr_ee = 0;
|
876 | 9a64fbe4 | bellard | msr_pr = 0;
|
877 | 9a64fbe4 | bellard | msr_fp = 0;
|
878 | 9a64fbe4 | bellard | msr_fe0 = 0;
|
879 | 9a64fbe4 | bellard | msr_se = 0;
|
880 | 9a64fbe4 | bellard | msr_be = 0;
|
881 | 9a64fbe4 | bellard | msr_fe1 = 0;
|
882 | 9a64fbe4 | bellard | msr_ir = 0;
|
883 | 9a64fbe4 | bellard | msr_dr = 0;
|
884 | 9a64fbe4 | bellard | msr_ri = 0;
|
885 | 9a64fbe4 | bellard | msr_le = msr_ile; |
886 | 9a64fbe4 | bellard | /* Jump to handler */
|
887 | 9a64fbe4 | bellard | env->nip = excp << 8;
|
888 | 9a64fbe4 | bellard | env->exception_index = EXCP_NONE; |
889 | 9a64fbe4 | bellard | /* Invalidate all TLB as we may have changed translation mode */
|
890 | 1ef59d0a | bellard | tlb_flush(env, 1);
|
891 | 9a64fbe4 | bellard | /* ensure that no TB jump will be modified as
|
892 | 9a64fbe4 | bellard | the program flow was changed */
|
893 | 9a64fbe4 | bellard | #ifdef __sparc__
|
894 | 9a64fbe4 | bellard | tmp_T0 = 0;
|
895 | 9a64fbe4 | bellard | #else
|
896 | 9a64fbe4 | bellard | T0 = 0;
|
897 | 9a64fbe4 | bellard | #endif
|
898 | 9fddaa0c | bellard | env->exception_index = -1;
|
899 | fb0eaffc | bellard | } |
900 | 18fba28c | bellard | #endif /* !CONFIG_USER_ONLY */ |