root / target-sparc / fop_template.h @ afc7df11
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1 | e8af50a3 | bellard | /*
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2 | e8af50a3 | bellard | * SPARC micro operations (templates for various register related
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3 | e8af50a3 | bellard | * operations)
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4 | e8af50a3 | bellard | *
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5 | e8af50a3 | bellard | * Copyright (c) 2003 Fabrice Bellard
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6 | e8af50a3 | bellard | *
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7 | e8af50a3 | bellard | * This library is free software; you can redistribute it and/or
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8 | e8af50a3 | bellard | * modify it under the terms of the GNU Lesser General Public
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9 | e8af50a3 | bellard | * License as published by the Free Software Foundation; either
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10 | e8af50a3 | bellard | * version 2 of the License, or (at your option) any later version.
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11 | e8af50a3 | bellard | *
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12 | e8af50a3 | bellard | * This library is distributed in the hope that it will be useful,
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13 | e8af50a3 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | e8af50a3 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | e8af50a3 | bellard | * Lesser General Public License for more details.
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16 | e8af50a3 | bellard | *
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17 | e8af50a3 | bellard | * You should have received a copy of the GNU Lesser General Public
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18 | e8af50a3 | bellard | * License along with this library; if not, write to the Free Software
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19 | e8af50a3 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | e8af50a3 | bellard | */
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21 | e8af50a3 | bellard | |
22 | e8af50a3 | bellard | /* floating point registers moves */
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23 | e8af50a3 | bellard | void OPPROTO glue(op_load_fpr_FT0_fpr, REGNAME)(void) |
24 | e8af50a3 | bellard | { |
25 | e8af50a3 | bellard | FT0 = REG; |
26 | e8af50a3 | bellard | } |
27 | e8af50a3 | bellard | |
28 | e8af50a3 | bellard | void OPPROTO glue(op_store_FT0_fpr_fpr, REGNAME)(void) |
29 | e8af50a3 | bellard | { |
30 | e8af50a3 | bellard | REG = FT0; |
31 | e8af50a3 | bellard | } |
32 | e8af50a3 | bellard | |
33 | e8af50a3 | bellard | void OPPROTO glue(op_load_fpr_FT1_fpr, REGNAME)(void) |
34 | e8af50a3 | bellard | { |
35 | e8af50a3 | bellard | FT1 = REG; |
36 | e8af50a3 | bellard | } |
37 | e8af50a3 | bellard | |
38 | e8af50a3 | bellard | void OPPROTO glue(op_store_FT1_fpr_fpr, REGNAME)(void) |
39 | e8af50a3 | bellard | { |
40 | e8af50a3 | bellard | REG = FT1; |
41 | e8af50a3 | bellard | } |
42 | e8af50a3 | bellard | |
43 | e8af50a3 | bellard | void OPPROTO glue(op_load_fpr_FT2_fpr, REGNAME)(void) |
44 | e8af50a3 | bellard | { |
45 | e8af50a3 | bellard | FT2 = REG; |
46 | e8af50a3 | bellard | } |
47 | e8af50a3 | bellard | |
48 | e8af50a3 | bellard | void OPPROTO glue(op_store_FT2_fpr_fpr, REGNAME)(void) |
49 | e8af50a3 | bellard | { |
50 | e8af50a3 | bellard | REG = FT2; |
51 | e8af50a3 | bellard | } |
52 | e8af50a3 | bellard | |
53 | e8af50a3 | bellard | /* double floating point registers moves */
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54 | e8af50a3 | bellard | void OPPROTO glue(op_load_fpr_DT0_fpr, REGNAME)(void) |
55 | e8af50a3 | bellard | { |
56 | e8af50a3 | bellard | CPU_DoubleU u; |
57 | e8af50a3 | bellard | uint32_t *p = (uint32_t *)® |
58 | e8af50a3 | bellard | u.l.lower = *(p +1);
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59 | e8af50a3 | bellard | u.l.upper = *p; |
60 | e8af50a3 | bellard | DT0 = u.d; |
61 | e8af50a3 | bellard | } |
62 | e8af50a3 | bellard | |
63 | e8af50a3 | bellard | void OPPROTO glue(op_store_DT0_fpr_fpr, REGNAME)(void) |
64 | e8af50a3 | bellard | { |
65 | e8af50a3 | bellard | CPU_DoubleU u; |
66 | e8af50a3 | bellard | uint32_t *p = (uint32_t *)® |
67 | e8af50a3 | bellard | u.d = DT0; |
68 | e8af50a3 | bellard | *(p +1) = u.l.lower;
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69 | e8af50a3 | bellard | *p = u.l.upper; |
70 | e8af50a3 | bellard | } |
71 | e8af50a3 | bellard | |
72 | e8af50a3 | bellard | void OPPROTO glue(op_load_fpr_DT1_fpr, REGNAME)(void) |
73 | e8af50a3 | bellard | { |
74 | e8af50a3 | bellard | CPU_DoubleU u; |
75 | e8af50a3 | bellard | uint32_t *p = (uint32_t *)® |
76 | e8af50a3 | bellard | u.l.lower = *(p +1);
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77 | e8af50a3 | bellard | u.l.upper = *p; |
78 | e8af50a3 | bellard | DT1 = u.d; |
79 | e8af50a3 | bellard | } |
80 | e8af50a3 | bellard | |
81 | e8af50a3 | bellard | void OPPROTO glue(op_store_DT1_fpr_fpr, REGNAME)(void) |
82 | e8af50a3 | bellard | { |
83 | e8af50a3 | bellard | CPU_DoubleU u; |
84 | e8af50a3 | bellard | uint32_t *p = (uint32_t *)® |
85 | e8af50a3 | bellard | u.d = DT1; |
86 | e8af50a3 | bellard | *(p +1) = u.l.lower;
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87 | e8af50a3 | bellard | *p = u.l.upper; |
88 | e8af50a3 | bellard | } |
89 | e8af50a3 | bellard | |
90 | e8af50a3 | bellard | void OPPROTO glue(op_load_fpr_DT2_fpr, REGNAME)(void) |
91 | e8af50a3 | bellard | { |
92 | e8af50a3 | bellard | CPU_DoubleU u; |
93 | e8af50a3 | bellard | uint32_t *p = (uint32_t *)® |
94 | e8af50a3 | bellard | u.l.lower = *(p +1);
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95 | e8af50a3 | bellard | u.l.upper = *p; |
96 | e8af50a3 | bellard | DT2 = u.d; |
97 | e8af50a3 | bellard | } |
98 | e8af50a3 | bellard | |
99 | e8af50a3 | bellard | void OPPROTO glue(op_store_DT2_fpr_fpr, REGNAME)(void) |
100 | e8af50a3 | bellard | { |
101 | e8af50a3 | bellard | CPU_DoubleU u; |
102 | e8af50a3 | bellard | uint32_t *p = (uint32_t *)® |
103 | e8af50a3 | bellard | u.d = DT2; |
104 | e8af50a3 | bellard | *(p +1) = u.l.lower;
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105 | e8af50a3 | bellard | *p = u.l.upper; |
106 | e8af50a3 | bellard | } |
107 | e8af50a3 | bellard | |
108 | e8af50a3 | bellard | #undef REG
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109 | e8af50a3 | bellard | #undef REGNAME |