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/*
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* defines common to all virtual CPUs
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef CPU_ALL_H
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#define CPU_ALL_H
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#if defined(__arm__) || defined(__sparc__)
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#define WORDS_ALIGNED
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#endif
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/* some important defines:
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*
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* WORDS_ALIGNED : if defined, the host cpu can only make word aligned
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* memory accesses.
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*
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* WORDS_BIGENDIAN : if defined, the host cpu is big endian and
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* otherwise little endian.
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*
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* (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
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*
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* TARGET_WORDS_BIGENDIAN : same for target cpu
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*/
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#include "bswap.h" |
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#if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
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#define BSWAP_NEEDED
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#endif
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#ifdef BSWAP_NEEDED
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static inline uint16_t tswap16(uint16_t s) |
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{ |
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return bswap16(s);
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} |
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static inline uint32_t tswap32(uint32_t s) |
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{ |
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return bswap32(s);
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} |
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static inline uint64_t tswap64(uint64_t s) |
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{ |
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return bswap64(s);
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} |
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static inline void tswap16s(uint16_t *s) |
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{ |
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*s = bswap16(*s); |
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} |
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static inline void tswap32s(uint32_t *s) |
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{ |
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*s = bswap32(*s); |
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} |
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static inline void tswap64s(uint64_t *s) |
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{ |
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*s = bswap64(*s); |
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} |
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#else
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static inline uint16_t tswap16(uint16_t s) |
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{ |
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return s;
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} |
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static inline uint32_t tswap32(uint32_t s) |
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{ |
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return s;
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} |
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static inline uint64_t tswap64(uint64_t s) |
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{ |
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return s;
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} |
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static inline void tswap16s(uint16_t *s) |
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{ |
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} |
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static inline void tswap32s(uint32_t *s) |
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{ |
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} |
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static inline void tswap64s(uint64_t *s) |
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{ |
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} |
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#endif
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#if TARGET_LONG_SIZE == 4 |
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#define tswapl(s) tswap32(s)
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#define tswapls(s) tswap32s((uint32_t *)(s))
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#define bswaptls(s) bswap32s(s)
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#else
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#define tswapl(s) tswap64(s)
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#define tswapls(s) tswap64s((uint64_t *)(s))
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#define bswaptls(s) bswap64s(s)
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#endif
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/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
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endian ! */
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typedef union { |
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double d;
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#if defined(WORDS_BIGENDIAN) || (defined(__arm__) && !defined(__VFP_FP__))
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struct {
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uint32_t upper; |
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uint32_t lower; |
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} l; |
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#else
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struct {
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uint32_t lower; |
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uint32_t upper; |
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} l; |
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#endif
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uint64_t ll; |
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} CPU_DoubleU; |
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/* CPU memory access without any memory or io remapping */
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/*
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* the generic syntax for the memory accesses is:
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*
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* load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
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*
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* store: st{type}{size}{endian}_{access_type}(ptr, val)
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*
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* type is:
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* (empty): integer access
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* f : float access
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*
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* sign is:
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* (empty): for floats or 32 bit size
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* u : unsigned
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* s : signed
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*
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* size is:
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* b: 8 bits
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* w: 16 bits
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* l: 32 bits
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* q: 64 bits
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*
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* endian is:
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* (empty): target cpu endianness or 8 bit access
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* r : reversed target cpu endianness (not implemented yet)
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* be : big endian (not implemented yet)
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* le : little endian (not implemented yet)
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*
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* access_type is:
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* raw : host memory access
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* user : user mode access using soft MMU
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* kernel : kernel mode access using soft MMU
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*/
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static inline int ldub_p(void *ptr) |
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{ |
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return *(uint8_t *)ptr;
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} |
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static inline int ldsb_p(void *ptr) |
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{ |
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return *(int8_t *)ptr;
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} |
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static inline void stb_p(void *ptr, int v) |
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{ |
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*(uint8_t *)ptr = v; |
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} |
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/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
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kernel handles unaligned load/stores may give better results, but
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it is a system wide setting : bad */
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#if !defined(TARGET_WORDS_BIGENDIAN) && (defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED))
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/* conservative code for little endian unaligned accesses */
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static inline int lduw_p(void *ptr) |
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{ |
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#ifdef __powerpc__
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int val;
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__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
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return val;
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#else
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uint8_t *p = ptr; |
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return p[0] | (p[1] << 8); |
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#endif
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} |
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static inline int ldsw_p(void *ptr) |
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{ |
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#ifdef __powerpc__
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int val;
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__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
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return (int16_t)val;
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#else
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uint8_t *p = ptr; |
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return (int16_t)(p[0] | (p[1] << 8)); |
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#endif
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} |
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static inline int ldl_p(void *ptr) |
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{ |
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#ifdef __powerpc__
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int val;
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__asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
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return val;
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#else
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uint8_t *p = ptr; |
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return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); |
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#endif
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} |
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static inline uint64_t ldq_p(void *ptr) |
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{ |
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uint8_t *p = ptr; |
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uint32_t v1, v2; |
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v1 = ldl_p(p); |
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v2 = ldl_p(p + 4);
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return v1 | ((uint64_t)v2 << 32); |
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} |
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static inline void stw_p(void *ptr, int v) |
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{ |
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#ifdef __powerpc__
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__asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); |
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#else
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uint8_t *p = ptr; |
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p[0] = v;
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p[1] = v >> 8; |
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#endif
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} |
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static inline void stl_p(void *ptr, int v) |
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{ |
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#ifdef __powerpc__
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__asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); |
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#else
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uint8_t *p = ptr; |
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p[0] = v;
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p[1] = v >> 8; |
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p[2] = v >> 16; |
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p[3] = v >> 24; |
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#endif
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} |
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static inline void stq_p(void *ptr, uint64_t v) |
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{ |
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uint8_t *p = ptr; |
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stl_p(p, (uint32_t)v); |
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stl_p(p + 4, v >> 32); |
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} |
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/* float access */
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static inline float ldfl_p(void *ptr) |
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{ |
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union {
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float f;
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uint32_t i; |
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} u; |
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u.i = ldl_p(ptr); |
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return u.f;
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} |
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static inline void stfl_p(void *ptr, float v) |
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{ |
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union {
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float f;
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uint32_t i; |
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} u; |
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u.f = v; |
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stl_p(ptr, u.i); |
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} |
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static inline double ldfq_p(void *ptr) |
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{ |
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CPU_DoubleU u; |
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u.l.lower = ldl_p(ptr); |
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u.l.upper = ldl_p(ptr + 4);
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return u.d;
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} |
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static inline void stfq_p(void *ptr, double v) |
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{ |
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CPU_DoubleU u; |
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u.d = v; |
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stl_p(ptr, u.l.lower); |
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stl_p(ptr + 4, u.l.upper);
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} |
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#elif defined(TARGET_WORDS_BIGENDIAN) && (!defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED))
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static inline int lduw_p(void *ptr) |
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{ |
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#if defined(__i386__)
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int val;
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asm volatile ("movzwl %1, %0\n" |
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"xchgb %b0, %h0\n"
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: "=q" (val)
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: "m" (*(uint16_t *)ptr));
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return val;
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#else
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uint8_t *b = (uint8_t *) ptr; |
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return ((b[0] << 8) | b[1]); |
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#endif
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} |
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static inline int ldsw_p(void *ptr) |
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{ |
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#if defined(__i386__)
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int val;
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asm volatile ("movzwl %1, %0\n" |
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"xchgb %b0, %h0\n"
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: "=q" (val)
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: "m" (*(uint16_t *)ptr));
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return (int16_t)val;
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#else
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uint8_t *b = (uint8_t *) ptr; |
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return (int16_t)((b[0] << 8) | b[1]); |
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#endif
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} |
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static inline int ldl_p(void *ptr) |
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{ |
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#if defined(__i386__) || defined(__x86_64__)
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int val;
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asm volatile ("movl %1, %0\n" |
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"bswap %0\n"
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: "=r" (val)
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: "m" (*(uint32_t *)ptr));
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return val;
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#else
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uint8_t *b = (uint8_t *) ptr; |
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return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; |
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#endif
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} |
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static inline uint64_t ldq_p(void *ptr) |
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{ |
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uint32_t a,b; |
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a = ldl_p(ptr); |
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b = ldl_p(ptr+4);
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return (((uint64_t)a<<32)|b); |
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} |
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static inline void stw_p(void *ptr, int v) |
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{ |
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#if defined(__i386__)
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asm volatile ("xchgb %b0, %h0\n" |
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"movw %w0, %1\n"
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: "=q" (v)
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: "m" (*(uint16_t *)ptr), "0" (v)); |
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#else
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uint8_t *d = (uint8_t *) ptr; |
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d[0] = v >> 8; |
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d[1] = v;
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#endif
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} |
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static inline void stl_p(void *ptr, int v) |
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{ |
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#if defined(__i386__) || defined(__x86_64__)
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asm volatile ("bswap %0\n" |
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"movl %0, %1\n"
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: "=r" (v)
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: "m" (*(uint32_t *)ptr), "0" (v)); |
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#else
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uint8_t *d = (uint8_t *) ptr; |
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d[0] = v >> 24; |
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d[1] = v >> 16; |
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d[2] = v >> 8; |
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d[3] = v;
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#endif
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} |
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static inline void stq_p(void *ptr, uint64_t v) |
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{ |
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stl_p(ptr, v >> 32);
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stl_p(ptr + 4, v);
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} |
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/* float access */
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static inline float ldfl_p(void *ptr) |
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{ |
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union {
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float f;
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uint32_t i; |
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} u; |
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u.i = ldl_p(ptr); |
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return u.f;
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} |
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static inline void stfl_p(void *ptr, float v) |
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{ |
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union {
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float f;
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uint32_t i; |
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} u; |
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u.f = v; |
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stl_p(ptr, u.i); |
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} |
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static inline double ldfq_p(void *ptr) |
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{ |
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CPU_DoubleU u; |
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u.l.upper = ldl_p(ptr); |
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u.l.lower = ldl_p(ptr + 4);
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return u.d;
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} |
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static inline void stfq_p(void *ptr, double v) |
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{ |
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CPU_DoubleU u; |
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u.d = v; |
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stl_p(ptr, u.l.upper); |
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stl_p(ptr + 4, u.l.lower);
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} |
435 |
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#else
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static inline int lduw_p(void *ptr) |
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{ |
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return *(uint16_t *)ptr;
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} |
442 |
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static inline int ldsw_p(void *ptr) |
444 |
{ |
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return *(int16_t *)ptr;
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} |
447 |
|
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static inline int ldl_p(void *ptr) |
449 |
{ |
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return *(uint32_t *)ptr;
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} |
452 |
|
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static inline uint64_t ldq_p(void *ptr) |
454 |
{ |
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return *(uint64_t *)ptr;
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} |
457 |
|
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static inline void stw_p(void *ptr, int v) |
459 |
{ |
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*(uint16_t *)ptr = v; |
461 |
} |
462 |
|
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static inline void stl_p(void *ptr, int v) |
464 |
{ |
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*(uint32_t *)ptr = v; |
466 |
} |
467 |
|
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static inline void stq_p(void *ptr, uint64_t v) |
469 |
{ |
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*(uint64_t *)ptr = v; |
471 |
} |
472 |
|
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/* float access */
|
474 |
|
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static inline float ldfl_p(void *ptr) |
476 |
{ |
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return *(float *)ptr; |
478 |
} |
479 |
|
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static inline double ldfq_p(void *ptr) |
481 |
{ |
482 |
return *(double *)ptr; |
483 |
} |
484 |
|
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static inline void stfl_p(void *ptr, float v) |
486 |
{ |
487 |
*(float *)ptr = v;
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} |
489 |
|
490 |
static inline void stfq_p(void *ptr, double v) |
491 |
{ |
492 |
*(double *)ptr = v;
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} |
494 |
#endif
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495 |
|
496 |
/* MMU memory access macros */
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497 |
|
498 |
/* NOTE: we use double casts if pointers and target_ulong have
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different sizes */
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#define ldub_raw(p) ldub_p((uint8_t *)(long)(p)) |
501 |
#define ldsb_raw(p) ldsb_p((uint8_t *)(long)(p)) |
502 |
#define lduw_raw(p) lduw_p((uint8_t *)(long)(p)) |
503 |
#define ldsw_raw(p) ldsw_p((uint8_t *)(long)(p)) |
504 |
#define ldl_raw(p) ldl_p((uint8_t *)(long)(p)) |
505 |
#define ldq_raw(p) ldq_p((uint8_t *)(long)(p)) |
506 |
#define ldfl_raw(p) ldfl_p((uint8_t *)(long)(p)) |
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#define ldfq_raw(p) ldfq_p((uint8_t *)(long)(p)) |
508 |
#define stb_raw(p, v) stb_p((uint8_t *)(long)(p), v) |
509 |
#define stw_raw(p, v) stw_p((uint8_t *)(long)(p), v) |
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#define stl_raw(p, v) stl_p((uint8_t *)(long)(p), v) |
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#define stq_raw(p, v) stq_p((uint8_t *)(long)(p), v) |
512 |
#define stfl_raw(p, v) stfl_p((uint8_t *)(long)(p), v) |
513 |
#define stfq_raw(p, v) stfq_p((uint8_t *)(long)(p), v) |
514 |
|
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|
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#if defined(CONFIG_USER_ONLY)
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|
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/* if user mode, no other memory access functions */
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#define ldub(p) ldub_raw(p)
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#define ldsb(p) ldsb_raw(p)
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#define lduw(p) lduw_raw(p)
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#define ldsw(p) ldsw_raw(p)
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#define ldl(p) ldl_raw(p)
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#define ldq(p) ldq_raw(p)
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#define ldfl(p) ldfl_raw(p)
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#define ldfq(p) ldfq_raw(p)
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527 |
#define stb(p, v) stb_raw(p, v)
|
528 |
#define stw(p, v) stw_raw(p, v)
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#define stl(p, v) stl_raw(p, v)
|
530 |
#define stq(p, v) stq_raw(p, v)
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#define stfl(p, v) stfl_raw(p, v)
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532 |
#define stfq(p, v) stfq_raw(p, v)
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533 |
|
534 |
#define ldub_code(p) ldub_raw(p)
|
535 |
#define ldsb_code(p) ldsb_raw(p)
|
536 |
#define lduw_code(p) lduw_raw(p)
|
537 |
#define ldsw_code(p) ldsw_raw(p)
|
538 |
#define ldl_code(p) ldl_raw(p)
|
539 |
|
540 |
#define ldub_kernel(p) ldub_raw(p)
|
541 |
#define ldsb_kernel(p) ldsb_raw(p)
|
542 |
#define lduw_kernel(p) lduw_raw(p)
|
543 |
#define ldsw_kernel(p) ldsw_raw(p)
|
544 |
#define ldl_kernel(p) ldl_raw(p)
|
545 |
#define ldfl_kernel(p) ldfl_raw(p)
|
546 |
#define ldfq_kernel(p) ldfq_raw(p)
|
547 |
#define stb_kernel(p, v) stb_raw(p, v)
|
548 |
#define stw_kernel(p, v) stw_raw(p, v)
|
549 |
#define stl_kernel(p, v) stl_raw(p, v)
|
550 |
#define stq_kernel(p, v) stq_raw(p, v)
|
551 |
#define stfl_kernel(p, v) stfl_raw(p, v)
|
552 |
#define stfq_kernel(p, vt) stfq_raw(p, v)
|
553 |
|
554 |
#endif /* defined(CONFIG_USER_ONLY) */ |
555 |
|
556 |
/* page related stuff */
|
557 |
|
558 |
#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
559 |
#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
560 |
#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) |
561 |
|
562 |
extern unsigned long qemu_real_host_page_size; |
563 |
extern unsigned long qemu_host_page_bits; |
564 |
extern unsigned long qemu_host_page_size; |
565 |
extern unsigned long qemu_host_page_mask; |
566 |
|
567 |
#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
568 |
|
569 |
/* same as PROT_xxx */
|
570 |
#define PAGE_READ 0x0001 |
571 |
#define PAGE_WRITE 0x0002 |
572 |
#define PAGE_EXEC 0x0004 |
573 |
#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
|
574 |
#define PAGE_VALID 0x0008 |
575 |
/* original state of the write flag (used when tracking self-modifying
|
576 |
code */
|
577 |
#define PAGE_WRITE_ORG 0x0010 |
578 |
|
579 |
void page_dump(FILE *f);
|
580 |
int page_get_flags(unsigned long address); |
581 |
void page_set_flags(unsigned long start, unsigned long end, int flags); |
582 |
void page_unprotect_range(uint8_t *data, unsigned long data_size); |
583 |
|
584 |
#define SINGLE_CPU_DEFINES
|
585 |
#ifdef SINGLE_CPU_DEFINES
|
586 |
|
587 |
#if defined(TARGET_I386)
|
588 |
|
589 |
#define CPUState CPUX86State
|
590 |
#define cpu_init cpu_x86_init
|
591 |
#define cpu_exec cpu_x86_exec
|
592 |
#define cpu_gen_code cpu_x86_gen_code
|
593 |
#define cpu_signal_handler cpu_x86_signal_handler
|
594 |
|
595 |
#elif defined(TARGET_ARM)
|
596 |
|
597 |
#define CPUState CPUARMState
|
598 |
#define cpu_init cpu_arm_init
|
599 |
#define cpu_exec cpu_arm_exec
|
600 |
#define cpu_gen_code cpu_arm_gen_code
|
601 |
#define cpu_signal_handler cpu_arm_signal_handler
|
602 |
|
603 |
#elif defined(TARGET_SPARC)
|
604 |
|
605 |
#define CPUState CPUSPARCState
|
606 |
#define cpu_init cpu_sparc_init
|
607 |
#define cpu_exec cpu_sparc_exec
|
608 |
#define cpu_gen_code cpu_sparc_gen_code
|
609 |
#define cpu_signal_handler cpu_sparc_signal_handler
|
610 |
|
611 |
#elif defined(TARGET_PPC)
|
612 |
|
613 |
#define CPUState CPUPPCState
|
614 |
#define cpu_init cpu_ppc_init
|
615 |
#define cpu_exec cpu_ppc_exec
|
616 |
#define cpu_gen_code cpu_ppc_gen_code
|
617 |
#define cpu_signal_handler cpu_ppc_signal_handler
|
618 |
|
619 |
#else
|
620 |
|
621 |
#error unsupported target CPU
|
622 |
|
623 |
#endif
|
624 |
|
625 |
#endif /* SINGLE_CPU_DEFINES */ |
626 |
|
627 |
void cpu_dump_state(CPUState *env, FILE *f,
|
628 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
629 |
int flags);
|
630 |
|
631 |
void cpu_abort(CPUState *env, const char *fmt, ...); |
632 |
extern CPUState *cpu_single_env;
|
633 |
extern int code_copy_enabled; |
634 |
|
635 |
#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */ |
636 |
#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */ |
637 |
#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */ |
638 |
#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ |
639 |
void cpu_interrupt(CPUState *s, int mask); |
640 |
void cpu_reset_interrupt(CPUState *env, int mask); |
641 |
|
642 |
int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
|
643 |
int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
|
644 |
void cpu_single_step(CPUState *env, int enabled); |
645 |
void cpu_reset(CPUState *s);
|
646 |
|
647 |
/* Return the physical page corresponding to a virtual one. Use it
|
648 |
only for debugging because no protection checks are done. Return -1
|
649 |
if no page found. */
|
650 |
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr); |
651 |
|
652 |
#define CPU_LOG_TB_OUT_ASM (1 << 0) |
653 |
#define CPU_LOG_TB_IN_ASM (1 << 1) |
654 |
#define CPU_LOG_TB_OP (1 << 2) |
655 |
#define CPU_LOG_TB_OP_OPT (1 << 3) |
656 |
#define CPU_LOG_INT (1 << 4) |
657 |
#define CPU_LOG_EXEC (1 << 5) |
658 |
#define CPU_LOG_PCALL (1 << 6) |
659 |
#define CPU_LOG_IOPORT (1 << 7) |
660 |
#define CPU_LOG_TB_CPU (1 << 8) |
661 |
|
662 |
/* define log items */
|
663 |
typedef struct CPULogItem { |
664 |
int mask;
|
665 |
const char *name; |
666 |
const char *help; |
667 |
} CPULogItem; |
668 |
|
669 |
extern CPULogItem cpu_log_items[];
|
670 |
|
671 |
void cpu_set_log(int log_flags); |
672 |
void cpu_set_log_filename(const char *filename); |
673 |
int cpu_str_to_log_mask(const char *str); |
674 |
|
675 |
/* IO ports API */
|
676 |
|
677 |
/* NOTE: as these functions may be even used when there is an isa
|
678 |
brige on non x86 targets, we always defined them */
|
679 |
#ifndef NO_CPU_IO_DEFS
|
680 |
void cpu_outb(CPUState *env, int addr, int val); |
681 |
void cpu_outw(CPUState *env, int addr, int val); |
682 |
void cpu_outl(CPUState *env, int addr, int val); |
683 |
int cpu_inb(CPUState *env, int addr); |
684 |
int cpu_inw(CPUState *env, int addr); |
685 |
int cpu_inl(CPUState *env, int addr); |
686 |
#endif
|
687 |
|
688 |
/* memory API */
|
689 |
|
690 |
extern int phys_ram_size; |
691 |
extern int phys_ram_fd; |
692 |
extern uint8_t *phys_ram_base;
|
693 |
extern uint8_t *phys_ram_dirty;
|
694 |
|
695 |
/* physical memory access */
|
696 |
#define IO_MEM_NB_ENTRIES 256 |
697 |
#define TLB_INVALID_MASK (1 << 3) |
698 |
#define IO_MEM_SHIFT 4 |
699 |
|
700 |
#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */ |
701 |
#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ |
702 |
#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) |
703 |
#define IO_MEM_CODE (3 << IO_MEM_SHIFT) /* used internally, never use directly */ |
704 |
#define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */ |
705 |
|
706 |
typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); |
707 |
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); |
708 |
|
709 |
void cpu_register_physical_memory(target_phys_addr_t start_addr,
|
710 |
unsigned long size, |
711 |
unsigned long phys_offset); |
712 |
int cpu_register_io_memory(int io_index, |
713 |
CPUReadMemoryFunc **mem_read, |
714 |
CPUWriteMemoryFunc **mem_write, |
715 |
void *opaque);
|
716 |
CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
|
717 |
CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
|
718 |
|
719 |
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
|
720 |
int len, int is_write); |
721 |
static inline void cpu_physical_memory_read(target_phys_addr_t addr, |
722 |
uint8_t *buf, int len)
|
723 |
{ |
724 |
cpu_physical_memory_rw(addr, buf, len, 0);
|
725 |
} |
726 |
static inline void cpu_physical_memory_write(target_phys_addr_t addr, |
727 |
const uint8_t *buf, int len) |
728 |
{ |
729 |
cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
|
730 |
} |
731 |
uint32_t ldl_phys(target_phys_addr_t addr); |
732 |
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
|
733 |
void stl_phys(target_phys_addr_t addr, uint32_t val);
|
734 |
|
735 |
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
736 |
uint8_t *buf, int len, int is_write); |
737 |
|
738 |
#define VGA_DIRTY_FLAG 0x01 |
739 |
|
740 |
/* read dirty bit (return 0 or 1) */
|
741 |
static inline int cpu_physical_memory_is_dirty(target_ulong addr) |
742 |
{ |
743 |
return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; |
744 |
} |
745 |
|
746 |
static inline int cpu_physical_memory_get_dirty(target_ulong addr, |
747 |
int dirty_flags)
|
748 |
{ |
749 |
return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
|
750 |
} |
751 |
|
752 |
static inline void cpu_physical_memory_set_dirty(target_ulong addr) |
753 |
{ |
754 |
phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
|
755 |
} |
756 |
|
757 |
void cpu_physical_memory_reset_dirty(target_ulong start, target_ulong end,
|
758 |
int dirty_flags);
|
759 |
|
760 |
void dump_exec_info(FILE *f,
|
761 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
762 |
|
763 |
#endif /* CPU_ALL_H */ |