root / opc-i386.h @ b03c60f3
History | View | Annotate | Download (8.5 kB)
1 | dc99065b | bellard | DEF(end) |
---|---|---|---|
2 | dc99065b | bellard | DEF(movl_A0_EAX) |
3 | dc99065b | bellard | DEF(addl_A0_EAX) |
4 | dc99065b | bellard | DEF(addl_A0_EAX_s1) |
5 | dc99065b | bellard | DEF(addl_A0_EAX_s2) |
6 | dc99065b | bellard | DEF(addl_A0_EAX_s3) |
7 | dc99065b | bellard | DEF(movl_T0_EAX) |
8 | dc99065b | bellard | DEF(movl_T1_EAX) |
9 | dc99065b | bellard | DEF(movh_T0_EAX) |
10 | dc99065b | bellard | DEF(movh_T1_EAX) |
11 | dc99065b | bellard | DEF(movl_EAX_T0) |
12 | dc99065b | bellard | DEF(movl_EAX_T1) |
13 | dc99065b | bellard | DEF(movl_EAX_A0) |
14 | dc99065b | bellard | DEF(cmovw_EAX_T1_T0) |
15 | dc99065b | bellard | DEF(cmovl_EAX_T1_T0) |
16 | dc99065b | bellard | DEF(movw_EAX_T0) |
17 | dc99065b | bellard | DEF(movw_EAX_T1) |
18 | dc99065b | bellard | DEF(movw_EAX_A0) |
19 | dc99065b | bellard | DEF(movb_EAX_T0) |
20 | dc99065b | bellard | DEF(movh_EAX_T0) |
21 | dc99065b | bellard | DEF(movb_EAX_T1) |
22 | dc99065b | bellard | DEF(movh_EAX_T1) |
23 | dc99065b | bellard | DEF(movl_A0_ECX) |
24 | dc99065b | bellard | DEF(addl_A0_ECX) |
25 | dc99065b | bellard | DEF(addl_A0_ECX_s1) |
26 | dc99065b | bellard | DEF(addl_A0_ECX_s2) |
27 | dc99065b | bellard | DEF(addl_A0_ECX_s3) |
28 | dc99065b | bellard | DEF(movl_T0_ECX) |
29 | dc99065b | bellard | DEF(movl_T1_ECX) |
30 | dc99065b | bellard | DEF(movh_T0_ECX) |
31 | dc99065b | bellard | DEF(movh_T1_ECX) |
32 | dc99065b | bellard | DEF(movl_ECX_T0) |
33 | dc99065b | bellard | DEF(movl_ECX_T1) |
34 | dc99065b | bellard | DEF(movl_ECX_A0) |
35 | dc99065b | bellard | DEF(cmovw_ECX_T1_T0) |
36 | dc99065b | bellard | DEF(cmovl_ECX_T1_T0) |
37 | dc99065b | bellard | DEF(movw_ECX_T0) |
38 | dc99065b | bellard | DEF(movw_ECX_T1) |
39 | dc99065b | bellard | DEF(movw_ECX_A0) |
40 | dc99065b | bellard | DEF(movb_ECX_T0) |
41 | dc99065b | bellard | DEF(movh_ECX_T0) |
42 | dc99065b | bellard | DEF(movb_ECX_T1) |
43 | dc99065b | bellard | DEF(movh_ECX_T1) |
44 | dc99065b | bellard | DEF(movl_A0_EDX) |
45 | dc99065b | bellard | DEF(addl_A0_EDX) |
46 | dc99065b | bellard | DEF(addl_A0_EDX_s1) |
47 | dc99065b | bellard | DEF(addl_A0_EDX_s2) |
48 | dc99065b | bellard | DEF(addl_A0_EDX_s3) |
49 | dc99065b | bellard | DEF(movl_T0_EDX) |
50 | dc99065b | bellard | DEF(movl_T1_EDX) |
51 | dc99065b | bellard | DEF(movh_T0_EDX) |
52 | dc99065b | bellard | DEF(movh_T1_EDX) |
53 | dc99065b | bellard | DEF(movl_EDX_T0) |
54 | dc99065b | bellard | DEF(movl_EDX_T1) |
55 | dc99065b | bellard | DEF(movl_EDX_A0) |
56 | dc99065b | bellard | DEF(cmovw_EDX_T1_T0) |
57 | dc99065b | bellard | DEF(cmovl_EDX_T1_T0) |
58 | dc99065b | bellard | DEF(movw_EDX_T0) |
59 | dc99065b | bellard | DEF(movw_EDX_T1) |
60 | dc99065b | bellard | DEF(movw_EDX_A0) |
61 | dc99065b | bellard | DEF(movb_EDX_T0) |
62 | dc99065b | bellard | DEF(movh_EDX_T0) |
63 | dc99065b | bellard | DEF(movb_EDX_T1) |
64 | dc99065b | bellard | DEF(movh_EDX_T1) |
65 | dc99065b | bellard | DEF(movl_A0_EBX) |
66 | dc99065b | bellard | DEF(addl_A0_EBX) |
67 | dc99065b | bellard | DEF(addl_A0_EBX_s1) |
68 | dc99065b | bellard | DEF(addl_A0_EBX_s2) |
69 | dc99065b | bellard | DEF(addl_A0_EBX_s3) |
70 | dc99065b | bellard | DEF(movl_T0_EBX) |
71 | dc99065b | bellard | DEF(movl_T1_EBX) |
72 | dc99065b | bellard | DEF(movh_T0_EBX) |
73 | dc99065b | bellard | DEF(movh_T1_EBX) |
74 | dc99065b | bellard | DEF(movl_EBX_T0) |
75 | dc99065b | bellard | DEF(movl_EBX_T1) |
76 | dc99065b | bellard | DEF(movl_EBX_A0) |
77 | dc99065b | bellard | DEF(cmovw_EBX_T1_T0) |
78 | dc99065b | bellard | DEF(cmovl_EBX_T1_T0) |
79 | dc99065b | bellard | DEF(movw_EBX_T0) |
80 | dc99065b | bellard | DEF(movw_EBX_T1) |
81 | dc99065b | bellard | DEF(movw_EBX_A0) |
82 | dc99065b | bellard | DEF(movb_EBX_T0) |
83 | dc99065b | bellard | DEF(movh_EBX_T0) |
84 | dc99065b | bellard | DEF(movb_EBX_T1) |
85 | dc99065b | bellard | DEF(movh_EBX_T1) |
86 | dc99065b | bellard | DEF(movl_A0_ESP) |
87 | dc99065b | bellard | DEF(addl_A0_ESP) |
88 | dc99065b | bellard | DEF(addl_A0_ESP_s1) |
89 | dc99065b | bellard | DEF(addl_A0_ESP_s2) |
90 | dc99065b | bellard | DEF(addl_A0_ESP_s3) |
91 | dc99065b | bellard | DEF(movl_T0_ESP) |
92 | dc99065b | bellard | DEF(movl_T1_ESP) |
93 | dc99065b | bellard | DEF(movh_T0_ESP) |
94 | dc99065b | bellard | DEF(movh_T1_ESP) |
95 | dc99065b | bellard | DEF(movl_ESP_T0) |
96 | dc99065b | bellard | DEF(movl_ESP_T1) |
97 | dc99065b | bellard | DEF(movl_ESP_A0) |
98 | dc99065b | bellard | DEF(cmovw_ESP_T1_T0) |
99 | dc99065b | bellard | DEF(cmovl_ESP_T1_T0) |
100 | dc99065b | bellard | DEF(movw_ESP_T0) |
101 | dc99065b | bellard | DEF(movw_ESP_T1) |
102 | dc99065b | bellard | DEF(movw_ESP_A0) |
103 | dc99065b | bellard | DEF(movb_ESP_T0) |
104 | dc99065b | bellard | DEF(movh_ESP_T0) |
105 | dc99065b | bellard | DEF(movb_ESP_T1) |
106 | dc99065b | bellard | DEF(movh_ESP_T1) |
107 | dc99065b | bellard | DEF(movl_A0_EBP) |
108 | dc99065b | bellard | DEF(addl_A0_EBP) |
109 | dc99065b | bellard | DEF(addl_A0_EBP_s1) |
110 | dc99065b | bellard | DEF(addl_A0_EBP_s2) |
111 | dc99065b | bellard | DEF(addl_A0_EBP_s3) |
112 | dc99065b | bellard | DEF(movl_T0_EBP) |
113 | dc99065b | bellard | DEF(movl_T1_EBP) |
114 | dc99065b | bellard | DEF(movh_T0_EBP) |
115 | dc99065b | bellard | DEF(movh_T1_EBP) |
116 | dc99065b | bellard | DEF(movl_EBP_T0) |
117 | dc99065b | bellard | DEF(movl_EBP_T1) |
118 | dc99065b | bellard | DEF(movl_EBP_A0) |
119 | dc99065b | bellard | DEF(cmovw_EBP_T1_T0) |
120 | dc99065b | bellard | DEF(cmovl_EBP_T1_T0) |
121 | dc99065b | bellard | DEF(movw_EBP_T0) |
122 | dc99065b | bellard | DEF(movw_EBP_T1) |
123 | dc99065b | bellard | DEF(movw_EBP_A0) |
124 | dc99065b | bellard | DEF(movb_EBP_T0) |
125 | dc99065b | bellard | DEF(movh_EBP_T0) |
126 | dc99065b | bellard | DEF(movb_EBP_T1) |
127 | dc99065b | bellard | DEF(movh_EBP_T1) |
128 | dc99065b | bellard | DEF(movl_A0_ESI) |
129 | dc99065b | bellard | DEF(addl_A0_ESI) |
130 | dc99065b | bellard | DEF(addl_A0_ESI_s1) |
131 | dc99065b | bellard | DEF(addl_A0_ESI_s2) |
132 | dc99065b | bellard | DEF(addl_A0_ESI_s3) |
133 | dc99065b | bellard | DEF(movl_T0_ESI) |
134 | dc99065b | bellard | DEF(movl_T1_ESI) |
135 | dc99065b | bellard | DEF(movh_T0_ESI) |
136 | dc99065b | bellard | DEF(movh_T1_ESI) |
137 | dc99065b | bellard | DEF(movl_ESI_T0) |
138 | dc99065b | bellard | DEF(movl_ESI_T1) |
139 | dc99065b | bellard | DEF(movl_ESI_A0) |
140 | dc99065b | bellard | DEF(cmovw_ESI_T1_T0) |
141 | dc99065b | bellard | DEF(cmovl_ESI_T1_T0) |
142 | dc99065b | bellard | DEF(movw_ESI_T0) |
143 | dc99065b | bellard | DEF(movw_ESI_T1) |
144 | dc99065b | bellard | DEF(movw_ESI_A0) |
145 | dc99065b | bellard | DEF(movb_ESI_T0) |
146 | dc99065b | bellard | DEF(movh_ESI_T0) |
147 | dc99065b | bellard | DEF(movb_ESI_T1) |
148 | dc99065b | bellard | DEF(movh_ESI_T1) |
149 | dc99065b | bellard | DEF(movl_A0_EDI) |
150 | dc99065b | bellard | DEF(addl_A0_EDI) |
151 | dc99065b | bellard | DEF(addl_A0_EDI_s1) |
152 | dc99065b | bellard | DEF(addl_A0_EDI_s2) |
153 | dc99065b | bellard | DEF(addl_A0_EDI_s3) |
154 | dc99065b | bellard | DEF(movl_T0_EDI) |
155 | dc99065b | bellard | DEF(movl_T1_EDI) |
156 | dc99065b | bellard | DEF(movh_T0_EDI) |
157 | dc99065b | bellard | DEF(movh_T1_EDI) |
158 | dc99065b | bellard | DEF(movl_EDI_T0) |
159 | dc99065b | bellard | DEF(movl_EDI_T1) |
160 | dc99065b | bellard | DEF(movl_EDI_A0) |
161 | dc99065b | bellard | DEF(cmovw_EDI_T1_T0) |
162 | dc99065b | bellard | DEF(cmovl_EDI_T1_T0) |
163 | dc99065b | bellard | DEF(movw_EDI_T0) |
164 | dc99065b | bellard | DEF(movw_EDI_T1) |
165 | dc99065b | bellard | DEF(movw_EDI_A0) |
166 | dc99065b | bellard | DEF(movb_EDI_T0) |
167 | dc99065b | bellard | DEF(movh_EDI_T0) |
168 | dc99065b | bellard | DEF(movb_EDI_T1) |
169 | dc99065b | bellard | DEF(movh_EDI_T1) |
170 | dc99065b | bellard | DEF(addl_T0_T1_cc) |
171 | dc99065b | bellard | DEF(orl_T0_T1_cc) |
172 | dc99065b | bellard | DEF(andl_T0_T1_cc) |
173 | dc99065b | bellard | DEF(subl_T0_T1_cc) |
174 | dc99065b | bellard | DEF(xorl_T0_T1_cc) |
175 | dc99065b | bellard | DEF(cmpl_T0_T1_cc) |
176 | dc99065b | bellard | DEF(negl_T0_cc) |
177 | dc99065b | bellard | DEF(incl_T0_cc) |
178 | dc99065b | bellard | DEF(decl_T0_cc) |
179 | dc99065b | bellard | DEF(testl_T0_T1_cc) |
180 | dc99065b | bellard | DEF(addl_T0_T1) |
181 | dc99065b | bellard | DEF(orl_T0_T1) |
182 | dc99065b | bellard | DEF(andl_T0_T1) |
183 | dc99065b | bellard | DEF(subl_T0_T1) |
184 | dc99065b | bellard | DEF(xorl_T0_T1) |
185 | dc99065b | bellard | DEF(negl_T0) |
186 | dc99065b | bellard | DEF(incl_T0) |
187 | dc99065b | bellard | DEF(decl_T0) |
188 | dc99065b | bellard | DEF(notl_T0) |
189 | dc99065b | bellard | DEF(bswapl_T0) |
190 | dc99065b | bellard | DEF(mulb_AL_T0) |
191 | dc99065b | bellard | DEF(imulb_AL_T0) |
192 | dc99065b | bellard | DEF(mulw_AX_T0) |
193 | dc99065b | bellard | DEF(imulw_AX_T0) |
194 | dc99065b | bellard | DEF(mull_EAX_T0) |
195 | dc99065b | bellard | DEF(imull_EAX_T0) |
196 | dc99065b | bellard | DEF(imulw_T0_T1) |
197 | dc99065b | bellard | DEF(imull_T0_T1) |
198 | dc99065b | bellard | DEF(divb_AL_T0) |
199 | dc99065b | bellard | DEF(idivb_AL_T0) |
200 | dc99065b | bellard | DEF(divw_AX_T0) |
201 | dc99065b | bellard | DEF(idivw_AX_T0) |
202 | dc99065b | bellard | DEF(divl_EAX_T0) |
203 | dc99065b | bellard | DEF(idivl_EAX_T0) |
204 | dc99065b | bellard | DEF(movl_T0_im) |
205 | dab2ed99 | bellard | DEF(addl_T0_im) |
206 | dab2ed99 | bellard | DEF(andl_T0_ffff) |
207 | dab2ed99 | bellard | DEF(movl_T0_T1) |
208 | dc99065b | bellard | DEF(movl_T1_im) |
209 | dab2ed99 | bellard | DEF(addl_T1_im) |
210 | dab2ed99 | bellard | DEF(movl_T1_A0) |
211 | dc99065b | bellard | DEF(movl_A0_im) |
212 | dc99065b | bellard | DEF(addl_A0_im) |
213 | dc99065b | bellard | DEF(andl_A0_ffff) |
214 | dc99065b | bellard | DEF(ldub_T0_A0) |
215 | dc99065b | bellard | DEF(ldsb_T0_A0) |
216 | dc99065b | bellard | DEF(lduw_T0_A0) |
217 | dc99065b | bellard | DEF(ldsw_T0_A0) |
218 | dc99065b | bellard | DEF(ldl_T0_A0) |
219 | dc99065b | bellard | DEF(ldub_T1_A0) |
220 | dc99065b | bellard | DEF(ldsb_T1_A0) |
221 | dc99065b | bellard | DEF(lduw_T1_A0) |
222 | dc99065b | bellard | DEF(ldsw_T1_A0) |
223 | dc99065b | bellard | DEF(ldl_T1_A0) |
224 | dc99065b | bellard | DEF(stb_T0_A0) |
225 | dc99065b | bellard | DEF(stw_T0_A0) |
226 | dc99065b | bellard | DEF(stl_T0_A0) |
227 | dc99065b | bellard | DEF(add_bitw_A0_T1) |
228 | dc99065b | bellard | DEF(add_bitl_A0_T1) |
229 | dc99065b | bellard | DEF(jmp_T0) |
230 | dc99065b | bellard | DEF(jmp_im) |
231 | dc99065b | bellard | DEF(int_im) |
232 | dc99065b | bellard | DEF(int3) |
233 | dc99065b | bellard | DEF(into) |
234 | dc99065b | bellard | DEF(jb_subb) |
235 | dc99065b | bellard | DEF(jz_subb) |
236 | dc99065b | bellard | DEF(jbe_subb) |
237 | dc99065b | bellard | DEF(js_subb) |
238 | dc99065b | bellard | DEF(jl_subb) |
239 | dc99065b | bellard | DEF(jle_subb) |
240 | dc99065b | bellard | DEF(setb_T0_subb) |
241 | dc99065b | bellard | DEF(setz_T0_subb) |
242 | dc99065b | bellard | DEF(setbe_T0_subb) |
243 | dc99065b | bellard | DEF(sets_T0_subb) |
244 | dc99065b | bellard | DEF(setl_T0_subb) |
245 | dc99065b | bellard | DEF(setle_T0_subb) |
246 | dc99065b | bellard | DEF(rolb_T0_T1_cc) |
247 | dc99065b | bellard | DEF(rolb_T0_T1) |
248 | dc99065b | bellard | DEF(rorb_T0_T1_cc) |
249 | dc99065b | bellard | DEF(rorb_T0_T1) |
250 | dc99065b | bellard | DEF(rclb_T0_T1_cc) |
251 | dc99065b | bellard | DEF(rcrb_T0_T1_cc) |
252 | dc99065b | bellard | DEF(shlb_T0_T1_cc) |
253 | dc99065b | bellard | DEF(shlb_T0_T1) |
254 | dc99065b | bellard | DEF(shrb_T0_T1_cc) |
255 | dc99065b | bellard | DEF(shrb_T0_T1) |
256 | dc99065b | bellard | DEF(sarb_T0_T1_cc) |
257 | dc99065b | bellard | DEF(sarb_T0_T1) |
258 | dc99065b | bellard | DEF(adcb_T0_T1_cc) |
259 | dc99065b | bellard | DEF(sbbb_T0_T1_cc) |
260 | dc99065b | bellard | DEF(cmpxchgb_T0_T1_EAX_cc) |
261 | dc99065b | bellard | DEF(movsb) |
262 | dc99065b | bellard | DEF(rep_movsb) |
263 | dc99065b | bellard | DEF(stosb) |
264 | dc99065b | bellard | DEF(rep_stosb) |
265 | dc99065b | bellard | DEF(lodsb) |
266 | dc99065b | bellard | DEF(rep_lodsb) |
267 | dc99065b | bellard | DEF(scasb) |
268 | dc99065b | bellard | DEF(repz_scasb) |
269 | dc99065b | bellard | DEF(repnz_scasb) |
270 | dc99065b | bellard | DEF(cmpsb) |
271 | dc99065b | bellard | DEF(repz_cmpsb) |
272 | dc99065b | bellard | DEF(repnz_cmpsb) |
273 | dc99065b | bellard | DEF(outsb) |
274 | dc99065b | bellard | DEF(rep_outsb) |
275 | dc99065b | bellard | DEF(insb) |
276 | dc99065b | bellard | DEF(rep_insb) |
277 | dc99065b | bellard | DEF(outb_T0_T1) |
278 | dc99065b | bellard | DEF(inb_T0_T1) |
279 | dc99065b | bellard | DEF(jb_subw) |
280 | dc99065b | bellard | DEF(jz_subw) |
281 | dc99065b | bellard | DEF(jbe_subw) |
282 | dc99065b | bellard | DEF(js_subw) |
283 | dc99065b | bellard | DEF(jl_subw) |
284 | dc99065b | bellard | DEF(jle_subw) |
285 | dc99065b | bellard | DEF(loopnzw) |
286 | dc99065b | bellard | DEF(loopzw) |
287 | dc99065b | bellard | DEF(loopw) |
288 | dc99065b | bellard | DEF(jecxzw) |
289 | dc99065b | bellard | DEF(setb_T0_subw) |
290 | dc99065b | bellard | DEF(setz_T0_subw) |
291 | dc99065b | bellard | DEF(setbe_T0_subw) |
292 | dc99065b | bellard | DEF(sets_T0_subw) |
293 | dc99065b | bellard | DEF(setl_T0_subw) |
294 | dc99065b | bellard | DEF(setle_T0_subw) |
295 | dc99065b | bellard | DEF(rolw_T0_T1_cc) |
296 | dc99065b | bellard | DEF(rolw_T0_T1) |
297 | dc99065b | bellard | DEF(rorw_T0_T1_cc) |
298 | dc99065b | bellard | DEF(rorw_T0_T1) |
299 | dc99065b | bellard | DEF(rclw_T0_T1_cc) |
300 | dc99065b | bellard | DEF(rcrw_T0_T1_cc) |
301 | dc99065b | bellard | DEF(shlw_T0_T1_cc) |
302 | dc99065b | bellard | DEF(shlw_T0_T1) |
303 | dc99065b | bellard | DEF(shrw_T0_T1_cc) |
304 | dc99065b | bellard | DEF(shrw_T0_T1) |
305 | dc99065b | bellard | DEF(sarw_T0_T1_cc) |
306 | dc99065b | bellard | DEF(sarw_T0_T1) |
307 | dc99065b | bellard | DEF(shldw_T0_T1_im_cc) |
308 | dc99065b | bellard | DEF(shldw_T0_T1_ECX_cc) |
309 | dc99065b | bellard | DEF(shrdw_T0_T1_im_cc) |
310 | dc99065b | bellard | DEF(shrdw_T0_T1_ECX_cc) |
311 | dc99065b | bellard | DEF(adcw_T0_T1_cc) |
312 | dc99065b | bellard | DEF(sbbw_T0_T1_cc) |
313 | dc99065b | bellard | DEF(cmpxchgw_T0_T1_EAX_cc) |
314 | dc99065b | bellard | DEF(btw_T0_T1_cc) |
315 | dc99065b | bellard | DEF(btsw_T0_T1_cc) |
316 | dc99065b | bellard | DEF(btrw_T0_T1_cc) |
317 | dc99065b | bellard | DEF(btcw_T0_T1_cc) |
318 | dc99065b | bellard | DEF(bsfw_T0_cc) |
319 | dc99065b | bellard | DEF(bsrw_T0_cc) |
320 | dc99065b | bellard | DEF(movsw) |
321 | dc99065b | bellard | DEF(rep_movsw) |
322 | dc99065b | bellard | DEF(stosw) |
323 | dc99065b | bellard | DEF(rep_stosw) |
324 | dc99065b | bellard | DEF(lodsw) |
325 | dc99065b | bellard | DEF(rep_lodsw) |
326 | dc99065b | bellard | DEF(scasw) |
327 | dc99065b | bellard | DEF(repz_scasw) |
328 | dc99065b | bellard | DEF(repnz_scasw) |
329 | dc99065b | bellard | DEF(cmpsw) |
330 | dc99065b | bellard | DEF(repz_cmpsw) |
331 | dc99065b | bellard | DEF(repnz_cmpsw) |
332 | dc99065b | bellard | DEF(outsw) |
333 | dc99065b | bellard | DEF(rep_outsw) |
334 | dc99065b | bellard | DEF(insw) |
335 | dc99065b | bellard | DEF(rep_insw) |
336 | dc99065b | bellard | DEF(outw_T0_T1) |
337 | dc99065b | bellard | DEF(inw_T0_T1) |
338 | dc99065b | bellard | DEF(jb_subl) |
339 | dc99065b | bellard | DEF(jz_subl) |
340 | dc99065b | bellard | DEF(jbe_subl) |
341 | dc99065b | bellard | DEF(js_subl) |
342 | dc99065b | bellard | DEF(jl_subl) |
343 | dc99065b | bellard | DEF(jle_subl) |
344 | dc99065b | bellard | DEF(loopnzl) |
345 | dc99065b | bellard | DEF(loopzl) |
346 | dc99065b | bellard | DEF(loopl) |
347 | dc99065b | bellard | DEF(jecxzl) |
348 | dc99065b | bellard | DEF(setb_T0_subl) |
349 | dc99065b | bellard | DEF(setz_T0_subl) |
350 | dc99065b | bellard | DEF(setbe_T0_subl) |
351 | dc99065b | bellard | DEF(sets_T0_subl) |
352 | dc99065b | bellard | DEF(setl_T0_subl) |
353 | dc99065b | bellard | DEF(setle_T0_subl) |
354 | dc99065b | bellard | DEF(roll_T0_T1_cc) |
355 | dc99065b | bellard | DEF(roll_T0_T1) |
356 | dc99065b | bellard | DEF(rorl_T0_T1_cc) |
357 | dc99065b | bellard | DEF(rorl_T0_T1) |
358 | dc99065b | bellard | DEF(rcll_T0_T1_cc) |
359 | dc99065b | bellard | DEF(rcrl_T0_T1_cc) |
360 | dc99065b | bellard | DEF(shll_T0_T1_cc) |
361 | dc99065b | bellard | DEF(shll_T0_T1) |
362 | dc99065b | bellard | DEF(shrl_T0_T1_cc) |
363 | dc99065b | bellard | DEF(shrl_T0_T1) |
364 | dc99065b | bellard | DEF(sarl_T0_T1_cc) |
365 | dc99065b | bellard | DEF(sarl_T0_T1) |
366 | dc99065b | bellard | DEF(shldl_T0_T1_im_cc) |
367 | dc99065b | bellard | DEF(shldl_T0_T1_ECX_cc) |
368 | dc99065b | bellard | DEF(shrdl_T0_T1_im_cc) |
369 | dc99065b | bellard | DEF(shrdl_T0_T1_ECX_cc) |
370 | dc99065b | bellard | DEF(adcl_T0_T1_cc) |
371 | dc99065b | bellard | DEF(sbbl_T0_T1_cc) |
372 | dc99065b | bellard | DEF(cmpxchgl_T0_T1_EAX_cc) |
373 | dc99065b | bellard | DEF(btl_T0_T1_cc) |
374 | dc99065b | bellard | DEF(btsl_T0_T1_cc) |
375 | dc99065b | bellard | DEF(btrl_T0_T1_cc) |
376 | dc99065b | bellard | DEF(btcl_T0_T1_cc) |
377 | dc99065b | bellard | DEF(bsfl_T0_cc) |
378 | dc99065b | bellard | DEF(bsrl_T0_cc) |
379 | dc99065b | bellard | DEF(movsl) |
380 | dc99065b | bellard | DEF(rep_movsl) |
381 | dc99065b | bellard | DEF(stosl) |
382 | dc99065b | bellard | DEF(rep_stosl) |
383 | dc99065b | bellard | DEF(lodsl) |
384 | dc99065b | bellard | DEF(rep_lodsl) |
385 | dc99065b | bellard | DEF(scasl) |
386 | dc99065b | bellard | DEF(repz_scasl) |
387 | dc99065b | bellard | DEF(repnz_scasl) |
388 | dc99065b | bellard | DEF(cmpsl) |
389 | dc99065b | bellard | DEF(repz_cmpsl) |
390 | dc99065b | bellard | DEF(repnz_cmpsl) |
391 | dc99065b | bellard | DEF(outsl) |
392 | dc99065b | bellard | DEF(rep_outsl) |
393 | dc99065b | bellard | DEF(insl) |
394 | dc99065b | bellard | DEF(rep_insl) |
395 | dc99065b | bellard | DEF(outl_T0_T1) |
396 | dc99065b | bellard | DEF(inl_T0_T1) |
397 | dc99065b | bellard | DEF(movsbl_T0_T0) |
398 | dc99065b | bellard | DEF(movzbl_T0_T0) |
399 | dc99065b | bellard | DEF(movswl_T0_T0) |
400 | dc99065b | bellard | DEF(movzwl_T0_T0) |
401 | dc99065b | bellard | DEF(movswl_EAX_AX) |
402 | dc99065b | bellard | DEF(movsbw_AX_AL) |
403 | dc99065b | bellard | DEF(movslq_EDX_EAX) |
404 | dc99065b | bellard | DEF(movswl_DX_AX) |
405 | dc99065b | bellard | DEF(pushl_T0) |
406 | dab2ed99 | bellard | DEF(pushw_T0) |
407 | dab2ed99 | bellard | DEF(pushl_ss32_T0) |
408 | dab2ed99 | bellard | DEF(pushw_ss32_T0) |
409 | dab2ed99 | bellard | DEF(pushl_ss16_T0) |
410 | dab2ed99 | bellard | DEF(pushw_ss16_T0) |
411 | dc99065b | bellard | DEF(popl_T0) |
412 | dab2ed99 | bellard | DEF(popw_T0) |
413 | dab2ed99 | bellard | DEF(popl_ss32_T0) |
414 | dab2ed99 | bellard | DEF(popw_ss32_T0) |
415 | dab2ed99 | bellard | DEF(popl_ss16_T0) |
416 | dab2ed99 | bellard | DEF(popw_ss16_T0) |
417 | dab2ed99 | bellard | DEF(addl_ESP_4) |
418 | dab2ed99 | bellard | DEF(addl_ESP_2) |
419 | dab2ed99 | bellard | DEF(addw_ESP_4) |
420 | dab2ed99 | bellard | DEF(addw_ESP_2) |
421 | dc99065b | bellard | DEF(addl_ESP_im) |
422 | dab2ed99 | bellard | DEF(addw_ESP_im) |
423 | dc99065b | bellard | DEF(rdtsc) |
424 | dc99065b | bellard | DEF(aam) |
425 | dc99065b | bellard | DEF(aad) |
426 | dc99065b | bellard | DEF(aaa) |
427 | dc99065b | bellard | DEF(aas) |
428 | dc99065b | bellard | DEF(daa) |
429 | dc99065b | bellard | DEF(das) |
430 | dc99065b | bellard | DEF(movl_seg_T0) |
431 | dc99065b | bellard | DEF(movl_T0_seg) |
432 | dc99065b | bellard | DEF(addl_A0_seg) |
433 | dc99065b | bellard | DEF(jo_cc) |
434 | dc99065b | bellard | DEF(jb_cc) |
435 | dc99065b | bellard | DEF(jz_cc) |
436 | dc99065b | bellard | DEF(jbe_cc) |
437 | dc99065b | bellard | DEF(js_cc) |
438 | dc99065b | bellard | DEF(jp_cc) |
439 | dc99065b | bellard | DEF(jl_cc) |
440 | dc99065b | bellard | DEF(jle_cc) |
441 | dc99065b | bellard | DEF(seto_T0_cc) |
442 | dc99065b | bellard | DEF(setb_T0_cc) |
443 | dc99065b | bellard | DEF(setz_T0_cc) |
444 | dc99065b | bellard | DEF(setbe_T0_cc) |
445 | dc99065b | bellard | DEF(sets_T0_cc) |
446 | dc99065b | bellard | DEF(setp_T0_cc) |
447 | dc99065b | bellard | DEF(setl_T0_cc) |
448 | dc99065b | bellard | DEF(setle_T0_cc) |
449 | dc99065b | bellard | DEF(xor_T0_1) |
450 | dc99065b | bellard | DEF(set_cc_op) |
451 | dc99065b | bellard | DEF(movl_eflags_T0) |
452 | dc99065b | bellard | DEF(movb_eflags_T0) |
453 | dc99065b | bellard | DEF(movl_T0_eflags) |
454 | dc99065b | bellard | DEF(cld) |
455 | dc99065b | bellard | DEF(std) |
456 | dc99065b | bellard | DEF(clc) |
457 | dc99065b | bellard | DEF(stc) |
458 | dc99065b | bellard | DEF(cmc) |
459 | dc99065b | bellard | DEF(salc) |
460 | dc99065b | bellard | DEF(flds_FT0_A0) |
461 | dc99065b | bellard | DEF(fldl_FT0_A0) |
462 | dc99065b | bellard | DEF(fild_FT0_A0) |
463 | dc99065b | bellard | DEF(fildl_FT0_A0) |
464 | dc99065b | bellard | DEF(fildll_FT0_A0) |
465 | dc99065b | bellard | DEF(flds_ST0_A0) |
466 | dc99065b | bellard | DEF(fldl_ST0_A0) |
467 | dc99065b | bellard | DEF(fldt_ST0_A0) |
468 | dc99065b | bellard | DEF(fild_ST0_A0) |
469 | dc99065b | bellard | DEF(fildl_ST0_A0) |
470 | dc99065b | bellard | DEF(fildll_ST0_A0) |
471 | dc99065b | bellard | DEF(fsts_ST0_A0) |
472 | dc99065b | bellard | DEF(fstl_ST0_A0) |
473 | dc99065b | bellard | DEF(fstt_ST0_A0) |
474 | dc99065b | bellard | DEF(fist_ST0_A0) |
475 | dc99065b | bellard | DEF(fistl_ST0_A0) |
476 | dc99065b | bellard | DEF(fistll_ST0_A0) |
477 | dc99065b | bellard | DEF(fbld_ST0_A0) |
478 | dc99065b | bellard | DEF(fbst_ST0_A0) |
479 | dc99065b | bellard | DEF(fpush) |
480 | dc99065b | bellard | DEF(fpop) |
481 | dc99065b | bellard | DEF(fdecstp) |
482 | dc99065b | bellard | DEF(fincstp) |
483 | dc99065b | bellard | DEF(fmov_ST0_FT0) |
484 | dc99065b | bellard | DEF(fmov_FT0_STN) |
485 | dc99065b | bellard | DEF(fmov_ST0_STN) |
486 | dc99065b | bellard | DEF(fmov_STN_ST0) |
487 | dc99065b | bellard | DEF(fxchg_ST0_STN) |
488 | dc99065b | bellard | DEF(fcom_ST0_FT0) |
489 | dc99065b | bellard | DEF(fucom_ST0_FT0) |
490 | dc99065b | bellard | DEF(fadd_ST0_FT0) |
491 | dc99065b | bellard | DEF(fmul_ST0_FT0) |
492 | dc99065b | bellard | DEF(fsub_ST0_FT0) |
493 | dc99065b | bellard | DEF(fsubr_ST0_FT0) |
494 | dc99065b | bellard | DEF(fdiv_ST0_FT0) |
495 | dc99065b | bellard | DEF(fdivr_ST0_FT0) |
496 | dc99065b | bellard | DEF(fadd_STN_ST0) |
497 | dc99065b | bellard | DEF(fmul_STN_ST0) |
498 | dc99065b | bellard | DEF(fsub_STN_ST0) |
499 | dc99065b | bellard | DEF(fsubr_STN_ST0) |
500 | dc99065b | bellard | DEF(fdiv_STN_ST0) |
501 | dc99065b | bellard | DEF(fdivr_STN_ST0) |
502 | dc99065b | bellard | DEF(fchs_ST0) |
503 | dc99065b | bellard | DEF(fabs_ST0) |
504 | dc99065b | bellard | DEF(fxam_ST0) |
505 | dc99065b | bellard | DEF(fld1_ST0) |
506 | dc99065b | bellard | DEF(fldl2t_ST0) |
507 | dc99065b | bellard | DEF(fldl2e_ST0) |
508 | dc99065b | bellard | DEF(fldpi_ST0) |
509 | dc99065b | bellard | DEF(fldlg2_ST0) |
510 | dc99065b | bellard | DEF(fldln2_ST0) |
511 | dc99065b | bellard | DEF(fldz_ST0) |
512 | dc99065b | bellard | DEF(fldz_FT0) |
513 | dc99065b | bellard | DEF(f2xm1) |
514 | dc99065b | bellard | DEF(fyl2x) |
515 | dc99065b | bellard | DEF(fptan) |
516 | dc99065b | bellard | DEF(fpatan) |
517 | dc99065b | bellard | DEF(fxtract) |
518 | dc99065b | bellard | DEF(fprem1) |
519 | dc99065b | bellard | DEF(fprem) |
520 | dc99065b | bellard | DEF(fyl2xp1) |
521 | dc99065b | bellard | DEF(fsqrt) |
522 | dc99065b | bellard | DEF(fsincos) |
523 | dc99065b | bellard | DEF(frndint) |
524 | dc99065b | bellard | DEF(fscale) |
525 | dc99065b | bellard | DEF(fsin) |
526 | dc99065b | bellard | DEF(fcos) |
527 | dc99065b | bellard | DEF(fnstsw_A0) |
528 | dc99065b | bellard | DEF(fnstsw_EAX) |
529 | dc99065b | bellard | DEF(fnstcw_A0) |
530 | dc99065b | bellard | DEF(fldcw_A0) |
531 | dc99065b | bellard | DEF(fclex) |
532 | dc99065b | bellard | DEF(fninit) |
533 | 1b6b029e | bellard | DEF(lock) |
534 | 1b6b029e | bellard | DEF(unlock) |