209 |
209 |
(*gen_op_st##width[ctx->mem_idx])(); \
|
210 |
210 |
}
|
211 |
211 |
|
212 |
|
GEN_LD(bu);
|
213 |
|
GEN_ST(b);
|
214 |
|
GEN_LD(wu);
|
215 |
|
GEN_ST(w);
|
216 |
212 |
GEN_LD(l);
|
217 |
213 |
GEN_ST(l);
|
218 |
214 |
GEN_LD(q);
|
219 |
215 |
GEN_ST(q);
|
220 |
|
GEN_LD(q_u);
|
221 |
|
GEN_ST(q_u);
|
222 |
216 |
GEN_LD(l_l);
|
223 |
217 |
GEN_ST(l_c);
|
224 |
218 |
GEN_LD(q_l);
|
... | ... | |
661 |
655 |
/* LDBU */
|
662 |
656 |
if (!(ctx->amask & AMASK_BWX))
|
663 |
657 |
goto invalid_opc;
|
664 |
|
gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);
|
|
658 |
if (likely(ra != 31)) {
|
|
659 |
TCGv addr = tcg_temp_new(TCG_TYPE_I64);
|
|
660 |
if (rb != 31)
|
|
661 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
|
|
662 |
else
|
|
663 |
tcg_gen_movi_i64(addr, disp16);
|
|
664 |
tcg_gen_qemu_ld8u(cpu_ir[ra], addr, ctx->mem_idx);
|
|
665 |
tcg_temp_free(addr);
|
|
666 |
}
|
665 |
667 |
break;
|
666 |
668 |
case 0x0B:
|
667 |
669 |
/* LDQ_U */
|
668 |
|
gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);
|
|
670 |
if (likely(ra != 31)) {
|
|
671 |
TCGv addr = tcg_temp_new(TCG_TYPE_I64);
|
|
672 |
if (rb != 31) {
|
|
673 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
|
|
674 |
tcg_gen_andi_i64(addr, addr, ~0x7);
|
|
675 |
} else
|
|
676 |
tcg_gen_movi_i64(addr, disp16 & ~0x7);
|
|
677 |
tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->mem_idx);
|
|
678 |
tcg_temp_free(addr);
|
|
679 |
}
|
669 |
680 |
break;
|
670 |
681 |
case 0x0C:
|
671 |
682 |
/* LDWU */
|
672 |
683 |
if (!(ctx->amask & AMASK_BWX))
|
673 |
684 |
goto invalid_opc;
|
674 |
|
gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);
|
|
685 |
if (likely(ra != 31)) {
|
|
686 |
TCGv addr = tcg_temp_new(TCG_TYPE_I64);
|
|
687 |
if (rb != 31)
|
|
688 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
|
|
689 |
else
|
|
690 |
tcg_gen_movi_i64(addr, disp16);
|
|
691 |
tcg_gen_qemu_ld16u(cpu_ir[ra], addr, ctx->mem_idx);
|
|
692 |
tcg_temp_free(addr);
|
|
693 |
}
|
675 |
694 |
break;
|
676 |
695 |
case 0x0D:
|
677 |
696 |
/* STW */
|
678 |
|
if (!(ctx->amask & AMASK_BWX))
|
679 |
|
goto invalid_opc;
|
680 |
|
gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);
|
|
697 |
{
|
|
698 |
TCGv addr;
|
|
699 |
if (!(ctx->amask & AMASK_BWX))
|
|
700 |
goto invalid_opc;
|
|
701 |
addr = tcg_temp_new(TCG_TYPE_I64);
|
|
702 |
if (rb != 31)
|
|
703 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
|
|
704 |
else
|
|
705 |
tcg_gen_movi_i64(addr, disp16);
|
|
706 |
if (ra != 31)
|
|
707 |
tcg_gen_qemu_st16(cpu_ir[ra], addr, ctx->mem_idx);
|
|
708 |
else {
|
|
709 |
TCGv zero = tcg_const_i64(0);
|
|
710 |
tcg_gen_qemu_st16(zero, addr, ctx->mem_idx);
|
|
711 |
tcg_temp_free(zero);
|
|
712 |
}
|
|
713 |
tcg_temp_free(addr);
|
|
714 |
}
|
681 |
715 |
break;
|
682 |
716 |
case 0x0E:
|
683 |
717 |
/* STB */
|
684 |
|
if (!(ctx->amask & AMASK_BWX))
|
685 |
|
goto invalid_opc;
|
686 |
|
gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);
|
|
718 |
{
|
|
719 |
TCGv addr;
|
|
720 |
if (!(ctx->amask & AMASK_BWX))
|
|
721 |
goto invalid_opc;
|
|
722 |
addr = tcg_temp_new(TCG_TYPE_I64);
|
|
723 |
if (rb != 31)
|
|
724 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
|
|
725 |
else
|
|
726 |
tcg_gen_movi_i64(addr, disp16);
|
|
727 |
if (ra != 31)
|
|
728 |
tcg_gen_qemu_st8(cpu_ir[ra], addr, ctx->mem_idx);
|
|
729 |
else {
|
|
730 |
TCGv zero = tcg_const_i64(0);
|
|
731 |
tcg_gen_qemu_st8(zero, addr, ctx->mem_idx);
|
|
732 |
tcg_temp_free(zero);
|
|
733 |
}
|
|
734 |
tcg_temp_free(addr);
|
|
735 |
}
|
687 |
736 |
break;
|
688 |
737 |
case 0x0F:
|
689 |
738 |
/* STQ_U */
|
690 |
|
gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);
|
|
739 |
{
|
|
740 |
TCGv addr = tcg_temp_new(TCG_TYPE_I64);
|
|
741 |
if (rb != 31) {
|
|
742 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
|
|
743 |
tcg_gen_andi_i64(addr, addr, ~0x7);
|
|
744 |
} else
|
|
745 |
tcg_gen_movi_i64(addr, disp16 & ~0x7);
|
|
746 |
if (ra != 31)
|
|
747 |
tcg_gen_qemu_st64(cpu_ir[ra], addr, ctx->mem_idx);
|
|
748 |
else {
|
|
749 |
TCGv zero = tcg_const_i64(0);
|
|
750 |
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
|
|
751 |
tcg_temp_free(zero);
|
|
752 |
}
|
|
753 |
tcg_temp_free(addr);
|
|
754 |
}
|
691 |
755 |
break;
|
692 |
756 |
case 0x10:
|
693 |
757 |
switch (fn7) {
|
... | ... | |
2125 |
2189 |
break;
|
2126 |
2190 |
case 0x28:
|
2127 |
2191 |
/* LDL */
|
2128 |
|
gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0);
|
|
2192 |
if (likely(ra != 31)) {
|
|
2193 |
TCGv addr = tcg_temp_new(TCG_TYPE_I64);
|
|
2194 |
if (rb != 31)
|
|
2195 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
|
|
2196 |
else
|
|
2197 |
tcg_gen_movi_i64(addr, disp16);
|
|
2198 |
tcg_gen_qemu_ld32s(cpu_ir[ra], addr, ctx->mem_idx);
|
|
2199 |
tcg_temp_free(addr);
|
|
2200 |
}
|
2129 |
2201 |
break;
|
2130 |
2202 |
case 0x29:
|
2131 |
2203 |
/* LDQ */
|
2132 |
|
gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0);
|
|
2204 |
if (likely(ra != 31)) {
|
|
2205 |
TCGv addr = tcg_temp_new(TCG_TYPE_I64);
|
|
2206 |
if (rb != 31)
|
|
2207 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
|
|
2208 |
else
|
|
2209 |
tcg_gen_movi_i64(addr, disp16);
|
|
2210 |
tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->mem_idx);
|
|
2211 |
tcg_temp_free(addr);
|
|
2212 |
}
|
2133 |
2213 |
break;
|
2134 |
2214 |
case 0x2A:
|
2135 |
2215 |
/* LDL_L */
|
... | ... | |
2141 |
2221 |
break;
|
2142 |
2222 |
case 0x2C:
|
2143 |
2223 |
/* STL */
|
2144 |
|
gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0);
|
|
2224 |
{
|
|
2225 |
TCGv addr = tcg_temp_new(TCG_TYPE_I64);
|
|
2226 |
if (rb != 31)
|
|
2227 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
|
|
2228 |
else
|
|
2229 |
tcg_gen_movi_i64(addr, disp16);
|
|
2230 |
if (ra != 31)
|
|
2231 |
tcg_gen_qemu_st32(cpu_ir[ra], addr, ctx->mem_idx);
|
|
2232 |
else {
|
|
2233 |
TCGv zero = tcg_const_i64(0);
|
|
2234 |
tcg_gen_qemu_st32(zero, addr, ctx->mem_idx);
|
|
2235 |
tcg_temp_free(zero);
|
|
2236 |
}
|
|
2237 |
tcg_temp_free(addr);
|
|
2238 |
}
|
2145 |
2239 |
break;
|
2146 |
2240 |
case 0x2D:
|
2147 |
2241 |
/* STQ */
|
2148 |
|
gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0);
|
|
2242 |
{
|
|
2243 |
TCGv addr = tcg_temp_new(TCG_TYPE_I64);
|
|
2244 |
if (rb != 31)
|
|
2245 |
tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
|
|
2246 |
else
|
|
2247 |
tcg_gen_movi_i64(addr, disp16);
|
|
2248 |
if (ra != 31)
|
|
2249 |
tcg_gen_qemu_st64(cpu_ir[ra], addr, ctx->mem_idx);
|
|
2250 |
else {
|
|
2251 |
TCGv zero = tcg_const_i64(0);
|
|
2252 |
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
|
|
2253 |
tcg_temp_free(zero);
|
|
2254 |
}
|
|
2255 |
tcg_temp_free(addr);
|
|
2256 |
}
|
2149 |
2257 |
break;
|
2150 |
2258 |
case 0x2E:
|
2151 |
2259 |
/* STL_C */
|