root / target-sparc / int32_helper.c @ b072a3c8
History | View | Annotate | Download (5.1 kB)
1 | ab3b491f | Blue Swirl | /*
|
---|---|---|---|
2 | ab3b491f | Blue Swirl | * Sparc32 interrupt helpers
|
3 | ab3b491f | Blue Swirl | *
|
4 | ab3b491f | Blue Swirl | * Copyright (c) 2003-2005 Fabrice Bellard
|
5 | ab3b491f | Blue Swirl | *
|
6 | ab3b491f | Blue Swirl | * This library is free software; you can redistribute it and/or
|
7 | ab3b491f | Blue Swirl | * modify it under the terms of the GNU Lesser General Public
|
8 | ab3b491f | Blue Swirl | * License as published by the Free Software Foundation; either
|
9 | ab3b491f | Blue Swirl | * version 2 of the License, or (at your option) any later version.
|
10 | ab3b491f | Blue Swirl | *
|
11 | ab3b491f | Blue Swirl | * This library is distributed in the hope that it will be useful,
|
12 | ab3b491f | Blue Swirl | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | ab3b491f | Blue Swirl | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | ab3b491f | Blue Swirl | * Lesser General Public License for more details.
|
15 | ab3b491f | Blue Swirl | *
|
16 | ab3b491f | Blue Swirl | * You should have received a copy of the GNU Lesser General Public
|
17 | ab3b491f | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
18 | ab3b491f | Blue Swirl | */
|
19 | ab3b491f | Blue Swirl | |
20 | ab3b491f | Blue Swirl | #include "cpu.h" |
21 | 11e66bca | Blue Swirl | #include "trace.h" |
22 | 96d922a6 | Fabien Chouteau | #include "sysemu.h" |
23 | ab3b491f | Blue Swirl | |
24 | ab3b491f | Blue Swirl | //#define DEBUG_PCALL
|
25 | ab3b491f | Blue Swirl | |
26 | ab3b491f | Blue Swirl | #ifdef DEBUG_PCALL
|
27 | ab3b491f | Blue Swirl | static const char * const excp_names[0x80] = { |
28 | ab3b491f | Blue Swirl | [TT_TFAULT] = "Instruction Access Fault",
|
29 | ab3b491f | Blue Swirl | [TT_ILL_INSN] = "Illegal Instruction",
|
30 | ab3b491f | Blue Swirl | [TT_PRIV_INSN] = "Privileged Instruction",
|
31 | ab3b491f | Blue Swirl | [TT_NFPU_INSN] = "FPU Disabled",
|
32 | ab3b491f | Blue Swirl | [TT_WIN_OVF] = "Window Overflow",
|
33 | ab3b491f | Blue Swirl | [TT_WIN_UNF] = "Window Underflow",
|
34 | ab3b491f | Blue Swirl | [TT_UNALIGNED] = "Unaligned Memory Access",
|
35 | ab3b491f | Blue Swirl | [TT_FP_EXCP] = "FPU Exception",
|
36 | ab3b491f | Blue Swirl | [TT_DFAULT] = "Data Access Fault",
|
37 | ab3b491f | Blue Swirl | [TT_TOVF] = "Tag Overflow",
|
38 | ab3b491f | Blue Swirl | [TT_EXTINT | 0x1] = "External Interrupt 1", |
39 | ab3b491f | Blue Swirl | [TT_EXTINT | 0x2] = "External Interrupt 2", |
40 | ab3b491f | Blue Swirl | [TT_EXTINT | 0x3] = "External Interrupt 3", |
41 | ab3b491f | Blue Swirl | [TT_EXTINT | 0x4] = "External Interrupt 4", |
42 | ab3b491f | Blue Swirl | [TT_EXTINT | 0x5] = "External Interrupt 5", |
43 | ab3b491f | Blue Swirl | [TT_EXTINT | 0x6] = "External Interrupt 6", |
44 | ab3b491f | Blue Swirl | [TT_EXTINT | 0x7] = "External Interrupt 7", |
45 | ab3b491f | Blue Swirl | [TT_EXTINT | 0x8] = "External Interrupt 8", |
46 | ab3b491f | Blue Swirl | [TT_EXTINT | 0x9] = "External Interrupt 9", |
47 | ab3b491f | Blue Swirl | [TT_EXTINT | 0xa] = "External Interrupt 10", |
48 | ab3b491f | Blue Swirl | [TT_EXTINT | 0xb] = "External Interrupt 11", |
49 | ab3b491f | Blue Swirl | [TT_EXTINT | 0xc] = "External Interrupt 12", |
50 | ab3b491f | Blue Swirl | [TT_EXTINT | 0xd] = "External Interrupt 13", |
51 | ab3b491f | Blue Swirl | [TT_EXTINT | 0xe] = "External Interrupt 14", |
52 | ab3b491f | Blue Swirl | [TT_EXTINT | 0xf] = "External Interrupt 15", |
53 | ab3b491f | Blue Swirl | [TT_TOVF] = "Tag Overflow",
|
54 | ab3b491f | Blue Swirl | [TT_CODE_ACCESS] = "Instruction Access Error",
|
55 | ab3b491f | Blue Swirl | [TT_DATA_ACCESS] = "Data Access Error",
|
56 | ab3b491f | Blue Swirl | [TT_DIV_ZERO] = "Division By Zero",
|
57 | ab3b491f | Blue Swirl | [TT_NCP_INSN] = "Coprocessor Disabled",
|
58 | ab3b491f | Blue Swirl | }; |
59 | ab3b491f | Blue Swirl | #endif
|
60 | ab3b491f | Blue Swirl | |
61 | ab3b491f | Blue Swirl | void do_interrupt(CPUState *env)
|
62 | ab3b491f | Blue Swirl | { |
63 | ab3b491f | Blue Swirl | int cwp, intno = env->exception_index;
|
64 | ab3b491f | Blue Swirl | |
65 | ab3b491f | Blue Swirl | #ifdef DEBUG_PCALL
|
66 | ab3b491f | Blue Swirl | if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
67 | ab3b491f | Blue Swirl | static int count; |
68 | ab3b491f | Blue Swirl | const char *name; |
69 | ab3b491f | Blue Swirl | |
70 | ab3b491f | Blue Swirl | if (intno < 0 || intno >= 0x100) { |
71 | ab3b491f | Blue Swirl | name = "Unknown";
|
72 | ab3b491f | Blue Swirl | } else if (intno >= 0x80) { |
73 | ab3b491f | Blue Swirl | name = "Trap Instruction";
|
74 | ab3b491f | Blue Swirl | } else {
|
75 | ab3b491f | Blue Swirl | name = excp_names[intno]; |
76 | ab3b491f | Blue Swirl | if (!name) {
|
77 | ab3b491f | Blue Swirl | name = "Unknown";
|
78 | ab3b491f | Blue Swirl | } |
79 | ab3b491f | Blue Swirl | } |
80 | ab3b491f | Blue Swirl | |
81 | ab3b491f | Blue Swirl | qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
|
82 | ab3b491f | Blue Swirl | count, name, intno, |
83 | ab3b491f | Blue Swirl | env->pc, |
84 | ab3b491f | Blue Swirl | env->npc, env->regwptr[6]);
|
85 | ab3b491f | Blue Swirl | log_cpu_state(env, 0);
|
86 | ab3b491f | Blue Swirl | #if 0
|
87 | ab3b491f | Blue Swirl | {
|
88 | ab3b491f | Blue Swirl | int i;
|
89 | ab3b491f | Blue Swirl | uint8_t *ptr;
|
90 | ab3b491f | Blue Swirl | |
91 | ab3b491f | Blue Swirl | qemu_log(" code=");
|
92 | ab3b491f | Blue Swirl | ptr = (uint8_t *)env->pc;
|
93 | ab3b491f | Blue Swirl | for (i = 0; i < 16; i++) {
|
94 | ab3b491f | Blue Swirl | qemu_log(" %02x", ldub(ptr + i));
|
95 | ab3b491f | Blue Swirl | }
|
96 | ab3b491f | Blue Swirl | qemu_log("\n");
|
97 | ab3b491f | Blue Swirl | }
|
98 | ab3b491f | Blue Swirl | #endif
|
99 | ab3b491f | Blue Swirl | count++; |
100 | ab3b491f | Blue Swirl | } |
101 | ab3b491f | Blue Swirl | #endif
|
102 | ab3b491f | Blue Swirl | #if !defined(CONFIG_USER_ONLY)
|
103 | ab3b491f | Blue Swirl | if (env->psret == 0) { |
104 | 96d922a6 | Fabien Chouteau | if (env->exception_index == 0x80 && |
105 | 96d922a6 | Fabien Chouteau | env->def->features & CPU_FEATURE_TA0_SHUTDOWN) { |
106 | 96d922a6 | Fabien Chouteau | qemu_system_shutdown_request(); |
107 | 96d922a6 | Fabien Chouteau | } else {
|
108 | 96d922a6 | Fabien Chouteau | cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
|
109 | 96d922a6 | Fabien Chouteau | env->exception_index); |
110 | 96d922a6 | Fabien Chouteau | } |
111 | ab3b491f | Blue Swirl | return;
|
112 | ab3b491f | Blue Swirl | } |
113 | ab3b491f | Blue Swirl | #endif
|
114 | ab3b491f | Blue Swirl | env->psret = 0;
|
115 | ab3b491f | Blue Swirl | cwp = cpu_cwp_dec(env, env->cwp - 1);
|
116 | ab3b491f | Blue Swirl | cpu_set_cwp(env, cwp); |
117 | ab3b491f | Blue Swirl | env->regwptr[9] = env->pc;
|
118 | ab3b491f | Blue Swirl | env->regwptr[10] = env->npc;
|
119 | ab3b491f | Blue Swirl | env->psrps = env->psrs; |
120 | ab3b491f | Blue Swirl | env->psrs = 1;
|
121 | ab3b491f | Blue Swirl | env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
122 | ab3b491f | Blue Swirl | env->pc = env->tbr; |
123 | ab3b491f | Blue Swirl | env->npc = env->pc + 4;
|
124 | ab3b491f | Blue Swirl | env->exception_index = -1;
|
125 | ab3b491f | Blue Swirl | |
126 | ab3b491f | Blue Swirl | #if !defined(CONFIG_USER_ONLY)
|
127 | ab3b491f | Blue Swirl | /* IRQ acknowledgment */
|
128 | ab3b491f | Blue Swirl | if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) { |
129 | 79227036 | Blue Swirl | env->qemu_irq_ack(env, env->irq_manager, intno); |
130 | ab3b491f | Blue Swirl | } |
131 | ab3b491f | Blue Swirl | #endif
|
132 | ab3b491f | Blue Swirl | } |
133 | 79227036 | Blue Swirl | |
134 | 79227036 | Blue Swirl | #if !defined(CONFIG_USER_ONLY)
|
135 | 79227036 | Blue Swirl | static void leon3_cache_control_int(CPUState *env) |
136 | 79227036 | Blue Swirl | { |
137 | 79227036 | Blue Swirl | uint32_t state = 0;
|
138 | 79227036 | Blue Swirl | |
139 | 79227036 | Blue Swirl | if (env->cache_control & CACHE_CTRL_IF) {
|
140 | 79227036 | Blue Swirl | /* Instruction cache state */
|
141 | 79227036 | Blue Swirl | state = env->cache_control & CACHE_STATE_MASK; |
142 | 79227036 | Blue Swirl | if (state == CACHE_ENABLED) {
|
143 | 79227036 | Blue Swirl | state = CACHE_FROZEN; |
144 | 11e66bca | Blue Swirl | trace_int_helper_icache_freeze(); |
145 | 79227036 | Blue Swirl | } |
146 | 79227036 | Blue Swirl | |
147 | 79227036 | Blue Swirl | env->cache_control &= ~CACHE_STATE_MASK; |
148 | 79227036 | Blue Swirl | env->cache_control |= state; |
149 | 79227036 | Blue Swirl | } |
150 | 79227036 | Blue Swirl | |
151 | 79227036 | Blue Swirl | if (env->cache_control & CACHE_CTRL_DF) {
|
152 | 79227036 | Blue Swirl | /* Data cache state */
|
153 | 79227036 | Blue Swirl | state = (env->cache_control >> 2) & CACHE_STATE_MASK;
|
154 | 79227036 | Blue Swirl | if (state == CACHE_ENABLED) {
|
155 | 79227036 | Blue Swirl | state = CACHE_FROZEN; |
156 | 11e66bca | Blue Swirl | trace_int_helper_dcache_freeze(); |
157 | 79227036 | Blue Swirl | } |
158 | 79227036 | Blue Swirl | |
159 | 79227036 | Blue Swirl | env->cache_control &= ~(CACHE_STATE_MASK << 2);
|
160 | 79227036 | Blue Swirl | env->cache_control |= (state << 2);
|
161 | 79227036 | Blue Swirl | } |
162 | 79227036 | Blue Swirl | } |
163 | 79227036 | Blue Swirl | |
164 | 79227036 | Blue Swirl | void leon3_irq_manager(CPUState *env, void *irq_manager, int intno) |
165 | 79227036 | Blue Swirl | { |
166 | 79227036 | Blue Swirl | leon3_irq_ack(irq_manager, intno); |
167 | 79227036 | Blue Swirl | leon3_cache_control_int(env); |
168 | 79227036 | Blue Swirl | } |
169 | 79227036 | Blue Swirl | #endif |