Revision b0ff21b4
| ID | b0ff21b4f96fa8223ec252ec3e99a8a9af86cf0c |
target-arm: A64: add support for add, addi, sub, subi
Implement the non-carry forms of addition and subtraction
(immediate, extended register and shifted register).
This includes the code to calculate NZCV if the instruction
calls for setting the flags.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Files
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