root / hw / exynos4210.c @ b13ce26d
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1 | 0caa7113 | Evgeny Voevodin | /*
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2 | 0caa7113 | Evgeny Voevodin | * Samsung exynos4210 SoC emulation
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3 | 0caa7113 | Evgeny Voevodin | *
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4 | 0caa7113 | Evgeny Voevodin | * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
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5 | 0caa7113 | Evgeny Voevodin | * Maksim Kozlov <m.kozlov@samsung.com>
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6 | 0caa7113 | Evgeny Voevodin | * Evgeny Voevodin <e.voevodin@samsung.com>
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7 | 0caa7113 | Evgeny Voevodin | * Igor Mitsyanko <i.mitsyanko@samsung.com>
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8 | 0caa7113 | Evgeny Voevodin | *
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9 | 0caa7113 | Evgeny Voevodin | * This program is free software; you can redistribute it and/or modify it
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10 | 0caa7113 | Evgeny Voevodin | * under the terms of the GNU General Public License as published by the
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11 | 0caa7113 | Evgeny Voevodin | * Free Software Foundation; either version 2 of the License, or
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12 | 0caa7113 | Evgeny Voevodin | * (at your option) any later version.
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13 | 0caa7113 | Evgeny Voevodin | *
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14 | 0caa7113 | Evgeny Voevodin | * This program is distributed in the hope that it will be useful, but WITHOUT
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15 | 0caa7113 | Evgeny Voevodin | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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16 | 0caa7113 | Evgeny Voevodin | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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17 | 0caa7113 | Evgeny Voevodin | * for more details.
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18 | 0caa7113 | Evgeny Voevodin | *
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19 | 0caa7113 | Evgeny Voevodin | * You should have received a copy of the GNU General Public License along
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20 | 0caa7113 | Evgeny Voevodin | * with this program; if not, see <http://www.gnu.org/licenses/>.
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21 | 0caa7113 | Evgeny Voevodin | *
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22 | 0caa7113 | Evgeny Voevodin | */
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23 | 0caa7113 | Evgeny Voevodin | |
24 | 0caa7113 | Evgeny Voevodin | #include "boards.h" |
25 | 0caa7113 | Evgeny Voevodin | #include "sysemu.h" |
26 | 0caa7113 | Evgeny Voevodin | #include "sysbus.h" |
27 | 0caa7113 | Evgeny Voevodin | #include "arm-misc.h" |
28 | 3f088e36 | Evgeny Voevodin | #include "loader.h" |
29 | 0caa7113 | Evgeny Voevodin | #include "exynos4210.h" |
30 | 0caa7113 | Evgeny Voevodin | |
31 | 0caa7113 | Evgeny Voevodin | #define EXYNOS4210_CHIPID_ADDR 0x10000000 |
32 | 0caa7113 | Evgeny Voevodin | |
33 | 62db8bf3 | Evgeny Voevodin | /* PWM */
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34 | 62db8bf3 | Evgeny Voevodin | #define EXYNOS4210_PWM_BASE_ADDR 0x139D0000 |
35 | 62db8bf3 | Evgeny Voevodin | |
36 | 7bdf43a7 | Oleg Ogurtsov | /* RTC */
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37 | 7bdf43a7 | Oleg Ogurtsov | #define EXYNOS4210_RTC_BASE_ADDR 0x10070000 |
38 | 7bdf43a7 | Oleg Ogurtsov | |
39 | 12c775db | Evgeny Voevodin | /* MCT */
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40 | 12c775db | Evgeny Voevodin | #define EXYNOS4210_MCT_BASE_ADDR 0x10050000 |
41 | 12c775db | Evgeny Voevodin | |
42 | ffbbe7d0 | Mitsyanko Igor | /* I2C */
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43 | ffbbe7d0 | Mitsyanko Igor | #define EXYNOS4210_I2C_SHIFT 0x00010000 |
44 | ffbbe7d0 | Mitsyanko Igor | #define EXYNOS4210_I2C_BASE_ADDR 0x13860000 |
45 | ffbbe7d0 | Mitsyanko Igor | /* Interrupt Group of External Interrupt Combiner for I2C */
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46 | ffbbe7d0 | Mitsyanko Igor | #define EXYNOS4210_I2C_INTG 27 |
47 | ffbbe7d0 | Mitsyanko Igor | #define EXYNOS4210_HDMI_INTG 16 |
48 | ffbbe7d0 | Mitsyanko Igor | |
49 | e5a4914e | Maksim Kozlov | /* UART's definitions */
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50 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART0_BASE_ADDR 0x13800000 |
51 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART1_BASE_ADDR 0x13810000 |
52 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART2_BASE_ADDR 0x13820000 |
53 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART3_BASE_ADDR 0x13830000 |
54 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART0_FIFO_SIZE 256 |
55 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART1_FIFO_SIZE 64 |
56 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART2_FIFO_SIZE 16 |
57 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART3_FIFO_SIZE 16 |
58 | e5a4914e | Maksim Kozlov | /* Interrupt Group of External Interrupt Combiner for UART */
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59 | e5a4914e | Maksim Kozlov | #define EXYNOS4210_UART_INT_GRP 26 |
60 | e5a4914e | Maksim Kozlov | |
61 | 0caa7113 | Evgeny Voevodin | /* External GIC */
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62 | 0caa7113 | Evgeny Voevodin | #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 |
63 | 0caa7113 | Evgeny Voevodin | #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 |
64 | 0caa7113 | Evgeny Voevodin | |
65 | 0caa7113 | Evgeny Voevodin | /* Combiner */
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66 | 0caa7113 | Evgeny Voevodin | #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 |
67 | 0caa7113 | Evgeny Voevodin | #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 |
68 | 0caa7113 | Evgeny Voevodin | |
69 | df91b48f | Maksim Kozlov | /* PMU SFR base address */
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70 | df91b48f | Maksim Kozlov | #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 |
71 | df91b48f | Maksim Kozlov | |
72 | 30628cb1 | Mitsyanko Igor | /* Display controllers (FIMD) */
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73 | 30628cb1 | Mitsyanko Igor | #define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 |
74 | 30628cb1 | Mitsyanko Igor | |
75 | 0caa7113 | Evgeny Voevodin | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, |
76 | 0caa7113 | Evgeny Voevodin | 0x09, 0x00, 0x00, 0x00 }; |
77 | 0caa7113 | Evgeny Voevodin | |
78 | 9543b0cd | Andreas Färber | void exynos4210_write_secondary(ARMCPU *cpu,
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79 | 3f088e36 | Evgeny Voevodin | const struct arm_boot_info *info) |
80 | 3f088e36 | Evgeny Voevodin | { |
81 | 3f088e36 | Evgeny Voevodin | int n;
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82 | 3f088e36 | Evgeny Voevodin | uint32_t smpboot[] = { |
83 | 3f088e36 | Evgeny Voevodin | 0xe59f3024, /* ldr r3, External gic_cpu_if */ |
84 | 3f088e36 | Evgeny Voevodin | 0xe59f2024, /* ldr r2, Internal gic_cpu_if */ |
85 | 3f088e36 | Evgeny Voevodin | 0xe59f0024, /* ldr r0, startaddr */ |
86 | 3f088e36 | Evgeny Voevodin | 0xe3a01001, /* mov r1, #1 */ |
87 | 3f088e36 | Evgeny Voevodin | 0xe5821000, /* str r1, [r2] */ |
88 | 3f088e36 | Evgeny Voevodin | 0xe5831000, /* str r1, [r3] */ |
89 | 3f088e36 | Evgeny Voevodin | 0xe320f003, /* wfi */ |
90 | 3f088e36 | Evgeny Voevodin | 0xe5901000, /* ldr r1, [r0] */ |
91 | 3f088e36 | Evgeny Voevodin | 0xe1110001, /* tst r1, r1 */ |
92 | 3f088e36 | Evgeny Voevodin | 0x0afffffb, /* beq <wfi> */ |
93 | 3f088e36 | Evgeny Voevodin | 0xe12fff11, /* bx r1 */ |
94 | 3f088e36 | Evgeny Voevodin | EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, |
95 | 3f088e36 | Evgeny Voevodin | 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ |
96 | 3f088e36 | Evgeny Voevodin | 0 /* bootreg: Boot register address is held here */ |
97 | 3f088e36 | Evgeny Voevodin | }; |
98 | 3f088e36 | Evgeny Voevodin | smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
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99 | 3f088e36 | Evgeny Voevodin | smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
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100 | 3f088e36 | Evgeny Voevodin | for (n = 0; n < ARRAY_SIZE(smpboot); n++) { |
101 | 3f088e36 | Evgeny Voevodin | smpboot[n] = tswap32(smpboot[n]); |
102 | 3f088e36 | Evgeny Voevodin | } |
103 | 3f088e36 | Evgeny Voevodin | rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), |
104 | 3f088e36 | Evgeny Voevodin | info->smp_loader_start); |
105 | 3f088e36 | Evgeny Voevodin | } |
106 | 3f088e36 | Evgeny Voevodin | |
107 | 0caa7113 | Evgeny Voevodin | Exynos4210State *exynos4210_init(MemoryRegion *system_mem, |
108 | 0caa7113 | Evgeny Voevodin | unsigned long ram_size) |
109 | 0caa7113 | Evgeny Voevodin | { |
110 | 61558e7a | Evgeny Voevodin | qemu_irq cpu_irq[EXYNOS4210_NCPUS]; |
111 | 61558e7a | Evgeny Voevodin | int i, n;
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112 | 0caa7113 | Evgeny Voevodin | Exynos4210State *s = g_new(Exynos4210State, 1);
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113 | 0caa7113 | Evgeny Voevodin | qemu_irq *irqp; |
114 | 61558e7a | Evgeny Voevodin | qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; |
115 | 0caa7113 | Evgeny Voevodin | unsigned long mem_size; |
116 | 0caa7113 | Evgeny Voevodin | DeviceState *dev; |
117 | 0caa7113 | Evgeny Voevodin | SysBusDevice *busdev; |
118 | 0caa7113 | Evgeny Voevodin | |
119 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
120 | ef6cbcc5 | Andreas Färber | s->cpu[n] = cpu_arm_init("cortex-a9");
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121 | ef6cbcc5 | Andreas Färber | if (!s->cpu[n]) {
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122 | 0caa7113 | Evgeny Voevodin | fprintf(stderr, "Unable to find CPU %d definition\n", n);
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123 | 0caa7113 | Evgeny Voevodin | exit(1);
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124 | 0caa7113 | Evgeny Voevodin | } |
125 | 4bd74661 | Andreas Färber | |
126 | 0caa7113 | Evgeny Voevodin | /* Create PIC controller for each processor instance */
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127 | 4bd74661 | Andreas Färber | irqp = arm_pic_init_cpu(s->cpu[n]); |
128 | 0caa7113 | Evgeny Voevodin | |
129 | 0caa7113 | Evgeny Voevodin | /*
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130 | 0caa7113 | Evgeny Voevodin | * Get GICs gpio_in cpu_irq to connect a combiner to them later.
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131 | 0caa7113 | Evgeny Voevodin | * Use only IRQ for a while.
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132 | 0caa7113 | Evgeny Voevodin | */
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133 | 0caa7113 | Evgeny Voevodin | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
134 | 0caa7113 | Evgeny Voevodin | } |
135 | 0caa7113 | Evgeny Voevodin | |
136 | 0caa7113 | Evgeny Voevodin | /*** IRQs ***/
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137 | 0caa7113 | Evgeny Voevodin | |
138 | 0caa7113 | Evgeny Voevodin | s->irq_table = exynos4210_init_irq(&s->irqs); |
139 | 0caa7113 | Evgeny Voevodin | |
140 | 0caa7113 | Evgeny Voevodin | /* IRQ Gate */
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141 | 61558e7a | Evgeny Voevodin | for (i = 0; i < EXYNOS4210_NCPUS; i++) { |
142 | 61558e7a | Evgeny Voevodin | dev = qdev_create(NULL, "exynos4210.irq_gate"); |
143 | 61558e7a | Evgeny Voevodin | qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
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144 | 61558e7a | Evgeny Voevodin | qdev_init_nofail(dev); |
145 | 61558e7a | Evgeny Voevodin | /* Get IRQ Gate input in gate_irq */
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146 | 61558e7a | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { |
147 | 61558e7a | Evgeny Voevodin | gate_irq[i][n] = qdev_get_gpio_in(dev, n); |
148 | 61558e7a | Evgeny Voevodin | } |
149 | 61558e7a | Evgeny Voevodin | busdev = sysbus_from_qdev(dev); |
150 | 61558e7a | Evgeny Voevodin | |
151 | 61558e7a | Evgeny Voevodin | /* Connect IRQ Gate output to cpu_irq */
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152 | 61558e7a | Evgeny Voevodin | sysbus_connect_irq(busdev, 0, cpu_irq[i]);
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153 | 0caa7113 | Evgeny Voevodin | } |
154 | 0caa7113 | Evgeny Voevodin | |
155 | 0caa7113 | Evgeny Voevodin | /* Private memory region and Internal GIC */
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156 | 0caa7113 | Evgeny Voevodin | dev = qdev_create(NULL, "a9mpcore_priv"); |
157 | 0caa7113 | Evgeny Voevodin | qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
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158 | 0caa7113 | Evgeny Voevodin | qdev_init_nofail(dev); |
159 | 0caa7113 | Evgeny Voevodin | busdev = sysbus_from_qdev(dev); |
160 | 0caa7113 | Evgeny Voevodin | sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
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161 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
162 | 61558e7a | Evgeny Voevodin | sysbus_connect_irq(busdev, n, gate_irq[n][0]);
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163 | 0caa7113 | Evgeny Voevodin | } |
164 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { |
165 | 0caa7113 | Evgeny Voevodin | s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); |
166 | 0caa7113 | Evgeny Voevodin | } |
167 | 0caa7113 | Evgeny Voevodin | |
168 | 0caa7113 | Evgeny Voevodin | /* Cache controller */
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169 | 0caa7113 | Evgeny Voevodin | sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); |
170 | 0caa7113 | Evgeny Voevodin | |
171 | 0caa7113 | Evgeny Voevodin | /* External GIC */
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172 | 0caa7113 | Evgeny Voevodin | dev = qdev_create(NULL, "exynos4210.gic"); |
173 | 0caa7113 | Evgeny Voevodin | qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
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174 | 0caa7113 | Evgeny Voevodin | qdev_init_nofail(dev); |
175 | 0caa7113 | Evgeny Voevodin | busdev = sysbus_from_qdev(dev); |
176 | 0caa7113 | Evgeny Voevodin | /* Map CPU interface */
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177 | 0caa7113 | Evgeny Voevodin | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
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178 | 0caa7113 | Evgeny Voevodin | /* Map Distributer interface */
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179 | 0caa7113 | Evgeny Voevodin | sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
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180 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_NCPUS; n++) { |
181 | 61558e7a | Evgeny Voevodin | sysbus_connect_irq(busdev, n, gate_irq[n][1]);
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182 | 0caa7113 | Evgeny Voevodin | } |
183 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { |
184 | 0caa7113 | Evgeny Voevodin | s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n); |
185 | 0caa7113 | Evgeny Voevodin | } |
186 | 0caa7113 | Evgeny Voevodin | |
187 | 0caa7113 | Evgeny Voevodin | /* Internal Interrupt Combiner */
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188 | 0caa7113 | Evgeny Voevodin | dev = qdev_create(NULL, "exynos4210.combiner"); |
189 | 0caa7113 | Evgeny Voevodin | qdev_init_nofail(dev); |
190 | 0caa7113 | Evgeny Voevodin | busdev = sysbus_from_qdev(dev); |
191 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { |
192 | 0caa7113 | Evgeny Voevodin | sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); |
193 | 0caa7113 | Evgeny Voevodin | } |
194 | 0caa7113 | Evgeny Voevodin | exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
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195 | 0caa7113 | Evgeny Voevodin | sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
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196 | 0caa7113 | Evgeny Voevodin | |
197 | 0caa7113 | Evgeny Voevodin | /* External Interrupt Combiner */
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198 | 0caa7113 | Evgeny Voevodin | dev = qdev_create(NULL, "exynos4210.combiner"); |
199 | 0caa7113 | Evgeny Voevodin | qdev_prop_set_uint32(dev, "external", 1); |
200 | 0caa7113 | Evgeny Voevodin | qdev_init_nofail(dev); |
201 | 0caa7113 | Evgeny Voevodin | busdev = sysbus_from_qdev(dev); |
202 | 0caa7113 | Evgeny Voevodin | for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { |
203 | 0caa7113 | Evgeny Voevodin | sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); |
204 | 0caa7113 | Evgeny Voevodin | } |
205 | 0caa7113 | Evgeny Voevodin | exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
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206 | 0caa7113 | Evgeny Voevodin | sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
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207 | 0caa7113 | Evgeny Voevodin | |
208 | 0caa7113 | Evgeny Voevodin | /* Initialize board IRQs. */
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209 | 0caa7113 | Evgeny Voevodin | exynos4210_init_board_irqs(&s->irqs); |
210 | 0caa7113 | Evgeny Voevodin | |
211 | 0caa7113 | Evgeny Voevodin | /*** Memory ***/
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212 | 0caa7113 | Evgeny Voevodin | |
213 | 0caa7113 | Evgeny Voevodin | /* Chip-ID and OMR */
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214 | 0caa7113 | Evgeny Voevodin | memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
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215 | 0caa7113 | Evgeny Voevodin | sizeof(chipid_and_omr), chipid_and_omr);
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216 | 0caa7113 | Evgeny Voevodin | memory_region_set_readonly(&s->chipid_mem, true);
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217 | 0caa7113 | Evgeny Voevodin | memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR, |
218 | 0caa7113 | Evgeny Voevodin | &s->chipid_mem); |
219 | 0caa7113 | Evgeny Voevodin | |
220 | 0caa7113 | Evgeny Voevodin | /* Internal ROM */
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221 | 0caa7113 | Evgeny Voevodin | memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
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222 | 0caa7113 | Evgeny Voevodin | EXYNOS4210_IROM_SIZE); |
223 | 0caa7113 | Evgeny Voevodin | memory_region_set_readonly(&s->irom_mem, true);
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224 | 0caa7113 | Evgeny Voevodin | memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, |
225 | 0caa7113 | Evgeny Voevodin | &s->irom_mem); |
226 | 0caa7113 | Evgeny Voevodin | /* mirror of iROM */
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227 | 0caa7113 | Evgeny Voevodin | memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
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228 | 0caa7113 | Evgeny Voevodin | &s->irom_mem, |
229 | 7892df06 | Evgeny Voevodin | 0,
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230 | 0caa7113 | Evgeny Voevodin | EXYNOS4210_IROM_SIZE); |
231 | 0caa7113 | Evgeny Voevodin | memory_region_set_readonly(&s->irom_alias_mem, true);
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232 | 0caa7113 | Evgeny Voevodin | memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR, |
233 | 0caa7113 | Evgeny Voevodin | &s->irom_alias_mem); |
234 | 0caa7113 | Evgeny Voevodin | |
235 | 0caa7113 | Evgeny Voevodin | /* Internal RAM */
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236 | 0caa7113 | Evgeny Voevodin | memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
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237 | 0caa7113 | Evgeny Voevodin | EXYNOS4210_IRAM_SIZE); |
238 | 0caa7113 | Evgeny Voevodin | vmstate_register_ram_global(&s->iram_mem); |
239 | 0caa7113 | Evgeny Voevodin | memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, |
240 | 0caa7113 | Evgeny Voevodin | &s->iram_mem); |
241 | 0caa7113 | Evgeny Voevodin | |
242 | 0caa7113 | Evgeny Voevodin | /* DRAM */
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243 | 0caa7113 | Evgeny Voevodin | mem_size = ram_size; |
244 | 0caa7113 | Evgeny Voevodin | if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
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245 | 0caa7113 | Evgeny Voevodin | memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
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246 | 0caa7113 | Evgeny Voevodin | mem_size - EXYNOS4210_DRAM_MAX_SIZE); |
247 | 0caa7113 | Evgeny Voevodin | vmstate_register_ram_global(&s->dram1_mem); |
248 | 0caa7113 | Evgeny Voevodin | memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, |
249 | 0caa7113 | Evgeny Voevodin | &s->dram1_mem); |
250 | 0caa7113 | Evgeny Voevodin | mem_size = EXYNOS4210_DRAM_MAX_SIZE; |
251 | 0caa7113 | Evgeny Voevodin | } |
252 | 0caa7113 | Evgeny Voevodin | memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
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253 | 0caa7113 | Evgeny Voevodin | vmstate_register_ram_global(&s->dram0_mem); |
254 | 0caa7113 | Evgeny Voevodin | memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, |
255 | 0caa7113 | Evgeny Voevodin | &s->dram0_mem); |
256 | 0caa7113 | Evgeny Voevodin | |
257 | df91b48f | Maksim Kozlov | /* PMU.
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258 | df91b48f | Maksim Kozlov | * The only reason of existence at the moment is that secondary CPU boot
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259 | df91b48f | Maksim Kozlov | * loader uses PMU INFORM5 register as a holding pen.
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260 | df91b48f | Maksim Kozlov | */
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261 | df91b48f | Maksim Kozlov | sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); |
262 | df91b48f | Maksim Kozlov | |
263 | 62db8bf3 | Evgeny Voevodin | /* PWM */
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264 | 62db8bf3 | Evgeny Voevodin | sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
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265 | 62db8bf3 | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(22, 0)], |
266 | 62db8bf3 | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(22, 1)], |
267 | 62db8bf3 | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(22, 2)], |
268 | 62db8bf3 | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(22, 3)], |
269 | 62db8bf3 | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(22, 4)], |
270 | 62db8bf3 | Evgeny Voevodin | NULL);
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271 | 7bdf43a7 | Oleg Ogurtsov | /* RTC */
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272 | 7bdf43a7 | Oleg Ogurtsov | sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
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273 | 7bdf43a7 | Oleg Ogurtsov | s->irq_table[exynos4210_get_irq(23, 0)], |
274 | 7bdf43a7 | Oleg Ogurtsov | s->irq_table[exynos4210_get_irq(23, 1)], |
275 | 7bdf43a7 | Oleg Ogurtsov | NULL);
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276 | 62db8bf3 | Evgeny Voevodin | |
277 | 12c775db | Evgeny Voevodin | /* Multi Core Timer */
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278 | 12c775db | Evgeny Voevodin | dev = qdev_create(NULL, "exynos4210.mct"); |
279 | 12c775db | Evgeny Voevodin | qdev_init_nofail(dev); |
280 | 12c775db | Evgeny Voevodin | busdev = sysbus_from_qdev(dev); |
281 | 12c775db | Evgeny Voevodin | for (n = 0; n < 4; n++) { |
282 | 12c775db | Evgeny Voevodin | /* Connect global timer interrupts to Combiner gpio_in */
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283 | 12c775db | Evgeny Voevodin | sysbus_connect_irq(busdev, n, |
284 | 12c775db | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(1, 4 + n)]); |
285 | 12c775db | Evgeny Voevodin | } |
286 | 12c775db | Evgeny Voevodin | /* Connect local timer interrupts to Combiner gpio_in */
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287 | 12c775db | Evgeny Voevodin | sysbus_connect_irq(busdev, 4,
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288 | 12c775db | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(51, 0)]); |
289 | 12c775db | Evgeny Voevodin | sysbus_connect_irq(busdev, 5,
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290 | 12c775db | Evgeny Voevodin | s->irq_table[exynos4210_get_irq(35, 3)]); |
291 | 12c775db | Evgeny Voevodin | sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
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292 | 12c775db | Evgeny Voevodin | |
293 | ffbbe7d0 | Mitsyanko Igor | /*** I2C ***/
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294 | ffbbe7d0 | Mitsyanko Igor | for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) { |
295 | ffbbe7d0 | Mitsyanko Igor | uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n; |
296 | ffbbe7d0 | Mitsyanko Igor | qemu_irq i2c_irq; |
297 | ffbbe7d0 | Mitsyanko Igor | |
298 | ffbbe7d0 | Mitsyanko Igor | if (n < 8) { |
299 | ffbbe7d0 | Mitsyanko Igor | i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)]; |
300 | ffbbe7d0 | Mitsyanko Igor | } else {
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301 | ffbbe7d0 | Mitsyanko Igor | i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
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302 | ffbbe7d0 | Mitsyanko Igor | } |
303 | ffbbe7d0 | Mitsyanko Igor | |
304 | ffbbe7d0 | Mitsyanko Igor | dev = qdev_create(NULL, "exynos4210.i2c"); |
305 | ffbbe7d0 | Mitsyanko Igor | qdev_init_nofail(dev); |
306 | ffbbe7d0 | Mitsyanko Igor | busdev = sysbus_from_qdev(dev); |
307 | ffbbe7d0 | Mitsyanko Igor | sysbus_connect_irq(busdev, 0, i2c_irq);
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308 | ffbbe7d0 | Mitsyanko Igor | sysbus_mmio_map(busdev, 0, addr);
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309 | ffbbe7d0 | Mitsyanko Igor | s->i2c_if[n] = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
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310 | ffbbe7d0 | Mitsyanko Igor | } |
311 | ffbbe7d0 | Mitsyanko Igor | |
312 | ffbbe7d0 | Mitsyanko Igor | |
313 | e5a4914e | Maksim Kozlov | /*** UARTs ***/
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314 | e5a4914e | Maksim Kozlov | exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, |
315 | e5a4914e | Maksim Kozlov | EXYNOS4210_UART0_FIFO_SIZE, 0, NULL, |
316 | e5a4914e | Maksim Kozlov | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
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317 | e5a4914e | Maksim Kozlov | |
318 | e5a4914e | Maksim Kozlov | exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, |
319 | e5a4914e | Maksim Kozlov | EXYNOS4210_UART1_FIFO_SIZE, 1, NULL, |
320 | e5a4914e | Maksim Kozlov | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
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321 | e5a4914e | Maksim Kozlov | |
322 | e5a4914e | Maksim Kozlov | exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, |
323 | e5a4914e | Maksim Kozlov | EXYNOS4210_UART2_FIFO_SIZE, 2, NULL, |
324 | e5a4914e | Maksim Kozlov | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
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325 | e5a4914e | Maksim Kozlov | |
326 | e5a4914e | Maksim Kozlov | exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, |
327 | e5a4914e | Maksim Kozlov | EXYNOS4210_UART3_FIFO_SIZE, 3, NULL, |
328 | e5a4914e | Maksim Kozlov | s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
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329 | e5a4914e | Maksim Kozlov | |
330 | 30628cb1 | Mitsyanko Igor | /*** Display controller (FIMD) ***/
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331 | 30628cb1 | Mitsyanko Igor | sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
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332 | 30628cb1 | Mitsyanko Igor | s->irq_table[exynos4210_get_irq(11, 0)], |
333 | 30628cb1 | Mitsyanko Igor | s->irq_table[exynos4210_get_irq(11, 1)], |
334 | 30628cb1 | Mitsyanko Igor | s->irq_table[exynos4210_get_irq(11, 2)], |
335 | 30628cb1 | Mitsyanko Igor | NULL);
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336 | 30628cb1 | Mitsyanko Igor | |
337 | 0caa7113 | Evgeny Voevodin | return s;
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338 | 0caa7113 | Evgeny Voevodin | } |