Revision b158a785 target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 93 | 93 |
#define QFPREG(r) (r & 0x1c) |
| 94 | 94 |
#endif |
| 95 | 95 |
|
| 96 |
#define UA2005_HTRAP_MASK 0xff |
|
| 97 |
#define V8_TRAP_MASK 0x7f |
|
| 98 |
|
|
| 96 | 99 |
static int sign_extend(int x, int len) |
| 97 | 100 |
{
|
| 98 | 101 |
len = 32 - len; |
| ... | ... | |
| 2019 | 2022 |
cond = GET_FIELD(insn, 3, 6); |
| 2020 | 2023 |
if (cond == 0x8) {
|
| 2021 | 2024 |
save_state(dc, cpu_cond); |
| 2022 |
tcg_gen_helper_0_1(helper_trap, cpu_dst); |
|
| 2025 |
if ((dc->def->features & CPU_FEATURE_HYPV) && |
|
| 2026 |
supervisor(dc)) |
|
| 2027 |
tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK); |
|
| 2028 |
else |
|
| 2029 |
tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
|
| 2030 |
tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
|
| 2031 |
tcg_gen_helper_0_1(raise_exception, cpu_dst); |
|
| 2023 | 2032 |
} else if (cond != 0) {
|
| 2024 | 2033 |
TCGv r_cond = tcg_temp_new(TCG_TYPE_TL); |
| 2034 |
int l1; |
|
| 2025 | 2035 |
#ifdef TARGET_SPARC64 |
| 2026 | 2036 |
/* V9 icc/xcc */ |
| 2027 | 2037 |
int cc = GET_FIELD_SP(insn, 11, 12); |
| ... | ... | |
| 2037 | 2047 |
save_state(dc, cpu_cond); |
| 2038 | 2048 |
gen_cond(r_cond, 0, cond); |
| 2039 | 2049 |
#endif |
| 2040 |
tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond); |
|
| 2050 |
l1 = gen_new_label(); |
|
| 2051 |
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); |
|
| 2052 |
|
|
| 2053 |
if ((dc->def->features & CPU_FEATURE_HYPV) && |
|
| 2054 |
supervisor(dc)) |
|
| 2055 |
tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK); |
|
| 2056 |
else |
|
| 2057 |
tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
|
| 2058 |
tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
|
| 2059 |
tcg_gen_helper_0_1(raise_exception, cpu_dst); |
|
| 2060 |
|
|
| 2061 |
gen_set_label(l1); |
|
| 2041 | 2062 |
tcg_temp_free(r_cond); |
| 2042 | 2063 |
} |
| 2043 | 2064 |
gen_op_next_insn(); |
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