root / hw / hpet.c @ b20a0083
History | View | Annotate | Download (18.5 kB)
1 | 16b29ae1 | aliguori | /*
|
---|---|---|---|
2 | 16b29ae1 | aliguori | * High Precisition Event Timer emulation
|
3 | 16b29ae1 | aliguori | *
|
4 | 16b29ae1 | aliguori | * Copyright (c) 2007 Alexander Graf
|
5 | 16b29ae1 | aliguori | * Copyright (c) 2008 IBM Corporation
|
6 | 16b29ae1 | aliguori | *
|
7 | 16b29ae1 | aliguori | * Authors: Beth Kon <bkon@us.ibm.com>
|
8 | 16b29ae1 | aliguori | *
|
9 | 16b29ae1 | aliguori | * This library is free software; you can redistribute it and/or
|
10 | 16b29ae1 | aliguori | * modify it under the terms of the GNU Lesser General Public
|
11 | 16b29ae1 | aliguori | * License as published by the Free Software Foundation; either
|
12 | 16b29ae1 | aliguori | * version 2 of the License, or (at your option) any later version.
|
13 | 16b29ae1 | aliguori | *
|
14 | 16b29ae1 | aliguori | * This library is distributed in the hope that it will be useful,
|
15 | 16b29ae1 | aliguori | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
16 | 16b29ae1 | aliguori | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
17 | 16b29ae1 | aliguori | * Lesser General Public License for more details.
|
18 | 16b29ae1 | aliguori | *
|
19 | 16b29ae1 | aliguori | * You should have received a copy of the GNU Lesser General Public
|
20 | 16b29ae1 | aliguori | * License along with this library; if not, write to the Free Software
|
21 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
|
22 | 16b29ae1 | aliguori | *
|
23 | 16b29ae1 | aliguori | * *****************************************************************
|
24 | 16b29ae1 | aliguori | *
|
25 | 16b29ae1 | aliguori | * This driver attempts to emulate an HPET device in software.
|
26 | 16b29ae1 | aliguori | */
|
27 | 16b29ae1 | aliguori | |
28 | 16b29ae1 | aliguori | #include "hw.h" |
29 | bf4f74c0 | aurel32 | #include "pc.h" |
30 | 16b29ae1 | aliguori | #include "console.h" |
31 | 16b29ae1 | aliguori | #include "qemu-timer.h" |
32 | 16b29ae1 | aliguori | #include "hpet_emul.h" |
33 | 16b29ae1 | aliguori | |
34 | 16b29ae1 | aliguori | //#define HPET_DEBUG
|
35 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
36 | 16b29ae1 | aliguori | #define dprintf printf
|
37 | 16b29ae1 | aliguori | #else
|
38 | 16b29ae1 | aliguori | #define dprintf(...)
|
39 | 16b29ae1 | aliguori | #endif
|
40 | 16b29ae1 | aliguori | |
41 | 16b29ae1 | aliguori | static HPETState *hpet_statep;
|
42 | 16b29ae1 | aliguori | |
43 | 16b29ae1 | aliguori | uint32_t hpet_in_legacy_mode(void)
|
44 | 16b29ae1 | aliguori | { |
45 | 16b29ae1 | aliguori | if (hpet_statep)
|
46 | 16b29ae1 | aliguori | return hpet_statep->config & HPET_CFG_LEGACY;
|
47 | 16b29ae1 | aliguori | else
|
48 | 16b29ae1 | aliguori | return 0; |
49 | 16b29ae1 | aliguori | } |
50 | 16b29ae1 | aliguori | |
51 | c50c2d68 | aurel32 | static uint32_t timer_int_route(struct HPETTimer *timer) |
52 | 16b29ae1 | aliguori | { |
53 | 16b29ae1 | aliguori | uint32_t route; |
54 | 16b29ae1 | aliguori | route = (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; |
55 | 16b29ae1 | aliguori | return route;
|
56 | 16b29ae1 | aliguori | } |
57 | 16b29ae1 | aliguori | |
58 | 16b29ae1 | aliguori | static uint32_t hpet_enabled(void) |
59 | 16b29ae1 | aliguori | { |
60 | 16b29ae1 | aliguori | return hpet_statep->config & HPET_CFG_ENABLE;
|
61 | 16b29ae1 | aliguori | } |
62 | 16b29ae1 | aliguori | |
63 | 16b29ae1 | aliguori | static uint32_t timer_is_periodic(HPETTimer *t)
|
64 | 16b29ae1 | aliguori | { |
65 | 16b29ae1 | aliguori | return t->config & HPET_TN_PERIODIC;
|
66 | 16b29ae1 | aliguori | } |
67 | 16b29ae1 | aliguori | |
68 | 16b29ae1 | aliguori | static uint32_t timer_enabled(HPETTimer *t)
|
69 | 16b29ae1 | aliguori | { |
70 | 16b29ae1 | aliguori | return t->config & HPET_TN_ENABLE;
|
71 | 16b29ae1 | aliguori | } |
72 | 16b29ae1 | aliguori | |
73 | 16b29ae1 | aliguori | static uint32_t hpet_time_after(uint64_t a, uint64_t b)
|
74 | 16b29ae1 | aliguori | { |
75 | 16b29ae1 | aliguori | return ((int32_t)(b) - (int32_t)(a) < 0); |
76 | 16b29ae1 | aliguori | } |
77 | 16b29ae1 | aliguori | |
78 | 16b29ae1 | aliguori | static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
|
79 | 16b29ae1 | aliguori | { |
80 | 16b29ae1 | aliguori | return ((int64_t)(b) - (int64_t)(a) < 0); |
81 | 16b29ae1 | aliguori | } |
82 | 16b29ae1 | aliguori | |
83 | c50c2d68 | aurel32 | static uint64_t ticks_to_ns(uint64_t value)
|
84 | 16b29ae1 | aliguori | { |
85 | 16b29ae1 | aliguori | return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
|
86 | 16b29ae1 | aliguori | } |
87 | 16b29ae1 | aliguori | |
88 | c50c2d68 | aurel32 | static uint64_t ns_to_ticks(uint64_t value)
|
89 | 16b29ae1 | aliguori | { |
90 | 16b29ae1 | aliguori | return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
|
91 | 16b29ae1 | aliguori | } |
92 | 16b29ae1 | aliguori | |
93 | 16b29ae1 | aliguori | static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
|
94 | 16b29ae1 | aliguori | { |
95 | 16b29ae1 | aliguori | new &= mask; |
96 | 16b29ae1 | aliguori | new |= old & ~mask; |
97 | 16b29ae1 | aliguori | return new;
|
98 | 16b29ae1 | aliguori | } |
99 | 16b29ae1 | aliguori | |
100 | 16b29ae1 | aliguori | static int activating_bit(uint64_t old, uint64_t new, uint64_t mask) |
101 | 16b29ae1 | aliguori | { |
102 | c50c2d68 | aurel32 | return (!(old & mask) && (new & mask));
|
103 | 16b29ae1 | aliguori | } |
104 | 16b29ae1 | aliguori | |
105 | 16b29ae1 | aliguori | static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask) |
106 | 16b29ae1 | aliguori | { |
107 | c50c2d68 | aurel32 | return ((old & mask) && !(new & mask));
|
108 | 16b29ae1 | aliguori | } |
109 | 16b29ae1 | aliguori | |
110 | c50c2d68 | aurel32 | static uint64_t hpet_get_ticks(void) |
111 | 16b29ae1 | aliguori | { |
112 | 16b29ae1 | aliguori | uint64_t ticks; |
113 | 16b29ae1 | aliguori | ticks = ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset); |
114 | 16b29ae1 | aliguori | return ticks;
|
115 | 16b29ae1 | aliguori | } |
116 | 16b29ae1 | aliguori | |
117 | c50c2d68 | aurel32 | /*
|
118 | c50c2d68 | aurel32 | * calculate diff between comparator value and current ticks
|
119 | 16b29ae1 | aliguori | */
|
120 | 16b29ae1 | aliguori | static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current) |
121 | 16b29ae1 | aliguori | { |
122 | c50c2d68 | aurel32 | |
123 | 16b29ae1 | aliguori | if (t->config & HPET_TN_32BIT) {
|
124 | 16b29ae1 | aliguori | uint32_t diff, cmp; |
125 | 16b29ae1 | aliguori | cmp = (uint32_t)t->cmp; |
126 | 16b29ae1 | aliguori | diff = cmp - (uint32_t)current; |
127 | 16b29ae1 | aliguori | diff = (int32_t)diff > 0 ? diff : (uint32_t)0; |
128 | 16b29ae1 | aliguori | return (uint64_t)diff;
|
129 | 16b29ae1 | aliguori | } else {
|
130 | 16b29ae1 | aliguori | uint64_t diff, cmp; |
131 | 16b29ae1 | aliguori | cmp = t->cmp; |
132 | 16b29ae1 | aliguori | diff = cmp - current; |
133 | 16b29ae1 | aliguori | diff = (int64_t)diff > 0 ? diff : (uint64_t)0; |
134 | 16b29ae1 | aliguori | return diff;
|
135 | 16b29ae1 | aliguori | } |
136 | 16b29ae1 | aliguori | } |
137 | 16b29ae1 | aliguori | |
138 | 16b29ae1 | aliguori | static void update_irq(struct HPETTimer *timer) |
139 | 16b29ae1 | aliguori | { |
140 | 16b29ae1 | aliguori | qemu_irq irq; |
141 | 16b29ae1 | aliguori | int route;
|
142 | 16b29ae1 | aliguori | |
143 | 16b29ae1 | aliguori | if (timer->tn <= 1 && hpet_in_legacy_mode()) { |
144 | 16b29ae1 | aliguori | /* if LegacyReplacementRoute bit is set, HPET specification requires
|
145 | 16b29ae1 | aliguori | * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
|
146 | c50c2d68 | aurel32 | * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
|
147 | 16b29ae1 | aliguori | */
|
148 | 16b29ae1 | aliguori | if (timer->tn == 0) { |
149 | 16b29ae1 | aliguori | irq=timer->state->irqs[0];
|
150 | 16b29ae1 | aliguori | } else
|
151 | 16b29ae1 | aliguori | irq=timer->state->irqs[8];
|
152 | 16b29ae1 | aliguori | } else {
|
153 | 16b29ae1 | aliguori | route=timer_int_route(timer); |
154 | 16b29ae1 | aliguori | irq=timer->state->irqs[route]; |
155 | 16b29ae1 | aliguori | } |
156 | 16b29ae1 | aliguori | if (timer_enabled(timer) && hpet_enabled()) {
|
157 | 16b29ae1 | aliguori | qemu_irq_pulse(irq); |
158 | 16b29ae1 | aliguori | } |
159 | 16b29ae1 | aliguori | } |
160 | 16b29ae1 | aliguori | |
161 | 16b29ae1 | aliguori | static void hpet_save(QEMUFile *f, void *opaque) |
162 | 16b29ae1 | aliguori | { |
163 | 16b29ae1 | aliguori | HPETState *s = opaque; |
164 | 16b29ae1 | aliguori | int i;
|
165 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->config); |
166 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->isr); |
167 | 16b29ae1 | aliguori | /* save current counter value */
|
168 | c50c2d68 | aurel32 | s->hpet_counter = hpet_get_ticks(); |
169 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->hpet_counter); |
170 | 16b29ae1 | aliguori | |
171 | 16b29ae1 | aliguori | for (i = 0; i < HPET_NUM_TIMERS; i++) { |
172 | 16b29ae1 | aliguori | qemu_put_8s(f, &s->timer[i].tn); |
173 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->timer[i].config); |
174 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->timer[i].cmp); |
175 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->timer[i].fsb); |
176 | 16b29ae1 | aliguori | qemu_put_be64s(f, &s->timer[i].period); |
177 | 16b29ae1 | aliguori | qemu_put_8s(f, &s->timer[i].wrap_flag); |
178 | 16b29ae1 | aliguori | if (s->timer[i].qemu_timer) {
|
179 | 16b29ae1 | aliguori | qemu_put_timer(f, s->timer[i].qemu_timer); |
180 | 16b29ae1 | aliguori | } |
181 | 16b29ae1 | aliguori | } |
182 | 16b29ae1 | aliguori | } |
183 | 16b29ae1 | aliguori | |
184 | 16b29ae1 | aliguori | static int hpet_load(QEMUFile *f, void *opaque, int version_id) |
185 | 16b29ae1 | aliguori | { |
186 | 16b29ae1 | aliguori | HPETState *s = opaque; |
187 | 16b29ae1 | aliguori | int i;
|
188 | c50c2d68 | aurel32 | |
189 | 16b29ae1 | aliguori | if (version_id != 1) |
190 | 16b29ae1 | aliguori | return -EINVAL;
|
191 | 16b29ae1 | aliguori | |
192 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->config); |
193 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->isr); |
194 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->hpet_counter); |
195 | 16b29ae1 | aliguori | /* Recalculate the offset between the main counter and guest time */
|
196 | 16b29ae1 | aliguori | s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); |
197 | 16b29ae1 | aliguori | |
198 | 16b29ae1 | aliguori | for (i = 0; i < HPET_NUM_TIMERS; i++) { |
199 | 16b29ae1 | aliguori | qemu_get_8s(f, &s->timer[i].tn); |
200 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->timer[i].config); |
201 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->timer[i].cmp); |
202 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->timer[i].fsb); |
203 | 16b29ae1 | aliguori | qemu_get_be64s(f, &s->timer[i].period); |
204 | 16b29ae1 | aliguori | qemu_get_8s(f, &s->timer[i].wrap_flag); |
205 | 16b29ae1 | aliguori | if (s->timer[i].qemu_timer) {
|
206 | 16b29ae1 | aliguori | qemu_get_timer(f, s->timer[i].qemu_timer); |
207 | 16b29ae1 | aliguori | } |
208 | 16b29ae1 | aliguori | } |
209 | 16b29ae1 | aliguori | return 0; |
210 | 16b29ae1 | aliguori | } |
211 | 16b29ae1 | aliguori | |
212 | c50c2d68 | aurel32 | /*
|
213 | 16b29ae1 | aliguori | * timer expiration callback
|
214 | 16b29ae1 | aliguori | */
|
215 | 16b29ae1 | aliguori | static void hpet_timer(void *opaque) |
216 | 16b29ae1 | aliguori | { |
217 | 16b29ae1 | aliguori | HPETTimer *t = (HPETTimer*)opaque; |
218 | 16b29ae1 | aliguori | uint64_t diff; |
219 | 16b29ae1 | aliguori | |
220 | 16b29ae1 | aliguori | uint64_t period = t->period; |
221 | 16b29ae1 | aliguori | uint64_t cur_tick = hpet_get_ticks(); |
222 | 16b29ae1 | aliguori | |
223 | 16b29ae1 | aliguori | if (timer_is_periodic(t) && period != 0) { |
224 | 16b29ae1 | aliguori | if (t->config & HPET_TN_32BIT) {
|
225 | 16b29ae1 | aliguori | while (hpet_time_after(cur_tick, t->cmp))
|
226 | 16b29ae1 | aliguori | t->cmp = (uint32_t)(t->cmp + t->period); |
227 | 16b29ae1 | aliguori | } else
|
228 | 16b29ae1 | aliguori | while (hpet_time_after64(cur_tick, t->cmp))
|
229 | 16b29ae1 | aliguori | t->cmp += period; |
230 | 16b29ae1 | aliguori | |
231 | 16b29ae1 | aliguori | diff = hpet_calculate_diff(t, cur_tick); |
232 | c50c2d68 | aurel32 | qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) |
233 | 16b29ae1 | aliguori | + (int64_t)ticks_to_ns(diff)); |
234 | 16b29ae1 | aliguori | } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
235 | 16b29ae1 | aliguori | if (t->wrap_flag) {
|
236 | 16b29ae1 | aliguori | diff = hpet_calculate_diff(t, cur_tick); |
237 | c50c2d68 | aurel32 | qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) |
238 | 16b29ae1 | aliguori | + (int64_t)ticks_to_ns(diff)); |
239 | 16b29ae1 | aliguori | t->wrap_flag = 0;
|
240 | 16b29ae1 | aliguori | } |
241 | 16b29ae1 | aliguori | } |
242 | 16b29ae1 | aliguori | update_irq(t); |
243 | 16b29ae1 | aliguori | } |
244 | 16b29ae1 | aliguori | |
245 | 16b29ae1 | aliguori | static void hpet_set_timer(HPETTimer *t) |
246 | 16b29ae1 | aliguori | { |
247 | 16b29ae1 | aliguori | uint64_t diff; |
248 | 16b29ae1 | aliguori | uint32_t wrap_diff; /* how many ticks until we wrap? */
|
249 | 16b29ae1 | aliguori | uint64_t cur_tick = hpet_get_ticks(); |
250 | c50c2d68 | aurel32 | |
251 | 16b29ae1 | aliguori | /* whenever new timer is being set up, make sure wrap_flag is 0 */
|
252 | 16b29ae1 | aliguori | t->wrap_flag = 0;
|
253 | 16b29ae1 | aliguori | diff = hpet_calculate_diff(t, cur_tick); |
254 | 16b29ae1 | aliguori | |
255 | c50c2d68 | aurel32 | /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
|
256 | 16b29ae1 | aliguori | * counter wraps in addition to an interrupt with comparator match.
|
257 | c50c2d68 | aurel32 | */
|
258 | 16b29ae1 | aliguori | if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
|
259 | 16b29ae1 | aliguori | wrap_diff = 0xffffffff - (uint32_t)cur_tick;
|
260 | 16b29ae1 | aliguori | if (wrap_diff < (uint32_t)diff) {
|
261 | 16b29ae1 | aliguori | diff = wrap_diff; |
262 | c50c2d68 | aurel32 | t->wrap_flag = 1;
|
263 | 16b29ae1 | aliguori | } |
264 | 16b29ae1 | aliguori | } |
265 | c50c2d68 | aurel32 | qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) |
266 | 16b29ae1 | aliguori | + (int64_t)ticks_to_ns(diff)); |
267 | 16b29ae1 | aliguori | } |
268 | 16b29ae1 | aliguori | |
269 | 16b29ae1 | aliguori | static void hpet_del_timer(HPETTimer *t) |
270 | 16b29ae1 | aliguori | { |
271 | 16b29ae1 | aliguori | qemu_del_timer(t->qemu_timer); |
272 | 16b29ae1 | aliguori | } |
273 | 16b29ae1 | aliguori | |
274 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
275 | 16b29ae1 | aliguori | static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr) |
276 | 16b29ae1 | aliguori | { |
277 | 16b29ae1 | aliguori | printf("qemu: hpet_read b at %" PRIx64 "\n", addr); |
278 | 16b29ae1 | aliguori | return 0; |
279 | 16b29ae1 | aliguori | } |
280 | 16b29ae1 | aliguori | |
281 | 16b29ae1 | aliguori | static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr) |
282 | 16b29ae1 | aliguori | { |
283 | 16b29ae1 | aliguori | printf("qemu: hpet_read w at %" PRIx64 "\n", addr); |
284 | 16b29ae1 | aliguori | return 0; |
285 | 16b29ae1 | aliguori | } |
286 | 16b29ae1 | aliguori | #endif
|
287 | 16b29ae1 | aliguori | |
288 | 16b29ae1 | aliguori | static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr) |
289 | 16b29ae1 | aliguori | { |
290 | 16b29ae1 | aliguori | HPETState *s = (HPETState *)opaque; |
291 | 16b29ae1 | aliguori | uint64_t cur_tick, index; |
292 | 16b29ae1 | aliguori | |
293 | 16b29ae1 | aliguori | dprintf("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); |
294 | 16b29ae1 | aliguori | index = addr; |
295 | 16b29ae1 | aliguori | /*address range of all TN regs*/
|
296 | 16b29ae1 | aliguori | if (index >= 0x100 && index <= 0x3ff) { |
297 | 16b29ae1 | aliguori | uint8_t timer_id = (addr - 0x100) / 0x20; |
298 | 16b29ae1 | aliguori | if (timer_id > HPET_NUM_TIMERS - 1) { |
299 | 16b29ae1 | aliguori | printf("qemu: timer id out of range\n");
|
300 | 16b29ae1 | aliguori | return 0; |
301 | 16b29ae1 | aliguori | } |
302 | 16b29ae1 | aliguori | HPETTimer *timer = &s->timer[timer_id]; |
303 | 16b29ae1 | aliguori | |
304 | 16b29ae1 | aliguori | switch ((addr - 0x100) % 0x20) { |
305 | 16b29ae1 | aliguori | case HPET_TN_CFG:
|
306 | 16b29ae1 | aliguori | return timer->config;
|
307 | 16b29ae1 | aliguori | case HPET_TN_CFG + 4: // Interrupt capabilities |
308 | 16b29ae1 | aliguori | return timer->config >> 32; |
309 | 16b29ae1 | aliguori | case HPET_TN_CMP: // comparator register |
310 | 16b29ae1 | aliguori | return timer->cmp;
|
311 | 16b29ae1 | aliguori | case HPET_TN_CMP + 4: |
312 | 16b29ae1 | aliguori | return timer->cmp >> 32; |
313 | 16b29ae1 | aliguori | case HPET_TN_ROUTE:
|
314 | 16b29ae1 | aliguori | return timer->fsb >> 32; |
315 | 16b29ae1 | aliguori | default:
|
316 | 16b29ae1 | aliguori | dprintf("qemu: invalid hpet_ram_readl\n");
|
317 | 16b29ae1 | aliguori | break;
|
318 | 16b29ae1 | aliguori | } |
319 | 16b29ae1 | aliguori | } else {
|
320 | 16b29ae1 | aliguori | switch (index) {
|
321 | 16b29ae1 | aliguori | case HPET_ID:
|
322 | 16b29ae1 | aliguori | return s->capability;
|
323 | 16b29ae1 | aliguori | case HPET_PERIOD:
|
324 | c50c2d68 | aurel32 | return s->capability >> 32; |
325 | 16b29ae1 | aliguori | case HPET_CFG:
|
326 | 16b29ae1 | aliguori | return s->config;
|
327 | 16b29ae1 | aliguori | case HPET_CFG + 4: |
328 | 16b29ae1 | aliguori | dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
|
329 | 16b29ae1 | aliguori | return 0; |
330 | c50c2d68 | aurel32 | case HPET_COUNTER:
|
331 | 16b29ae1 | aliguori | if (hpet_enabled())
|
332 | 16b29ae1 | aliguori | cur_tick = hpet_get_ticks(); |
333 | c50c2d68 | aurel32 | else
|
334 | 16b29ae1 | aliguori | cur_tick = s->hpet_counter; |
335 | 16b29ae1 | aliguori | dprintf("qemu: reading counter = %" PRIx64 "\n", cur_tick); |
336 | 16b29ae1 | aliguori | return cur_tick;
|
337 | 16b29ae1 | aliguori | case HPET_COUNTER + 4: |
338 | 16b29ae1 | aliguori | if (hpet_enabled())
|
339 | 16b29ae1 | aliguori | cur_tick = hpet_get_ticks(); |
340 | c50c2d68 | aurel32 | else
|
341 | 16b29ae1 | aliguori | cur_tick = s->hpet_counter; |
342 | 16b29ae1 | aliguori | dprintf("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); |
343 | 16b29ae1 | aliguori | return cur_tick >> 32; |
344 | 16b29ae1 | aliguori | case HPET_STATUS:
|
345 | 16b29ae1 | aliguori | return s->isr;
|
346 | 16b29ae1 | aliguori | default:
|
347 | 16b29ae1 | aliguori | dprintf("qemu: invalid hpet_ram_readl\n");
|
348 | 16b29ae1 | aliguori | break;
|
349 | 16b29ae1 | aliguori | } |
350 | 16b29ae1 | aliguori | } |
351 | 16b29ae1 | aliguori | return 0; |
352 | 16b29ae1 | aliguori | } |
353 | 16b29ae1 | aliguori | |
354 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
355 | c50c2d68 | aurel32 | static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr, |
356 | 16b29ae1 | aliguori | uint32_t value) |
357 | 16b29ae1 | aliguori | { |
358 | c50c2d68 | aurel32 | printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n", |
359 | 16b29ae1 | aliguori | addr, value); |
360 | 16b29ae1 | aliguori | } |
361 | 16b29ae1 | aliguori | |
362 | c50c2d68 | aurel32 | static void hpet_ram_writew(void *opaque, target_phys_addr_t addr, |
363 | 16b29ae1 | aliguori | uint32_t value) |
364 | 16b29ae1 | aliguori | { |
365 | c50c2d68 | aurel32 | printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n", |
366 | 16b29ae1 | aliguori | addr, value); |
367 | 16b29ae1 | aliguori | } |
368 | 16b29ae1 | aliguori | #endif
|
369 | 16b29ae1 | aliguori | |
370 | 16b29ae1 | aliguori | static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, |
371 | 16b29ae1 | aliguori | uint32_t value) |
372 | 16b29ae1 | aliguori | { |
373 | 16b29ae1 | aliguori | int i;
|
374 | 16b29ae1 | aliguori | HPETState *s = (HPETState *)opaque; |
375 | 16b29ae1 | aliguori | uint64_t old_val, new_val, index; |
376 | 16b29ae1 | aliguori | |
377 | 16b29ae1 | aliguori | dprintf("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); |
378 | 16b29ae1 | aliguori | index = addr; |
379 | 16b29ae1 | aliguori | old_val = hpet_ram_readl(opaque, addr); |
380 | 16b29ae1 | aliguori | new_val = value; |
381 | 16b29ae1 | aliguori | |
382 | 16b29ae1 | aliguori | /*address range of all TN regs*/
|
383 | 16b29ae1 | aliguori | if (index >= 0x100 && index <= 0x3ff) { |
384 | 16b29ae1 | aliguori | uint8_t timer_id = (addr - 0x100) / 0x20; |
385 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
|
386 | 16b29ae1 | aliguori | HPETTimer *timer = &s->timer[timer_id]; |
387 | c50c2d68 | aurel32 | |
388 | 16b29ae1 | aliguori | switch ((addr - 0x100) % 0x20) { |
389 | 16b29ae1 | aliguori | case HPET_TN_CFG:
|
390 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
|
391 | 35730fa0 | aurel32 | timer->config = hpet_fixup_reg(new_val, old_val, |
392 | 35730fa0 | aurel32 | HPET_TN_CFG_WRITE_MASK); |
393 | 16b29ae1 | aliguori | if (new_val & HPET_TN_32BIT) {
|
394 | 16b29ae1 | aliguori | timer->cmp = (uint32_t)timer->cmp; |
395 | 16b29ae1 | aliguori | timer->period = (uint32_t)timer->period; |
396 | 16b29ae1 | aliguori | } |
397 | 16b29ae1 | aliguori | if (new_val & HPET_TIMER_TYPE_LEVEL) {
|
398 | 16b29ae1 | aliguori | printf("qemu: level-triggered hpet not supported\n");
|
399 | 16b29ae1 | aliguori | exit (-1);
|
400 | 16b29ae1 | aliguori | } |
401 | 16b29ae1 | aliguori | |
402 | 16b29ae1 | aliguori | break;
|
403 | 16b29ae1 | aliguori | case HPET_TN_CFG + 4: // Interrupt capabilities |
404 | 16b29ae1 | aliguori | dprintf("qemu: invalid HPET_TN_CFG+4 write\n");
|
405 | 16b29ae1 | aliguori | break;
|
406 | 16b29ae1 | aliguori | case HPET_TN_CMP: // comparator register |
407 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel HPET_TN_CMP \n");
|
408 | 16b29ae1 | aliguori | if (timer->config & HPET_TN_32BIT)
|
409 | 16b29ae1 | aliguori | new_val = (uint32_t)new_val; |
410 | 16b29ae1 | aliguori | if (!timer_is_periodic(timer) ||
|
411 | 16b29ae1 | aliguori | (timer->config & HPET_TN_SETVAL)) |
412 | 16b29ae1 | aliguori | timer->cmp = (timer->cmp & 0xffffffff00000000ULL)
|
413 | 16b29ae1 | aliguori | | new_val; |
414 | 37873241 | aliguori | if (timer_is_periodic(timer)) {
|
415 | 16b29ae1 | aliguori | /*
|
416 | 16b29ae1 | aliguori | * FIXME: Clamp period to reasonable min value?
|
417 | 16b29ae1 | aliguori | * Clamp period to reasonable max value
|
418 | 16b29ae1 | aliguori | */
|
419 | 16b29ae1 | aliguori | new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
420 | 16b29ae1 | aliguori | timer->period = (timer->period & 0xffffffff00000000ULL)
|
421 | 16b29ae1 | aliguori | | new_val; |
422 | 16b29ae1 | aliguori | } |
423 | 16b29ae1 | aliguori | timer->config &= ~HPET_TN_SETVAL; |
424 | 16b29ae1 | aliguori | if (hpet_enabled())
|
425 | 16b29ae1 | aliguori | hpet_set_timer(timer); |
426 | 16b29ae1 | aliguori | break;
|
427 | 16b29ae1 | aliguori | case HPET_TN_CMP + 4: // comparator register high order |
428 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
|
429 | 16b29ae1 | aliguori | if (!timer_is_periodic(timer) ||
|
430 | 16b29ae1 | aliguori | (timer->config & HPET_TN_SETVAL)) |
431 | 16b29ae1 | aliguori | timer->cmp = (timer->cmp & 0xffffffffULL)
|
432 | 16b29ae1 | aliguori | | new_val << 32;
|
433 | 16b29ae1 | aliguori | else {
|
434 | 16b29ae1 | aliguori | /*
|
435 | 16b29ae1 | aliguori | * FIXME: Clamp period to reasonable min value?
|
436 | 16b29ae1 | aliguori | * Clamp period to reasonable max value
|
437 | 16b29ae1 | aliguori | */
|
438 | c50c2d68 | aurel32 | new_val &= (timer->config |
439 | 16b29ae1 | aliguori | & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
440 | 16b29ae1 | aliguori | timer->period = (timer->period & 0xffffffffULL)
|
441 | 16b29ae1 | aliguori | | new_val << 32;
|
442 | 16b29ae1 | aliguori | } |
443 | 16b29ae1 | aliguori | timer->config &= ~HPET_TN_SETVAL; |
444 | 16b29ae1 | aliguori | if (hpet_enabled())
|
445 | 16b29ae1 | aliguori | hpet_set_timer(timer); |
446 | 16b29ae1 | aliguori | break;
|
447 | 16b29ae1 | aliguori | case HPET_TN_ROUTE + 4: |
448 | 16b29ae1 | aliguori | dprintf("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
|
449 | 16b29ae1 | aliguori | break;
|
450 | 16b29ae1 | aliguori | default:
|
451 | 16b29ae1 | aliguori | dprintf("qemu: invalid hpet_ram_writel\n");
|
452 | 16b29ae1 | aliguori | break;
|
453 | 16b29ae1 | aliguori | } |
454 | 16b29ae1 | aliguori | return;
|
455 | 16b29ae1 | aliguori | } else {
|
456 | 16b29ae1 | aliguori | switch (index) {
|
457 | 16b29ae1 | aliguori | case HPET_ID:
|
458 | 16b29ae1 | aliguori | return;
|
459 | 16b29ae1 | aliguori | case HPET_CFG:
|
460 | 35730fa0 | aurel32 | s->config = hpet_fixup_reg(new_val, old_val, |
461 | 35730fa0 | aurel32 | HPET_CFG_WRITE_MASK); |
462 | 16b29ae1 | aliguori | if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
463 | 16b29ae1 | aliguori | /* Enable main counter and interrupt generation. */
|
464 | 16b29ae1 | aliguori | s->hpet_offset = ticks_to_ns(s->hpet_counter) |
465 | 16b29ae1 | aliguori | - qemu_get_clock(vm_clock); |
466 | 16b29ae1 | aliguori | for (i = 0; i < HPET_NUM_TIMERS; i++) |
467 | 16b29ae1 | aliguori | if ((&s->timer[i])->cmp != ~0ULL) |
468 | 16b29ae1 | aliguori | hpet_set_timer(&s->timer[i]); |
469 | 16b29ae1 | aliguori | } |
470 | 16b29ae1 | aliguori | else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { |
471 | 16b29ae1 | aliguori | /* Halt main counter and disable interrupt generation. */
|
472 | c50c2d68 | aurel32 | s->hpet_counter = hpet_get_ticks(); |
473 | 16b29ae1 | aliguori | for (i = 0; i < HPET_NUM_TIMERS; i++) |
474 | 16b29ae1 | aliguori | hpet_del_timer(&s->timer[i]); |
475 | 16b29ae1 | aliguori | } |
476 | 16b29ae1 | aliguori | /* i8254 and RTC are disabled when HPET is in legacy mode */
|
477 | 16b29ae1 | aliguori | if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
478 | 16b29ae1 | aliguori | hpet_pit_disable(); |
479 | 16b29ae1 | aliguori | } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { |
480 | 16b29ae1 | aliguori | hpet_pit_enable(); |
481 | 16b29ae1 | aliguori | } |
482 | 16b29ae1 | aliguori | break;
|
483 | c50c2d68 | aurel32 | case HPET_CFG + 4: |
484 | 16b29ae1 | aliguori | dprintf("qemu: invalid HPET_CFG+4 write \n");
|
485 | 16b29ae1 | aliguori | break;
|
486 | 16b29ae1 | aliguori | case HPET_STATUS:
|
487 | 16b29ae1 | aliguori | /* FIXME: need to handle level-triggered interrupts */
|
488 | 16b29ae1 | aliguori | break;
|
489 | 16b29ae1 | aliguori | case HPET_COUNTER:
|
490 | c50c2d68 | aurel32 | if (hpet_enabled())
|
491 | c50c2d68 | aurel32 | printf("qemu: Writing counter while HPET enabled!\n");
|
492 | c50c2d68 | aurel32 | s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
|
493 | 16b29ae1 | aliguori | | value; |
494 | 16b29ae1 | aliguori | dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", |
495 | 16b29ae1 | aliguori | value, s->hpet_counter); |
496 | 16b29ae1 | aliguori | break;
|
497 | 16b29ae1 | aliguori | case HPET_COUNTER + 4: |
498 | c50c2d68 | aurel32 | if (hpet_enabled())
|
499 | c50c2d68 | aurel32 | printf("qemu: Writing counter while HPET enabled!\n");
|
500 | c50c2d68 | aurel32 | s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
|
501 | 16b29ae1 | aliguori | | (((uint64_t)value) << 32);
|
502 | 16b29ae1 | aliguori | dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", |
503 | 16b29ae1 | aliguori | value, s->hpet_counter); |
504 | 16b29ae1 | aliguori | break;
|
505 | 16b29ae1 | aliguori | default:
|
506 | 16b29ae1 | aliguori | dprintf("qemu: invalid hpet_ram_writel\n");
|
507 | 16b29ae1 | aliguori | break;
|
508 | 16b29ae1 | aliguori | } |
509 | 16b29ae1 | aliguori | } |
510 | 16b29ae1 | aliguori | } |
511 | 16b29ae1 | aliguori | |
512 | 16b29ae1 | aliguori | static CPUReadMemoryFunc *hpet_ram_read[] = {
|
513 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
514 | 16b29ae1 | aliguori | hpet_ram_readb, |
515 | 16b29ae1 | aliguori | hpet_ram_readw, |
516 | 16b29ae1 | aliguori | #else
|
517 | 16b29ae1 | aliguori | NULL,
|
518 | 16b29ae1 | aliguori | NULL,
|
519 | 16b29ae1 | aliguori | #endif
|
520 | 16b29ae1 | aliguori | hpet_ram_readl, |
521 | 16b29ae1 | aliguori | }; |
522 | 16b29ae1 | aliguori | |
523 | 16b29ae1 | aliguori | static CPUWriteMemoryFunc *hpet_ram_write[] = {
|
524 | 16b29ae1 | aliguori | #ifdef HPET_DEBUG
|
525 | 16b29ae1 | aliguori | hpet_ram_writeb, |
526 | 16b29ae1 | aliguori | hpet_ram_writew, |
527 | 16b29ae1 | aliguori | #else
|
528 | 16b29ae1 | aliguori | NULL,
|
529 | 16b29ae1 | aliguori | NULL,
|
530 | 16b29ae1 | aliguori | #endif
|
531 | 16b29ae1 | aliguori | hpet_ram_writel, |
532 | 16b29ae1 | aliguori | }; |
533 | 16b29ae1 | aliguori | |
534 | 16b29ae1 | aliguori | static void hpet_reset(void *opaque) { |
535 | 16b29ae1 | aliguori | HPETState *s = opaque; |
536 | 16b29ae1 | aliguori | int i;
|
537 | 16b29ae1 | aliguori | static int count = 0; |
538 | 16b29ae1 | aliguori | |
539 | 16b29ae1 | aliguori | for (i=0; i<HPET_NUM_TIMERS; i++) { |
540 | 16b29ae1 | aliguori | HPETTimer *timer = &s->timer[i]; |
541 | 16b29ae1 | aliguori | hpet_del_timer(timer); |
542 | 16b29ae1 | aliguori | timer->tn = i; |
543 | 16b29ae1 | aliguori | timer->cmp = ~0ULL;
|
544 | 16b29ae1 | aliguori | timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; |
545 | 16b29ae1 | aliguori | /* advertise availability of irqs 5,10,11 */
|
546 | 16b29ae1 | aliguori | timer->config |= 0x00000c20ULL << 32; |
547 | 16b29ae1 | aliguori | timer->state = s; |
548 | 16b29ae1 | aliguori | timer->period = 0ULL;
|
549 | 16b29ae1 | aliguori | timer->wrap_flag = 0;
|
550 | 16b29ae1 | aliguori | } |
551 | 16b29ae1 | aliguori | |
552 | 16b29ae1 | aliguori | s->hpet_counter = 0ULL;
|
553 | 16b29ae1 | aliguori | s->hpet_offset = 0ULL;
|
554 | 16b29ae1 | aliguori | /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
|
555 | 16b29ae1 | aliguori | s->capability = 0x8086a201ULL;
|
556 | 16b29ae1 | aliguori | s->capability |= ((HPET_CLK_PERIOD) << 32);
|
557 | 16b29ae1 | aliguori | if (count > 0) |
558 | c50c2d68 | aurel32 | /* we don't enable pit when hpet_reset is first called (by hpet_init)
|
559 | 16b29ae1 | aliguori | * because hpet is taking over for pit here. On subsequent invocations,
|
560 | 16b29ae1 | aliguori | * hpet_reset is called due to system reset. At this point control must
|
561 | c50c2d68 | aurel32 | * be returned to pit until SW reenables hpet.
|
562 | 16b29ae1 | aliguori | */
|
563 | 16b29ae1 | aliguori | hpet_pit_enable(); |
564 | 16b29ae1 | aliguori | count = 1;
|
565 | 16b29ae1 | aliguori | } |
566 | 16b29ae1 | aliguori | |
567 | 16b29ae1 | aliguori | |
568 | 16b29ae1 | aliguori | void hpet_init(qemu_irq *irq) {
|
569 | 16b29ae1 | aliguori | int i, iomemtype;
|
570 | 16b29ae1 | aliguori | HPETState *s; |
571 | c50c2d68 | aurel32 | |
572 | 16b29ae1 | aliguori | dprintf ("hpet_init\n");
|
573 | 16b29ae1 | aliguori | |
574 | 16b29ae1 | aliguori | s = qemu_mallocz(sizeof(HPETState));
|
575 | 16b29ae1 | aliguori | hpet_statep = s; |
576 | 16b29ae1 | aliguori | s->irqs = irq; |
577 | 16b29ae1 | aliguori | for (i=0; i<HPET_NUM_TIMERS; i++) { |
578 | 16b29ae1 | aliguori | HPETTimer *timer = &s->timer[i]; |
579 | 16b29ae1 | aliguori | timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer); |
580 | 16b29ae1 | aliguori | } |
581 | 16b29ae1 | aliguori | hpet_reset(s); |
582 | 16b29ae1 | aliguori | register_savevm("hpet", -1, 1, hpet_save, hpet_load, s); |
583 | 8217606e | Jan Kiszka | qemu_register_reset(hpet_reset, 0, s);
|
584 | 16b29ae1 | aliguori | /* HPET Area */
|
585 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(hpet_ram_read, |
586 | 16b29ae1 | aliguori | hpet_ram_write, s); |
587 | 16b29ae1 | aliguori | cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
|
588 | 16b29ae1 | aliguori | } |