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1 | 7e1543c2 | pbrook | /*
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2 | 7e1543c2 | pbrook | * ARM AMBA PrimeCell PL031 RTC
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3 | 7e1543c2 | pbrook | *
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4 | 7e1543c2 | pbrook | * Copyright (c) 2007 CodeSourcery
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5 | 7e1543c2 | pbrook | *
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6 | 7e1543c2 | pbrook | * This file is free software; you can redistribute it and/or modify
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7 | 7e1543c2 | pbrook | * it under the terms of the GNU General Public License version 2 as
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8 | 7e1543c2 | pbrook | * published by the Free Software Foundation.
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9 | 7e1543c2 | pbrook | *
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10 | 7e1543c2 | pbrook | */
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11 | 7e1543c2 | pbrook | |
12 | 87ecb68b | pbrook | #include "hw.h" |
13 | 87ecb68b | pbrook | #include "primecell.h" |
14 | 87ecb68b | pbrook | #include "qemu-timer.h" |
15 | 87ecb68b | pbrook | #include "sysemu.h" |
16 | 7e1543c2 | pbrook | |
17 | 7e1543c2 | pbrook | //#define DEBUG_PL031
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18 | 7e1543c2 | pbrook | |
19 | 7e1543c2 | pbrook | #ifdef DEBUG_PL031
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20 | 7e1543c2 | pbrook | #define DPRINTF(fmt, args...) \
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21 | 7e1543c2 | pbrook | do { printf("pl031: " fmt , ##args); } while (0) |
22 | 7e1543c2 | pbrook | #else
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23 | 7e1543c2 | pbrook | #define DPRINTF(fmt, args...) do {} while(0) |
24 | 7e1543c2 | pbrook | #endif
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25 | 7e1543c2 | pbrook | |
26 | 7e1543c2 | pbrook | #define RTC_DR 0x00 /* Data read register */ |
27 | 7e1543c2 | pbrook | #define RTC_MR 0x04 /* Match register */ |
28 | 7e1543c2 | pbrook | #define RTC_LR 0x08 /* Data load register */ |
29 | 7e1543c2 | pbrook | #define RTC_CR 0x0c /* Control register */ |
30 | 7e1543c2 | pbrook | #define RTC_IMSC 0x10 /* Interrupt mask and set register */ |
31 | 7e1543c2 | pbrook | #define RTC_RIS 0x14 /* Raw interrupt status register */ |
32 | 7e1543c2 | pbrook | #define RTC_MIS 0x18 /* Masked interrupt status register */ |
33 | 7e1543c2 | pbrook | #define RTC_ICR 0x1c /* Interrupt clear register */ |
34 | 7e1543c2 | pbrook | |
35 | 7e1543c2 | pbrook | typedef struct { |
36 | 7e1543c2 | pbrook | QEMUTimer *timer; |
37 | 7e1543c2 | pbrook | qemu_irq irq; |
38 | 7e1543c2 | pbrook | |
39 | 7e1543c2 | pbrook | uint32_t tick_offset; |
40 | 7e1543c2 | pbrook | |
41 | 7e1543c2 | pbrook | uint32_t mr; |
42 | 7e1543c2 | pbrook | uint32_t lr; |
43 | 7e1543c2 | pbrook | uint32_t cr; |
44 | 7e1543c2 | pbrook | uint32_t im; |
45 | 7e1543c2 | pbrook | uint32_t is; |
46 | 7e1543c2 | pbrook | } pl031_state; |
47 | 7e1543c2 | pbrook | |
48 | 7e1543c2 | pbrook | static const unsigned char pl031_id[] = { |
49 | 7e1543c2 | pbrook | 0x31, 0x10, 0x14, 0x00, /* Device ID */ |
50 | 7e1543c2 | pbrook | 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */ |
51 | 7e1543c2 | pbrook | }; |
52 | 7e1543c2 | pbrook | |
53 | 7e1543c2 | pbrook | static void pl031_update(pl031_state *s) |
54 | 7e1543c2 | pbrook | { |
55 | 7e1543c2 | pbrook | qemu_set_irq(s->irq, s->is & s->im); |
56 | 7e1543c2 | pbrook | } |
57 | 7e1543c2 | pbrook | |
58 | 7e1543c2 | pbrook | static void pl031_interrupt(void * opaque) |
59 | 7e1543c2 | pbrook | { |
60 | 7e1543c2 | pbrook | pl031_state *s = (pl031_state *)opaque; |
61 | 7e1543c2 | pbrook | |
62 | 7e1543c2 | pbrook | s->im = 1;
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63 | 7e1543c2 | pbrook | DPRINTF("Alarm raised\n");
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64 | 7e1543c2 | pbrook | pl031_update(s); |
65 | 7e1543c2 | pbrook | } |
66 | 7e1543c2 | pbrook | |
67 | 7e1543c2 | pbrook | static uint32_t pl031_get_count(pl031_state *s)
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68 | 7e1543c2 | pbrook | { |
69 | 7e1543c2 | pbrook | /* This assumes qemu_get_clock returns the time since the machine was
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70 | 7e1543c2 | pbrook | created. */
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71 | 7e1543c2 | pbrook | return s->tick_offset + qemu_get_clock(vm_clock) / ticks_per_sec;
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72 | 7e1543c2 | pbrook | } |
73 | 7e1543c2 | pbrook | |
74 | 7e1543c2 | pbrook | static void pl031_set_alarm(pl031_state *s) |
75 | 7e1543c2 | pbrook | { |
76 | 7e1543c2 | pbrook | int64_t now; |
77 | 7e1543c2 | pbrook | uint32_t ticks; |
78 | 7e1543c2 | pbrook | |
79 | 7e1543c2 | pbrook | now = qemu_get_clock(vm_clock); |
80 | 7e1543c2 | pbrook | ticks = s->tick_offset + now / ticks_per_sec; |
81 | 7e1543c2 | pbrook | |
82 | 7e1543c2 | pbrook | /* The timer wraps around. This subtraction also wraps in the same way,
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83 | 7e1543c2 | pbrook | and gives correct results when alarm < now_ticks. */
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84 | 7e1543c2 | pbrook | ticks = s->mr - ticks; |
85 | 7e1543c2 | pbrook | DPRINTF("Alarm set in %ud ticks\n", ticks);
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86 | 7e1543c2 | pbrook | if (ticks == 0) { |
87 | 7e1543c2 | pbrook | qemu_del_timer(s->timer); |
88 | 7e1543c2 | pbrook | pl031_interrupt(s); |
89 | 7e1543c2 | pbrook | } else {
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90 | 7e1543c2 | pbrook | qemu_mod_timer(s->timer, now + (int64_t)ticks * ticks_per_sec); |
91 | 7e1543c2 | pbrook | } |
92 | 7e1543c2 | pbrook | } |
93 | 7e1543c2 | pbrook | |
94 | 7e1543c2 | pbrook | static uint32_t pl031_read(void *opaque, target_phys_addr_t offset) |
95 | 7e1543c2 | pbrook | { |
96 | 7e1543c2 | pbrook | pl031_state *s = (pl031_state *)opaque; |
97 | 7e1543c2 | pbrook | |
98 | 7e1543c2 | pbrook | if (offset >= 0xfe0 && offset < 0x1000) |
99 | 7e1543c2 | pbrook | return pl031_id[(offset - 0xfe0) >> 2]; |
100 | 7e1543c2 | pbrook | |
101 | 7e1543c2 | pbrook | switch (offset) {
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102 | 7e1543c2 | pbrook | case RTC_DR:
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103 | 7e1543c2 | pbrook | return pl031_get_count(s);
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104 | 7e1543c2 | pbrook | case RTC_MR:
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105 | 7e1543c2 | pbrook | return s->mr;
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106 | 7e1543c2 | pbrook | case RTC_IMSC:
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107 | 7e1543c2 | pbrook | return s->im;
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108 | 7e1543c2 | pbrook | case RTC_RIS:
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109 | 7e1543c2 | pbrook | return s->is;
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110 | 7e1543c2 | pbrook | case RTC_LR:
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111 | 7e1543c2 | pbrook | return s->lr;
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112 | 7e1543c2 | pbrook | case RTC_CR:
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113 | 7e1543c2 | pbrook | /* RTC is permanently enabled. */
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114 | 7e1543c2 | pbrook | return 1; |
115 | 7e1543c2 | pbrook | case RTC_MIS:
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116 | 7e1543c2 | pbrook | return s->is & s->im;
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117 | 7e1543c2 | pbrook | case RTC_ICR:
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118 | 7e1543c2 | pbrook | fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n",
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119 | 7e1543c2 | pbrook | (int)offset);
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120 | 7e1543c2 | pbrook | break;
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121 | 7e1543c2 | pbrook | default:
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122 | 7e1543c2 | pbrook | cpu_abort(cpu_single_env, "pl031_read: Bad offset 0x%x\n",
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123 | 7e1543c2 | pbrook | (int)offset);
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124 | 7e1543c2 | pbrook | break;
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125 | 7e1543c2 | pbrook | } |
126 | 7e1543c2 | pbrook | |
127 | 7e1543c2 | pbrook | return 0; |
128 | 7e1543c2 | pbrook | } |
129 | 7e1543c2 | pbrook | |
130 | 7e1543c2 | pbrook | static void pl031_write(void * opaque, target_phys_addr_t offset, |
131 | 7e1543c2 | pbrook | uint32_t value) |
132 | 7e1543c2 | pbrook | { |
133 | 7e1543c2 | pbrook | pl031_state *s = (pl031_state *)opaque; |
134 | 7e1543c2 | pbrook | |
135 | 7e1543c2 | pbrook | |
136 | 7e1543c2 | pbrook | switch (offset) {
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137 | 7e1543c2 | pbrook | case RTC_LR:
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138 | 7e1543c2 | pbrook | s->tick_offset += value - pl031_get_count(s); |
139 | 7e1543c2 | pbrook | pl031_set_alarm(s); |
140 | 7e1543c2 | pbrook | break;
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141 | 7e1543c2 | pbrook | case RTC_MR:
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142 | 7e1543c2 | pbrook | s->mr = value; |
143 | 7e1543c2 | pbrook | pl031_set_alarm(s); |
144 | 7e1543c2 | pbrook | break;
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145 | 7e1543c2 | pbrook | case RTC_IMSC:
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146 | 7e1543c2 | pbrook | s->im = value & 1;
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147 | 7e1543c2 | pbrook | DPRINTF("Interrupt mask %d\n", s->im);
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148 | 7e1543c2 | pbrook | pl031_update(s); |
149 | 7e1543c2 | pbrook | break;
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150 | 7e1543c2 | pbrook | case RTC_ICR:
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151 | 7e1543c2 | pbrook | /* The PL031 documentation (DDI0224B) states that the interupt is
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152 | 7e1543c2 | pbrook | cleared when bit 0 of the written value is set. However the
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153 | 7e1543c2 | pbrook | arm926e documentation (DDI0287B) states that the interrupt is
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154 | 7e1543c2 | pbrook | cleared when any value is written. */
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155 | 7e1543c2 | pbrook | DPRINTF("Interrupt cleared");
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156 | 7e1543c2 | pbrook | s->is = 0;
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157 | 7e1543c2 | pbrook | pl031_update(s); |
158 | 7e1543c2 | pbrook | break;
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159 | 7e1543c2 | pbrook | case RTC_CR:
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160 | 7e1543c2 | pbrook | /* Written value is ignored. */
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161 | 7e1543c2 | pbrook | break;
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162 | 7e1543c2 | pbrook | |
163 | 7e1543c2 | pbrook | case RTC_DR:
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164 | 7e1543c2 | pbrook | case RTC_MIS:
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165 | 7e1543c2 | pbrook | case RTC_RIS:
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166 | 7e1543c2 | pbrook | fprintf(stderr, "qemu: pl031_write: Unexpected offset 0x%x\n",
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167 | 7e1543c2 | pbrook | (int)offset);
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168 | 7e1543c2 | pbrook | break;
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169 | 7e1543c2 | pbrook | |
170 | 7e1543c2 | pbrook | default:
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171 | 7e1543c2 | pbrook | cpu_abort(cpu_single_env, "pl031_write: Bad offset 0x%x\n",
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172 | 7e1543c2 | pbrook | (int)offset);
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173 | 7e1543c2 | pbrook | break;
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174 | 7e1543c2 | pbrook | } |
175 | 7e1543c2 | pbrook | } |
176 | 7e1543c2 | pbrook | |
177 | 7e1543c2 | pbrook | static CPUWriteMemoryFunc * pl031_writefn[] = {
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178 | 7e1543c2 | pbrook | pl031_write, |
179 | 7e1543c2 | pbrook | pl031_write, |
180 | 7e1543c2 | pbrook | pl031_write |
181 | 7e1543c2 | pbrook | }; |
182 | 7e1543c2 | pbrook | |
183 | 7e1543c2 | pbrook | static CPUReadMemoryFunc * pl031_readfn[] = {
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184 | 7e1543c2 | pbrook | pl031_read, |
185 | 7e1543c2 | pbrook | pl031_read, |
186 | 7e1543c2 | pbrook | pl031_read |
187 | 7e1543c2 | pbrook | }; |
188 | 7e1543c2 | pbrook | |
189 | 7e1543c2 | pbrook | void pl031_init(uint32_t base, qemu_irq irq)
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190 | 7e1543c2 | pbrook | { |
191 | 7e1543c2 | pbrook | int iomemtype;
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192 | 7e1543c2 | pbrook | pl031_state *s; |
193 | f6503059 | balrog | struct tm tm;
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194 | 7e1543c2 | pbrook | |
195 | 7e1543c2 | pbrook | s = qemu_mallocz(sizeof(pl031_state));
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196 | 7e1543c2 | pbrook | |
197 | 7e1543c2 | pbrook | iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
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198 | 7e1543c2 | pbrook | if (iomemtype == -1) |
199 | 7e1543c2 | pbrook | cpu_abort(cpu_single_env, "pl031_init: Can't register I/O memory\n");
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200 | 7e1543c2 | pbrook | |
201 | 7e1543c2 | pbrook | cpu_register_physical_memory(base, 0x00001000, iomemtype);
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202 | 7e1543c2 | pbrook | |
203 | 7e1543c2 | pbrook | s->irq = irq; |
204 | 7e1543c2 | pbrook | /* ??? We assume vm_clock is zero at this point. */
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205 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
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206 | 0cd2df75 | aurel32 | s->tick_offset = mktimegm(&tm); |
207 | 7e1543c2 | pbrook | |
208 | 7e1543c2 | pbrook | s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s); |
209 | 7e1543c2 | pbrook | } |