root / hw / etraxfs_pic.c @ b23b0fd0
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/*
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* QEMU ETRAX Interrupt Controller.
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*
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* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h> |
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#include "hw.h" |
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#include "pc.h" |
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#include "etraxfs.h" |
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#define D(x)
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#define R_RW_MASK 0 |
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#define R_R_VECT 1 |
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#define R_R_MASKED_VECT 2 |
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#define R_R_NMI 3 |
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#define R_R_GURU 4 |
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#define R_MAX 5 |
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struct fs_pic_state
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{ |
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CPUState *env; |
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uint32_t regs[R_MAX]; |
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}; |
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static void pic_update(struct fs_pic_state *fs) |
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{ |
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CPUState *env = fs->env; |
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uint32_t vector = 0;
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int i;
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fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK]; |
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/* The ETRAX interrupt controller signals interrupts to teh core
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through an interrupt request wire and an irq vector bus. If
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multiple interrupts are simultaneously active it chooses vector
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0x30 and lets the sw choose the priorities. */
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if (fs->regs[R_R_MASKED_VECT]) {
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uint32_t mv = fs->regs[R_R_MASKED_VECT]; |
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for (i = 0; i < 31; i++) { |
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if (mv & 1) { |
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vector = 0x31 + i;
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/* Check for multiple interrupts. */
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if (mv > 1) |
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vector = 0x30;
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break;
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} |
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mv >>= 1;
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} |
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if (vector) {
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env->interrupt_vector = vector; |
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D(printf("%s vector=%x\n", __func__, vector));
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} else {
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env->interrupt_vector = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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D(printf("%s reset irqs\n", __func__));
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} |
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} |
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static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) |
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{ |
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struct fs_pic_state *fs = opaque;
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uint32_t rval; |
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rval = fs->regs[addr >> 2];
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D(printf("%s %x=%x\n", __func__, addr, rval));
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return rval;
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} |
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static void |
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pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{ |
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struct fs_pic_state *fs = opaque;
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D(printf("%s addr=%x val=%x\n", __func__, addr, value));
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if (addr == R_RW_MASK) {
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fs->regs[R_RW_MASK] = value; |
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pic_update(fs); |
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} |
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} |
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static CPUReadMemoryFunc *pic_read[] = {
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NULL, NULL, |
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&pic_readl, |
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}; |
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static CPUWriteMemoryFunc *pic_write[] = {
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NULL, NULL, |
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&pic_writel, |
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}; |
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void pic_info(Monitor *mon)
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{ |
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} |
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void irq_info(Monitor *mon)
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{ |
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} |
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static void irq_handler(void *opaque, int irq, int level) |
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{ |
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struct fs_pic_state *fs = (void *)opaque; |
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irq -= 1;
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fs->regs[R_R_VECT] &= ~(1 << irq);
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fs->regs[R_R_VECT] |= (!!level << irq); |
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pic_update(fs); |
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} |
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static void nmi_handler(void *opaque, int irq, int level) |
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{ |
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struct fs_pic_state *fs = (void *)opaque; |
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CPUState *env = fs->env; |
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uint32_t mask; |
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mask = 1 << irq;
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if (level)
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fs->regs[R_R_NMI] |= mask; |
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else
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fs->regs[R_R_NMI] &= ~mask; |
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if (fs->regs[R_R_NMI])
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cpu_interrupt(env, CPU_INTERRUPT_NMI); |
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else
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cpu_reset_interrupt(env, CPU_INTERRUPT_NMI); |
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} |
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static void guru_handler(void *opaque, int irq, int level) |
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{ |
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struct fs_pic_state *fs = (void *)opaque; |
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cpu_abort(fs->env, "%s unsupported exception\n", __func__);
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} |
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struct etraxfs_pic *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
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{ |
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struct fs_pic_state *fs = NULL; |
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struct etraxfs_pic *pic = NULL; |
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int intr_vect_regs;
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pic = qemu_mallocz(sizeof *pic);
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pic->internal = fs = qemu_mallocz(sizeof *fs);
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fs->env = env; |
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pic->irq = qemu_allocate_irqs(irq_handler, fs, 30);
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pic->nmi = qemu_allocate_irqs(nmi_handler, fs, 2);
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pic->guru = qemu_allocate_irqs(guru_handler, fs, 1);
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intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
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cpu_register_physical_memory(base, R_MAX * 4, intr_vect_regs);
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return pic;
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} |