Revision b2d9dfe9
| b/hw/net/xilinx_axienet.c | ||
|---|---|---|
| 853 | 853 |
.cleanup = eth_cleanup, |
| 854 | 854 |
}; |
| 855 | 855 |
|
| 856 |
static int xilinx_enet_init(SysBusDevice *dev)
|
|
| 856 |
static void xilinx_enet_realize(DeviceState *dev, Error **errp)
|
|
| 857 | 857 |
{
|
| 858 | 858 |
XilinxAXIEnet *s = XILINX_AXI_ENET(dev); |
| 859 | 859 |
|
| 860 |
sysbus_init_irq(dev, &s->irq); |
|
| 861 |
|
|
| 862 |
memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000); |
|
| 863 |
sysbus_init_mmio(dev, &s->iomem); |
|
| 864 |
|
|
| 865 | 860 |
qemu_macaddr_default_if_unset(&s->conf.macaddr); |
| 866 | 861 |
s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf, |
| 867 |
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
|
|
| 862 |
object_get_typename(OBJECT(dev)), dev->id, s); |
|
| 868 | 863 |
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
| 869 | 864 |
|
| 870 | 865 |
tdk_init(&s->TEMAC.phy); |
| ... | ... | |
| 873 | 868 |
s->TEMAC.parent = s; |
| 874 | 869 |
|
| 875 | 870 |
s->rxmem = g_malloc(s->c_rxmem); |
| 876 |
|
|
| 877 |
return 0; |
|
| 878 | 871 |
} |
| 879 | 872 |
|
| 880 |
static void xilinx_enet_initfn(Object *obj)
|
|
| 873 |
static void xilinx_enet_init(Object *obj) |
|
| 881 | 874 |
{
|
| 882 | 875 |
XilinxAXIEnet *s = XILINX_AXI_ENET(obj); |
| 876 |
SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
|
| 883 | 877 |
Error *errp = NULL; |
| 884 | 878 |
|
| 885 | 879 |
object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE, |
| 886 | 880 |
(Object **) &s->tx_dev, &errp); |
| 887 | 881 |
assert_no_error(errp); |
| 882 |
|
|
| 883 |
sysbus_init_irq(sbd, &s->irq); |
|
| 884 |
|
|
| 885 |
memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000); |
|
| 886 |
sysbus_init_mmio(sbd, &s->iomem); |
|
| 888 | 887 |
} |
| 889 | 888 |
|
| 890 | 889 |
static Property xilinx_enet_properties[] = {
|
| ... | ... | |
| 898 | 897 |
static void xilinx_enet_class_init(ObjectClass *klass, void *data) |
| 899 | 898 |
{
|
| 900 | 899 |
DeviceClass *dc = DEVICE_CLASS(klass); |
| 901 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
|
| 902 | 900 |
StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass); |
| 903 | 901 |
|
| 904 |
k->init = xilinx_enet_init;
|
|
| 902 |
dc->realize = xilinx_enet_realize;
|
|
| 905 | 903 |
dc->props = xilinx_enet_properties; |
| 906 | 904 |
dc->reset = xilinx_axienet_reset; |
| 907 | 905 |
ssc->push = axienet_stream_push; |
| ... | ... | |
| 912 | 910 |
.parent = TYPE_SYS_BUS_DEVICE, |
| 913 | 911 |
.instance_size = sizeof(XilinxAXIEnet), |
| 914 | 912 |
.class_init = xilinx_enet_class_init, |
| 915 |
.instance_init = xilinx_enet_initfn,
|
|
| 913 |
.instance_init = xilinx_enet_init, |
|
| 916 | 914 |
.interfaces = (InterfaceInfo[]) {
|
| 917 | 915 |
{ TYPE_STREAM_SLAVE },
|
| 918 | 916 |
{ }
|
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