| 168 |
168 |
if (IS_M(env))
|
| 169 |
169 |
env->uncached_cpsr &= ~CPSR_I;
|
| 170 |
170 |
env->vfp.xregs[ARM_VFP_FPEXC] = 0;
|
|
171 |
env->cp15.c2_base_mask = 0xffffc000u;
|
| 171 |
172 |
#endif
|
| 172 |
173 |
env->regs[15] = 0;
|
| 173 |
174 |
tlb_flush(env, 1);
|
| ... | ... | |
| 910 |
911 |
}
|
| 911 |
912 |
}
|
| 912 |
913 |
|
|
914 |
static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
|
|
915 |
{
|
|
916 |
uint32_t table;
|
|
917 |
|
|
918 |
if (address & env->cp15.c2_mask)
|
|
919 |
table = env->cp15.c2_base1 & 0xffffc000;
|
|
920 |
else
|
|
921 |
table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
|
|
922 |
|
|
923 |
table |= (address >> 18) & 0x3ffc;
|
|
924 |
return table;
|
|
925 |
}
|
|
926 |
|
| 913 |
927 |
static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
|
| 914 |
928 |
int is_user, uint32_t *phys_ptr, int *prot)
|
| 915 |
929 |
{
|
| ... | ... | |
| 923 |
937 |
|
| 924 |
938 |
/* Pagetable walk. */
|
| 925 |
939 |
/* Lookup l1 descriptor. */
|
| 926 |
|
if (address & env->cp15.c2_mask)
|
| 927 |
|
table = env->cp15.c2_base1;
|
| 928 |
|
else
|
| 929 |
|
table = env->cp15.c2_base0;
|
| 930 |
|
table = (table & 0xffffc000) | ((address >> 18) & 0x3ffc);
|
|
940 |
table = get_level1_table_address(env, address);
|
| 931 |
941 |
desc = ldl_phys(table);
|
| 932 |
942 |
type = (desc & 3);
|
| 933 |
943 |
domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
|
| ... | ... | |
| 1015 |
1025 |
|
| 1016 |
1026 |
/* Pagetable walk. */
|
| 1017 |
1027 |
/* Lookup l1 descriptor. */
|
| 1018 |
|
if (address & env->cp15.c2_mask)
|
| 1019 |
|
table = env->cp15.c2_base1;
|
| 1020 |
|
else
|
| 1021 |
|
table = env->cp15.c2_base0;
|
| 1022 |
|
table = (table & 0xffffc000) | ((address >> 18) & 0x3ffc);
|
|
1028 |
table = get_level1_table_address(env, address);
|
| 1023 |
1029 |
desc = ldl_phys(table);
|
| 1024 |
1030 |
type = (desc & 3);
|
| 1025 |
1031 |
if (type == 0) {
|
| ... | ... | |
| 1365 |
1371 |
env->cp15.c2_base1 = val;
|
| 1366 |
1372 |
break;
|
| 1367 |
1373 |
case 2:
|
|
1374 |
val &= 7;
|
|
1375 |
env->cp15.c2_control = val;
|
| 1368 |
1376 |
env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
|
|
1377 |
env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
|
| 1369 |
1378 |
break;
|
| 1370 |
1379 |
default:
|
| 1371 |
1380 |
goto bad_reg;
|
| ... | ... | |
| 1683 |
1692 |
case 1:
|
| 1684 |
1693 |
return env->cp15.c2_base1;
|
| 1685 |
1694 |
case 2:
|
| 1686 |
|
{
|
| 1687 |
|
int n;
|
| 1688 |
|
uint32_t mask;
|
| 1689 |
|
n = 0;
|
| 1690 |
|
mask = env->cp15.c2_mask;
|
| 1691 |
|
while (mask) {
|
| 1692 |
|
n++;
|
| 1693 |
|
mask <<= 1;
|
| 1694 |
|
}
|
| 1695 |
|
return n;
|
| 1696 |
|
}
|
|
1695 |
return env->cp15.c2_control;
|
| 1697 |
1696 |
default:
|
| 1698 |
1697 |
goto bad_reg;
|
| 1699 |
1698 |
}
|