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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU 16450 UART emulation
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3 | 80cabfad | bellard | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 80cabfad | bellard | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 80cabfad | bellard | #include "vl.h" |
25 | 80cabfad | bellard | |
26 | 80cabfad | bellard | //#define DEBUG_SERIAL
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27 | 80cabfad | bellard | |
28 | 80cabfad | bellard | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
29 | 80cabfad | bellard | |
30 | 80cabfad | bellard | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
31 | 80cabfad | bellard | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
32 | 80cabfad | bellard | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
33 | 80cabfad | bellard | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
34 | 80cabfad | bellard | |
35 | 80cabfad | bellard | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
36 | 80cabfad | bellard | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
37 | 80cabfad | bellard | |
38 | 80cabfad | bellard | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
39 | 80cabfad | bellard | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
40 | 80cabfad | bellard | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
41 | 80cabfad | bellard | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
42 | 80cabfad | bellard | |
43 | 80cabfad | bellard | /*
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44 | 80cabfad | bellard | * These are the definitions for the Modem Control Register
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45 | 80cabfad | bellard | */
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46 | 80cabfad | bellard | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
47 | 80cabfad | bellard | #define UART_MCR_OUT2 0x08 /* Out2 complement */ |
48 | 80cabfad | bellard | #define UART_MCR_OUT1 0x04 /* Out1 complement */ |
49 | 80cabfad | bellard | #define UART_MCR_RTS 0x02 /* RTS complement */ |
50 | 80cabfad | bellard | #define UART_MCR_DTR 0x01 /* DTR complement */ |
51 | 80cabfad | bellard | |
52 | 80cabfad | bellard | /*
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53 | 80cabfad | bellard | * These are the definitions for the Modem Status Register
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54 | 80cabfad | bellard | */
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55 | 80cabfad | bellard | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
56 | 80cabfad | bellard | #define UART_MSR_RI 0x40 /* Ring Indicator */ |
57 | 80cabfad | bellard | #define UART_MSR_DSR 0x20 /* Data Set Ready */ |
58 | 80cabfad | bellard | #define UART_MSR_CTS 0x10 /* Clear to Send */ |
59 | 80cabfad | bellard | #define UART_MSR_DDCD 0x08 /* Delta DCD */ |
60 | 80cabfad | bellard | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
61 | 80cabfad | bellard | #define UART_MSR_DDSR 0x02 /* Delta DSR */ |
62 | 80cabfad | bellard | #define UART_MSR_DCTS 0x01 /* Delta CTS */ |
63 | 80cabfad | bellard | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
64 | 80cabfad | bellard | |
65 | 80cabfad | bellard | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
66 | 80cabfad | bellard | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
67 | 80cabfad | bellard | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
68 | 80cabfad | bellard | #define UART_LSR_FE 0x08 /* Frame error indicator */ |
69 | 80cabfad | bellard | #define UART_LSR_PE 0x04 /* Parity error indicator */ |
70 | 80cabfad | bellard | #define UART_LSR_OE 0x02 /* Overrun error indicator */ |
71 | 80cabfad | bellard | #define UART_LSR_DR 0x01 /* Receiver data ready */ |
72 | 80cabfad | bellard | |
73 | b41a2cd1 | bellard | struct SerialState {
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74 | 80cabfad | bellard | uint8_t divider; |
75 | 80cabfad | bellard | uint8_t rbr; /* receive register */
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76 | 80cabfad | bellard | uint8_t ier; |
77 | 80cabfad | bellard | uint8_t iir; /* read only */
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78 | 80cabfad | bellard | uint8_t lcr; |
79 | 80cabfad | bellard | uint8_t mcr; |
80 | 80cabfad | bellard | uint8_t lsr; /* read only */
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81 | 80cabfad | bellard | uint8_t msr; |
82 | 80cabfad | bellard | uint8_t scr; |
83 | 80cabfad | bellard | /* NOTE: this hidden state is necessary for tx irq generation as
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84 | 80cabfad | bellard | it can be reset while reading iir */
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85 | 80cabfad | bellard | int thr_ipending;
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86 | 80cabfad | bellard | int irq;
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87 | b41a2cd1 | bellard | int out_fd;
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88 | b41a2cd1 | bellard | }; |
89 | 80cabfad | bellard | |
90 | b41a2cd1 | bellard | static void serial_update_irq(SerialState *s) |
91 | 80cabfad | bellard | { |
92 | 80cabfad | bellard | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
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93 | 80cabfad | bellard | s->iir = UART_IIR_RDI; |
94 | 80cabfad | bellard | } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) { |
95 | 80cabfad | bellard | s->iir = UART_IIR_THRI; |
96 | 80cabfad | bellard | } else {
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97 | 80cabfad | bellard | s->iir = UART_IIR_NO_INT; |
98 | 80cabfad | bellard | } |
99 | 80cabfad | bellard | if (s->iir != UART_IIR_NO_INT) {
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100 | 80cabfad | bellard | pic_set_irq(s->irq, 1);
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101 | 80cabfad | bellard | } else {
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102 | 80cabfad | bellard | pic_set_irq(s->irq, 0);
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103 | 80cabfad | bellard | } |
104 | 80cabfad | bellard | } |
105 | 80cabfad | bellard | |
106 | b41a2cd1 | bellard | static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
107 | 80cabfad | bellard | { |
108 | b41a2cd1 | bellard | SerialState *s = opaque; |
109 | 80cabfad | bellard | unsigned char ch; |
110 | 80cabfad | bellard | int ret;
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111 | 80cabfad | bellard | |
112 | 80cabfad | bellard | addr &= 7;
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113 | 80cabfad | bellard | #ifdef DEBUG_SERIAL
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114 | 80cabfad | bellard | printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
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115 | 80cabfad | bellard | #endif
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116 | 80cabfad | bellard | switch(addr) {
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117 | 80cabfad | bellard | default:
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118 | 80cabfad | bellard | case 0: |
119 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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120 | 80cabfad | bellard | s->divider = (s->divider & 0xff00) | val;
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121 | 80cabfad | bellard | } else {
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122 | 80cabfad | bellard | s->thr_ipending = 0;
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123 | 80cabfad | bellard | s->lsr &= ~UART_LSR_THRE; |
124 | b41a2cd1 | bellard | serial_update_irq(s); |
125 | 80cabfad | bellard | |
126 | 52302d72 | bellard | if (s->out_fd >= 0) { |
127 | 52302d72 | bellard | ch = val; |
128 | 52302d72 | bellard | do {
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129 | 52302d72 | bellard | ret = write(s->out_fd, &ch, 1);
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130 | 52302d72 | bellard | } while (ret != 1); |
131 | 52302d72 | bellard | } |
132 | 80cabfad | bellard | s->thr_ipending = 1;
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133 | 80cabfad | bellard | s->lsr |= UART_LSR_THRE; |
134 | 80cabfad | bellard | s->lsr |= UART_LSR_TEMT; |
135 | b41a2cd1 | bellard | serial_update_irq(s); |
136 | 80cabfad | bellard | } |
137 | 80cabfad | bellard | break;
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138 | 80cabfad | bellard | case 1: |
139 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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140 | 80cabfad | bellard | s->divider = (s->divider & 0x00ff) | (val << 8); |
141 | 80cabfad | bellard | } else {
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142 | 80cabfad | bellard | s->ier = val; |
143 | b41a2cd1 | bellard | serial_update_irq(s); |
144 | 80cabfad | bellard | } |
145 | 80cabfad | bellard | break;
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146 | 80cabfad | bellard | case 2: |
147 | 80cabfad | bellard | break;
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148 | 80cabfad | bellard | case 3: |
149 | 80cabfad | bellard | s->lcr = val; |
150 | 80cabfad | bellard | break;
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151 | 80cabfad | bellard | case 4: |
152 | 80cabfad | bellard | s->mcr = val; |
153 | 80cabfad | bellard | break;
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154 | 80cabfad | bellard | case 5: |
155 | 80cabfad | bellard | break;
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156 | 80cabfad | bellard | case 6: |
157 | 80cabfad | bellard | s->msr = val; |
158 | 80cabfad | bellard | break;
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159 | 80cabfad | bellard | case 7: |
160 | 80cabfad | bellard | s->scr = val; |
161 | 80cabfad | bellard | break;
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162 | 80cabfad | bellard | } |
163 | 80cabfad | bellard | } |
164 | 80cabfad | bellard | |
165 | b41a2cd1 | bellard | static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
166 | 80cabfad | bellard | { |
167 | b41a2cd1 | bellard | SerialState *s = opaque; |
168 | 80cabfad | bellard | uint32_t ret; |
169 | 80cabfad | bellard | |
170 | 80cabfad | bellard | addr &= 7;
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171 | 80cabfad | bellard | switch(addr) {
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172 | 80cabfad | bellard | default:
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173 | 80cabfad | bellard | case 0: |
174 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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175 | 80cabfad | bellard | ret = s->divider & 0xff;
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176 | 80cabfad | bellard | } else {
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177 | 80cabfad | bellard | ret = s->rbr; |
178 | 80cabfad | bellard | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
179 | b41a2cd1 | bellard | serial_update_irq(s); |
180 | 80cabfad | bellard | } |
181 | 80cabfad | bellard | break;
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182 | 80cabfad | bellard | case 1: |
183 | 80cabfad | bellard | if (s->lcr & UART_LCR_DLAB) {
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184 | 80cabfad | bellard | ret = (s->divider >> 8) & 0xff; |
185 | 80cabfad | bellard | } else {
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186 | 80cabfad | bellard | ret = s->ier; |
187 | 80cabfad | bellard | } |
188 | 80cabfad | bellard | break;
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189 | 80cabfad | bellard | case 2: |
190 | 80cabfad | bellard | ret = s->iir; |
191 | 80cabfad | bellard | /* reset THR pending bit */
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192 | 80cabfad | bellard | if ((ret & 0x7) == UART_IIR_THRI) |
193 | 80cabfad | bellard | s->thr_ipending = 0;
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194 | b41a2cd1 | bellard | serial_update_irq(s); |
195 | 80cabfad | bellard | break;
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196 | 80cabfad | bellard | case 3: |
197 | 80cabfad | bellard | ret = s->lcr; |
198 | 80cabfad | bellard | break;
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199 | 80cabfad | bellard | case 4: |
200 | 80cabfad | bellard | ret = s->mcr; |
201 | 80cabfad | bellard | break;
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202 | 80cabfad | bellard | case 5: |
203 | 80cabfad | bellard | ret = s->lsr; |
204 | 80cabfad | bellard | break;
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205 | 80cabfad | bellard | case 6: |
206 | 80cabfad | bellard | if (s->mcr & UART_MCR_LOOP) {
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207 | 80cabfad | bellard | /* in loopback, the modem output pins are connected to the
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208 | 80cabfad | bellard | inputs */
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209 | 80cabfad | bellard | ret = (s->mcr & 0x0c) << 4; |
210 | 80cabfad | bellard | ret |= (s->mcr & 0x02) << 3; |
211 | 80cabfad | bellard | ret |= (s->mcr & 0x01) << 5; |
212 | 80cabfad | bellard | } else {
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213 | 80cabfad | bellard | ret = s->msr; |
214 | 80cabfad | bellard | } |
215 | 80cabfad | bellard | break;
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216 | 80cabfad | bellard | case 7: |
217 | 80cabfad | bellard | ret = s->scr; |
218 | 80cabfad | bellard | break;
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219 | 80cabfad | bellard | } |
220 | 80cabfad | bellard | #ifdef DEBUG_SERIAL
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221 | 80cabfad | bellard | printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
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222 | 80cabfad | bellard | #endif
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223 | 80cabfad | bellard | return ret;
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224 | 80cabfad | bellard | } |
225 | 80cabfad | bellard | |
226 | b41a2cd1 | bellard | int serial_can_receive(SerialState *s)
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227 | 80cabfad | bellard | { |
228 | 80cabfad | bellard | return !(s->lsr & UART_LSR_DR);
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229 | 80cabfad | bellard | } |
230 | 80cabfad | bellard | |
231 | b41a2cd1 | bellard | void serial_receive_byte(SerialState *s, int ch) |
232 | 80cabfad | bellard | { |
233 | 80cabfad | bellard | s->rbr = ch; |
234 | 80cabfad | bellard | s->lsr |= UART_LSR_DR; |
235 | b41a2cd1 | bellard | serial_update_irq(s); |
236 | 80cabfad | bellard | } |
237 | 80cabfad | bellard | |
238 | b41a2cd1 | bellard | void serial_receive_break(SerialState *s)
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239 | 80cabfad | bellard | { |
240 | 80cabfad | bellard | s->rbr = 0;
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241 | 80cabfad | bellard | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
242 | b41a2cd1 | bellard | serial_update_irq(s); |
243 | 80cabfad | bellard | } |
244 | 80cabfad | bellard | |
245 | b41a2cd1 | bellard | static int serial_can_receive1(void *opaque) |
246 | 80cabfad | bellard | { |
247 | b41a2cd1 | bellard | SerialState *s = opaque; |
248 | b41a2cd1 | bellard | return serial_can_receive(s);
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249 | b41a2cd1 | bellard | } |
250 | b41a2cd1 | bellard | |
251 | b41a2cd1 | bellard | static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
252 | b41a2cd1 | bellard | { |
253 | b41a2cd1 | bellard | SerialState *s = opaque; |
254 | b41a2cd1 | bellard | serial_receive_byte(s, buf[0]);
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255 | b41a2cd1 | bellard | } |
256 | 80cabfad | bellard | |
257 | b41a2cd1 | bellard | /* If fd is zero, it means that the serial device uses the console */
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258 | b41a2cd1 | bellard | SerialState *serial_init(int base, int irq, int fd) |
259 | b41a2cd1 | bellard | { |
260 | b41a2cd1 | bellard | SerialState *s; |
261 | b41a2cd1 | bellard | |
262 | b41a2cd1 | bellard | s = qemu_mallocz(sizeof(SerialState));
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263 | b41a2cd1 | bellard | if (!s)
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264 | b41a2cd1 | bellard | return NULL; |
265 | 80cabfad | bellard | s->irq = irq; |
266 | 80cabfad | bellard | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
267 | 80cabfad | bellard | s->iir = UART_IIR_NO_INT; |
268 | b41a2cd1 | bellard | |
269 | b41a2cd1 | bellard | register_ioport_write(base, 8, 1, serial_ioport_write, s); |
270 | b41a2cd1 | bellard | register_ioport_read(base, 8, 1, serial_ioport_read, s); |
271 | b41a2cd1 | bellard | |
272 | 52302d72 | bellard | if (fd < 0) { |
273 | 52302d72 | bellard | /* no associated device */
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274 | 52302d72 | bellard | s->out_fd = -1;
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275 | 52302d72 | bellard | } else if (fd != 0) { |
276 | b0a21b53 | bellard | qemu_add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s); |
277 | b41a2cd1 | bellard | s->out_fd = fd; |
278 | b41a2cd1 | bellard | } else {
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279 | b41a2cd1 | bellard | serial_console = s; |
280 | b41a2cd1 | bellard | s->out_fd = 1;
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281 | b41a2cd1 | bellard | } |
282 | b41a2cd1 | bellard | return s;
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283 | 80cabfad | bellard | } |