root / target-lm32 / README @ b3ce604e
History | View | Annotate | Download (1.6 kB)
1 | 45664345 | Michael Walle | LatticeMico32 target |
---|---|---|---|
2 | 45664345 | Michael Walle | -------------------- |
3 | 45664345 | Michael Walle | |
4 | 45664345 | Michael Walle | General |
5 | 45664345 | Michael Walle | ------- |
6 | 45664345 | Michael Walle | All opcodes including the JUART CSRs are supported. |
7 | 45664345 | Michael Walle | |
8 | 45664345 | Michael Walle | |
9 | 45664345 | Michael Walle | JTAG UART |
10 | 45664345 | Michael Walle | --------- |
11 | 45664345 | Michael Walle | JTAG UART is routed to a serial console device. For the current boards it |
12 | 45664345 | Michael Walle | is the second one. Ie to enable it in the qemu virtual console window use |
13 | 45664345 | Michael Walle | the following command line parameters: |
14 | 45664345 | Michael Walle | -serial vc -serial vc |
15 | 45664345 | Michael Walle | This will make serial0 (the lm32_uart) and serial1 (the JTAG UART) |
16 | 45664345 | Michael Walle | available as virtual consoles. |
17 | 45664345 | Michael Walle | |
18 | 45664345 | Michael Walle | |
19 | 45664345 | Michael Walle | Programmatically terminate the emulator |
20 | 45664345 | Michael Walle | ---------------------------------------- |
21 | 45664345 | Michael Walle | Originally neither the LatticeMico32 nor its peripherals support a |
22 | 45664345 | Michael Walle | mechanism to shut down the machine. Emulation aware programs can write to a |
23 | 45664345 | Michael Walle | to a special register within the system control block to shut down the |
24 | 45664345 | Michael Walle | virtual machine. For more details see hw/lm32_sys.c. The lm32-evr is the |
25 | 45664345 | Michael Walle | first BSP which instantiate this model. A (32 bit) write to 0xfff0000 |
26 | 45664345 | Michael Walle | causes a vm shutdown. |
27 | 45664345 | Michael Walle | |
28 | 45664345 | Michael Walle | |
29 | 45664345 | Michael Walle | Special instructions |
30 | 45664345 | Michael Walle | -------------------- |
31 | 45664345 | Michael Walle | The translation recognizes one special instruction to halt the cpu: |
32 | 45664345 | Michael Walle | and r0, r0, r0 |
33 | 45664345 | Michael Walle | On real hardware this instruction is a nop. It is not used by GCC and |
34 | 45664345 | Michael Walle | should (hopefully) not be used within hand-crafted assembly. |
35 | 45664345 | Michael Walle | Insert this instruction in your idle loop to reduce the cpu load on the |
36 | 45664345 | Michael Walle | host. |
37 | 45664345 | Michael Walle | |
38 | 45664345 | Michael Walle | |
39 | 45664345 | Michael Walle | Ignoring the MSB of the address bus |
40 | 45664345 | Michael Walle | ----------------------------------- |
41 | 45664345 | Michael Walle | Some SoC ignores the MSB on the address bus. Thus creating a shadow memory |
42 | 45664345 | Michael Walle | area. As a general rule, 0x00000000-0x7fffffff is cached, whereas |
43 | 45664345 | Michael Walle | 0x80000000-0xffffffff is not cached and used to access IO devices. This |
44 | 45664345 | Michael Walle | behaviour can be enabled with: |
45 | 45664345 | Michael Walle | cpu_lm32_set_phys_msb_ignore(env, 1); |