root / hw / pl050.c @ b48d7d69
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1 | 5fafdf24 | ths | /*
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2 | 69db0ac7 | pbrook | * Arm PrimeCell PL050 Keyboard / Mouse Interface
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3 | cdbdb648 | pbrook | *
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4 | 9e61ec31 | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | cdbdb648 | pbrook | * Written by Paul Brook
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6 | cdbdb648 | pbrook | *
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7 | cdbdb648 | pbrook | * This code is licenced under the GPL.
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8 | cdbdb648 | pbrook | */
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9 | cdbdb648 | pbrook | |
10 | cdbdb648 | pbrook | #include "vl.h" |
11 | cdbdb648 | pbrook | |
12 | cdbdb648 | pbrook | typedef struct { |
13 | cdbdb648 | pbrook | void *dev;
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14 | cdbdb648 | pbrook | uint32_t base; |
15 | cdbdb648 | pbrook | uint32_t cr; |
16 | cdbdb648 | pbrook | uint32_t clk; |
17 | cdbdb648 | pbrook | uint32_t last; |
18 | cdbdb648 | pbrook | int pending;
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19 | d537cf6c | pbrook | qemu_irq irq; |
20 | cdbdb648 | pbrook | int is_mouse;
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21 | cdbdb648 | pbrook | } pl050_state; |
22 | cdbdb648 | pbrook | |
23 | 9e61ec31 | pbrook | #define PL050_TXEMPTY (1 << 6) |
24 | 9e61ec31 | pbrook | #define PL050_TXBUSY (1 << 5) |
25 | 9e61ec31 | pbrook | #define PL050_RXFULL (1 << 4) |
26 | 9e61ec31 | pbrook | #define PL050_RXBUSY (1 << 3) |
27 | 9e61ec31 | pbrook | #define PL050_RXPARITY (1 << 2) |
28 | 9e61ec31 | pbrook | #define PL050_KMIC (1 << 1) |
29 | 9e61ec31 | pbrook | #define PL050_KMID (1 << 0) |
30 | 9e61ec31 | pbrook | |
31 | cdbdb648 | pbrook | static const unsigned char pl050_id[] = |
32 | cdbdb648 | pbrook | { 0x50, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
33 | cdbdb648 | pbrook | |
34 | cdbdb648 | pbrook | static void pl050_update(void *opaque, int level) |
35 | cdbdb648 | pbrook | { |
36 | cdbdb648 | pbrook | pl050_state *s = (pl050_state *)opaque; |
37 | cdbdb648 | pbrook | int raise;
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38 | cdbdb648 | pbrook | |
39 | cdbdb648 | pbrook | s->pending = level; |
40 | cdbdb648 | pbrook | raise = (s->pending && (s->cr & 0x10) != 0) |
41 | cdbdb648 | pbrook | || (s->cr & 0x08) != 0; |
42 | d537cf6c | pbrook | qemu_set_irq(s->irq, raise); |
43 | cdbdb648 | pbrook | } |
44 | cdbdb648 | pbrook | |
45 | cdbdb648 | pbrook | static uint32_t pl050_read(void *opaque, target_phys_addr_t offset) |
46 | cdbdb648 | pbrook | { |
47 | cdbdb648 | pbrook | pl050_state *s = (pl050_state *)opaque; |
48 | cdbdb648 | pbrook | offset -= s->base; |
49 | cdbdb648 | pbrook | if (offset >= 0xfe0 && offset < 0x1000) |
50 | cdbdb648 | pbrook | return pl050_id[(offset - 0xfe0) >> 2]; |
51 | cdbdb648 | pbrook | |
52 | cdbdb648 | pbrook | switch (offset >> 2) { |
53 | cdbdb648 | pbrook | case 0: /* KMICR */ |
54 | cdbdb648 | pbrook | return s->cr;
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55 | cdbdb648 | pbrook | case 1: /* KMISTAT */ |
56 | 9e61ec31 | pbrook | { |
57 | 9e61ec31 | pbrook | uint8_t val; |
58 | 9e61ec31 | pbrook | uint32_t stat; |
59 | 9e61ec31 | pbrook | |
60 | 9e61ec31 | pbrook | val = s->last; |
61 | 9e61ec31 | pbrook | val = val ^ (val >> 4);
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62 | 9e61ec31 | pbrook | val = val ^ (val >> 2);
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63 | 9e61ec31 | pbrook | val = (val ^ (val >> 1)) & 1; |
64 | 9e61ec31 | pbrook | |
65 | 9e61ec31 | pbrook | stat = PL050_TXEMPTY; |
66 | 9e61ec31 | pbrook | if (val)
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67 | 9e61ec31 | pbrook | stat |= PL050_RXPARITY; |
68 | 9e61ec31 | pbrook | if (s->pending)
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69 | 9e61ec31 | pbrook | stat |= PL050_RXFULL; |
70 | 9e61ec31 | pbrook | |
71 | 9e61ec31 | pbrook | return stat;
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72 | cdbdb648 | pbrook | } |
73 | cdbdb648 | pbrook | case 2: /* KMIDATA */ |
74 | cdbdb648 | pbrook | if (s->pending)
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75 | cdbdb648 | pbrook | s->last = ps2_read_data(s->dev); |
76 | cdbdb648 | pbrook | return s->last;
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77 | cdbdb648 | pbrook | case 3: /* KMICLKDIV */ |
78 | cdbdb648 | pbrook | return s->clk;
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79 | cdbdb648 | pbrook | case 4: /* KMIIR */ |
80 | cdbdb648 | pbrook | return s->pending | 2; |
81 | cdbdb648 | pbrook | default:
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82 | cdbdb648 | pbrook | cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", offset);
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83 | cdbdb648 | pbrook | return 0; |
84 | cdbdb648 | pbrook | } |
85 | cdbdb648 | pbrook | } |
86 | cdbdb648 | pbrook | |
87 | cdbdb648 | pbrook | static void pl050_write(void *opaque, target_phys_addr_t offset, |
88 | cdbdb648 | pbrook | uint32_t value) |
89 | cdbdb648 | pbrook | { |
90 | cdbdb648 | pbrook | pl050_state *s = (pl050_state *)opaque; |
91 | cdbdb648 | pbrook | offset -= s->base; |
92 | cdbdb648 | pbrook | switch (offset >> 2) { |
93 | cdbdb648 | pbrook | case 0: /* KMICR */ |
94 | cdbdb648 | pbrook | s->cr = value; |
95 | cdbdb648 | pbrook | pl050_update(s, s->pending); |
96 | cdbdb648 | pbrook | /* ??? Need to implement the enable/disable bit. */
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97 | cdbdb648 | pbrook | break;
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98 | cdbdb648 | pbrook | case 2: /* KMIDATA */ |
99 | cdbdb648 | pbrook | /* ??? This should toggle the TX interrupt line. */
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100 | cdbdb648 | pbrook | /* ??? This means kbd/mouse can block each other. */
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101 | cdbdb648 | pbrook | if (s->is_mouse) {
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102 | cdbdb648 | pbrook | ps2_write_mouse(s->dev, value); |
103 | cdbdb648 | pbrook | } else {
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104 | cdbdb648 | pbrook | ps2_write_keyboard(s->dev, value); |
105 | cdbdb648 | pbrook | } |
106 | cdbdb648 | pbrook | break;
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107 | cdbdb648 | pbrook | case 3: /* KMICLKDIV */ |
108 | cdbdb648 | pbrook | s->clk = value; |
109 | cdbdb648 | pbrook | return;
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110 | cdbdb648 | pbrook | default:
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111 | cdbdb648 | pbrook | cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", offset);
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112 | cdbdb648 | pbrook | } |
113 | cdbdb648 | pbrook | } |
114 | cdbdb648 | pbrook | static CPUReadMemoryFunc *pl050_readfn[] = {
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115 | cdbdb648 | pbrook | pl050_read, |
116 | cdbdb648 | pbrook | pl050_read, |
117 | cdbdb648 | pbrook | pl050_read |
118 | cdbdb648 | pbrook | }; |
119 | cdbdb648 | pbrook | |
120 | cdbdb648 | pbrook | static CPUWriteMemoryFunc *pl050_writefn[] = {
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121 | cdbdb648 | pbrook | pl050_write, |
122 | cdbdb648 | pbrook | pl050_write, |
123 | cdbdb648 | pbrook | pl050_write |
124 | cdbdb648 | pbrook | }; |
125 | cdbdb648 | pbrook | |
126 | d537cf6c | pbrook | void pl050_init(uint32_t base, qemu_irq irq, int is_mouse) |
127 | cdbdb648 | pbrook | { |
128 | cdbdb648 | pbrook | int iomemtype;
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129 | cdbdb648 | pbrook | pl050_state *s; |
130 | cdbdb648 | pbrook | |
131 | cdbdb648 | pbrook | s = (pl050_state *)qemu_mallocz(sizeof(pl050_state));
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132 | cdbdb648 | pbrook | iomemtype = cpu_register_io_memory(0, pl050_readfn,
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133 | cdbdb648 | pbrook | pl050_writefn, s); |
134 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00001000, iomemtype);
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135 | cdbdb648 | pbrook | s->base = base; |
136 | cdbdb648 | pbrook | s->irq = irq; |
137 | cdbdb648 | pbrook | s->is_mouse = is_mouse; |
138 | cdbdb648 | pbrook | if (is_mouse)
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139 | cdbdb648 | pbrook | s->dev = ps2_mouse_init(pl050_update, s); |
140 | cdbdb648 | pbrook | else
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141 | cdbdb648 | pbrook | s->dev = ps2_kbd_init(pl050_update, s); |
142 | cdbdb648 | pbrook | /* ??? Save/restore. */
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143 | cdbdb648 | pbrook | } |