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1 | 008ff9d7 | j_mayer | /*
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2 | 008ff9d7 | j_mayer | * QEMU PowerPC 4xx embedded processors shared devices emulation
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3 | 008ff9d7 | j_mayer | *
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4 | 008ff9d7 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 008ff9d7 | j_mayer | *
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6 | 008ff9d7 | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 008ff9d7 | j_mayer | * of this software and associated documentation files (the "Software"), to deal
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8 | 008ff9d7 | j_mayer | * in the Software without restriction, including without limitation the rights
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9 | 008ff9d7 | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 008ff9d7 | j_mayer | * copies of the Software, and to permit persons to whom the Software is
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11 | 008ff9d7 | j_mayer | * furnished to do so, subject to the following conditions:
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12 | 008ff9d7 | j_mayer | *
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13 | 008ff9d7 | j_mayer | * The above copyright notice and this permission notice shall be included in
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14 | 008ff9d7 | j_mayer | * all copies or substantial portions of the Software.
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15 | 008ff9d7 | j_mayer | *
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16 | 008ff9d7 | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 008ff9d7 | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 008ff9d7 | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 008ff9d7 | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 008ff9d7 | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 008ff9d7 | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 008ff9d7 | j_mayer | * THE SOFTWARE.
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23 | 008ff9d7 | j_mayer | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc.h" |
26 | 008ff9d7 | j_mayer | #include "ppc4xx.h" |
27 | 87ecb68b | pbrook | #include "sysemu.h" |
28 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
29 | 008ff9d7 | j_mayer | |
30 | 008ff9d7 | j_mayer | //#define DEBUG_MMIO
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31 | aae9366a | j_mayer | //#define DEBUG_UNASSIGNED
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32 | 008ff9d7 | j_mayer | #define DEBUG_UIC
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33 | 008ff9d7 | j_mayer | |
34 | d12d51d5 | aliguori | |
35 | d12d51d5 | aliguori | #ifdef DEBUG_UIC
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36 | 93fcfe39 | aliguori | # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
37 | d12d51d5 | aliguori | #else
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38 | d12d51d5 | aliguori | # define LOG_UIC(...) do { } while (0) |
39 | d12d51d5 | aliguori | #endif
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40 | d12d51d5 | aliguori | |
41 | 008ff9d7 | j_mayer | /*****************************************************************************/
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42 | 008ff9d7 | j_mayer | /* Generic PowerPC 4xx processor instanciation */
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43 | b55266b5 | blueswir1 | CPUState *ppc4xx_init (const char *cpu_model, |
44 | c227f099 | Anthony Liguori | clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
45 | 008ff9d7 | j_mayer | uint32_t sysclk) |
46 | 008ff9d7 | j_mayer | { |
47 | 008ff9d7 | j_mayer | CPUState *env; |
48 | 008ff9d7 | j_mayer | |
49 | 008ff9d7 | j_mayer | /* init CPUs */
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50 | aaed909a | bellard | env = cpu_init(cpu_model); |
51 | aaed909a | bellard | if (!env) {
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52 | aaed909a | bellard | fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
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53 | aaed909a | bellard | cpu_model); |
54 | aaed909a | bellard | exit(1);
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55 | 008ff9d7 | j_mayer | } |
56 | 008ff9d7 | j_mayer | cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ |
57 | 008ff9d7 | j_mayer | cpu_clk->opaque = env; |
58 | 008ff9d7 | j_mayer | /* Set time-base frequency to sysclk */
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59 | 008ff9d7 | j_mayer | tb_clk->cb = ppc_emb_timers_init(env, sysclk); |
60 | 008ff9d7 | j_mayer | tb_clk->opaque = env; |
61 | 008ff9d7 | j_mayer | ppc_dcr_init(env, NULL, NULL); |
62 | 008ff9d7 | j_mayer | /* Register qemu callbacks */
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63 | d84bda46 | Blue Swirl | qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); |
64 | 008ff9d7 | j_mayer | |
65 | 008ff9d7 | j_mayer | return env;
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66 | 008ff9d7 | j_mayer | } |
67 | 008ff9d7 | j_mayer | |
68 | 008ff9d7 | j_mayer | /*****************************************************************************/
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69 | 008ff9d7 | j_mayer | /* "Universal" Interrupt controller */
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70 | 008ff9d7 | j_mayer | enum {
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71 | 008ff9d7 | j_mayer | DCR_UICSR = 0x000,
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72 | 008ff9d7 | j_mayer | DCR_UICSRS = 0x001,
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73 | 008ff9d7 | j_mayer | DCR_UICER = 0x002,
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74 | 008ff9d7 | j_mayer | DCR_UICCR = 0x003,
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75 | 008ff9d7 | j_mayer | DCR_UICPR = 0x004,
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76 | 008ff9d7 | j_mayer | DCR_UICTR = 0x005,
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77 | 008ff9d7 | j_mayer | DCR_UICMSR = 0x006,
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78 | 008ff9d7 | j_mayer | DCR_UICVR = 0x007,
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79 | 008ff9d7 | j_mayer | DCR_UICVCR = 0x008,
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80 | 008ff9d7 | j_mayer | DCR_UICMAX = 0x009,
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81 | 008ff9d7 | j_mayer | }; |
82 | 008ff9d7 | j_mayer | |
83 | 008ff9d7 | j_mayer | #define UIC_MAX_IRQ 32 |
84 | c227f099 | Anthony Liguori | typedef struct ppcuic_t ppcuic_t; |
85 | c227f099 | Anthony Liguori | struct ppcuic_t {
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86 | 008ff9d7 | j_mayer | uint32_t dcr_base; |
87 | 008ff9d7 | j_mayer | int use_vectors;
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88 | 4c54e875 | aurel32 | uint32_t level; /* Remembers the state of level-triggered interrupts. */
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89 | 008ff9d7 | j_mayer | uint32_t uicsr; /* Status register */
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90 | 008ff9d7 | j_mayer | uint32_t uicer; /* Enable register */
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91 | 008ff9d7 | j_mayer | uint32_t uiccr; /* Critical register */
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92 | 008ff9d7 | j_mayer | uint32_t uicpr; /* Polarity register */
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93 | 008ff9d7 | j_mayer | uint32_t uictr; /* Triggering register */
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94 | 008ff9d7 | j_mayer | uint32_t uicvcr; /* Vector configuration register */
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95 | 008ff9d7 | j_mayer | uint32_t uicvr; |
96 | 008ff9d7 | j_mayer | qemu_irq *irqs; |
97 | 008ff9d7 | j_mayer | }; |
98 | 008ff9d7 | j_mayer | |
99 | c227f099 | Anthony Liguori | static void ppcuic_trigger_irq (ppcuic_t *uic) |
100 | 008ff9d7 | j_mayer | { |
101 | 008ff9d7 | j_mayer | uint32_t ir, cr; |
102 | 008ff9d7 | j_mayer | int start, end, inc, i;
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103 | 008ff9d7 | j_mayer | |
104 | 008ff9d7 | j_mayer | /* Trigger interrupt if any is pending */
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105 | 008ff9d7 | j_mayer | ir = uic->uicsr & uic->uicer & (~uic->uiccr); |
106 | 008ff9d7 | j_mayer | cr = uic->uicsr & uic->uicer & uic->uiccr; |
107 | d12d51d5 | aliguori | LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32 |
108 | aae9366a | j_mayer | " uiccr %08" PRIx32 "\n" |
109 | aae9366a | j_mayer | " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", |
110 | aae9366a | j_mayer | __func__, uic->uicsr, uic->uicer, uic->uiccr, |
111 | 008ff9d7 | j_mayer | uic->uicsr & uic->uicer, ir, cr); |
112 | 008ff9d7 | j_mayer | if (ir != 0x0000000) { |
113 | d12d51d5 | aliguori | LOG_UIC("Raise UIC interrupt\n");
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114 | 008ff9d7 | j_mayer | qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); |
115 | 008ff9d7 | j_mayer | } else {
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116 | d12d51d5 | aliguori | LOG_UIC("Lower UIC interrupt\n");
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117 | 008ff9d7 | j_mayer | qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); |
118 | 008ff9d7 | j_mayer | } |
119 | 008ff9d7 | j_mayer | /* Trigger critical interrupt if any is pending and update vector */
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120 | 008ff9d7 | j_mayer | if (cr != 0x0000000) { |
121 | 008ff9d7 | j_mayer | qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); |
122 | 008ff9d7 | j_mayer | if (uic->use_vectors) {
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123 | 008ff9d7 | j_mayer | /* Compute critical IRQ vector */
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124 | 008ff9d7 | j_mayer | if (uic->uicvcr & 1) { |
125 | 008ff9d7 | j_mayer | start = 31;
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126 | 008ff9d7 | j_mayer | end = 0;
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127 | 008ff9d7 | j_mayer | inc = -1;
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128 | 008ff9d7 | j_mayer | } else {
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129 | 008ff9d7 | j_mayer | start = 0;
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130 | 008ff9d7 | j_mayer | end = 31;
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131 | 008ff9d7 | j_mayer | inc = 1;
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132 | 008ff9d7 | j_mayer | } |
133 | 008ff9d7 | j_mayer | uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
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134 | 008ff9d7 | j_mayer | for (i = start; i <= end; i += inc) {
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135 | 008ff9d7 | j_mayer | if (cr & (1 << i)) { |
136 | 008ff9d7 | j_mayer | uic->uicvr += (i - start) * 512 * inc;
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137 | 008ff9d7 | j_mayer | break;
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138 | 008ff9d7 | j_mayer | } |
139 | 008ff9d7 | j_mayer | } |
140 | 008ff9d7 | j_mayer | } |
141 | d12d51d5 | aliguori | LOG_UIC("Raise UIC critical interrupt - "
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142 | aae9366a | j_mayer | "vector %08" PRIx32 "\n", uic->uicvr); |
143 | 008ff9d7 | j_mayer | } else {
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144 | d12d51d5 | aliguori | LOG_UIC("Lower UIC critical interrupt\n");
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145 | 008ff9d7 | j_mayer | qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); |
146 | 008ff9d7 | j_mayer | uic->uicvr = 0x00000000;
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147 | 008ff9d7 | j_mayer | } |
148 | 008ff9d7 | j_mayer | } |
149 | 008ff9d7 | j_mayer | |
150 | 008ff9d7 | j_mayer | static void ppcuic_set_irq (void *opaque, int irq_num, int level) |
151 | 008ff9d7 | j_mayer | { |
152 | c227f099 | Anthony Liguori | ppcuic_t *uic; |
153 | 008ff9d7 | j_mayer | uint32_t mask, sr; |
154 | 008ff9d7 | j_mayer | |
155 | 008ff9d7 | j_mayer | uic = opaque; |
156 | 923e5e33 | aurel32 | mask = 1 << (31-irq_num); |
157 | d12d51d5 | aliguori | LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
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158 | aae9366a | j_mayer | " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", |
159 | aae9366a | j_mayer | __func__, irq_num, level, |
160 | 008ff9d7 | j_mayer | uic->uicsr, mask, uic->uicsr & mask, level << irq_num); |
161 | 008ff9d7 | j_mayer | if (irq_num < 0 || irq_num > 31) |
162 | 008ff9d7 | j_mayer | return;
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163 | 008ff9d7 | j_mayer | sr = uic->uicsr; |
164 | 50bf72b3 | aurel32 | |
165 | 008ff9d7 | j_mayer | /* Update status register */
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166 | 008ff9d7 | j_mayer | if (uic->uictr & mask) {
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167 | 008ff9d7 | j_mayer | /* Edge sensitive interrupt */
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168 | 008ff9d7 | j_mayer | if (level == 1) |
169 | 008ff9d7 | j_mayer | uic->uicsr |= mask; |
170 | 008ff9d7 | j_mayer | } else {
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171 | 008ff9d7 | j_mayer | /* Level sensitive interrupt */
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172 | 4c54e875 | aurel32 | if (level == 1) { |
173 | 008ff9d7 | j_mayer | uic->uicsr |= mask; |
174 | 4c54e875 | aurel32 | uic->level |= mask; |
175 | 4c54e875 | aurel32 | } else {
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176 | 008ff9d7 | j_mayer | uic->uicsr &= ~mask; |
177 | 4c54e875 | aurel32 | uic->level &= ~mask; |
178 | 4c54e875 | aurel32 | } |
179 | 008ff9d7 | j_mayer | } |
180 | d12d51d5 | aliguori | LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => " |
181 | aae9366a | j_mayer | "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); |
182 | 008ff9d7 | j_mayer | if (sr != uic->uicsr)
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183 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
184 | 008ff9d7 | j_mayer | } |
185 | 008ff9d7 | j_mayer | |
186 | 008ff9d7 | j_mayer | static target_ulong dcr_read_uic (void *opaque, int dcrn) |
187 | 008ff9d7 | j_mayer | { |
188 | c227f099 | Anthony Liguori | ppcuic_t *uic; |
189 | 008ff9d7 | j_mayer | target_ulong ret; |
190 | 008ff9d7 | j_mayer | |
191 | 008ff9d7 | j_mayer | uic = opaque; |
192 | 008ff9d7 | j_mayer | dcrn -= uic->dcr_base; |
193 | 008ff9d7 | j_mayer | switch (dcrn) {
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194 | 008ff9d7 | j_mayer | case DCR_UICSR:
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195 | 008ff9d7 | j_mayer | case DCR_UICSRS:
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196 | 008ff9d7 | j_mayer | ret = uic->uicsr; |
197 | 008ff9d7 | j_mayer | break;
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198 | 008ff9d7 | j_mayer | case DCR_UICER:
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199 | 008ff9d7 | j_mayer | ret = uic->uicer; |
200 | 008ff9d7 | j_mayer | break;
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201 | 008ff9d7 | j_mayer | case DCR_UICCR:
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202 | 008ff9d7 | j_mayer | ret = uic->uiccr; |
203 | 008ff9d7 | j_mayer | break;
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204 | 008ff9d7 | j_mayer | case DCR_UICPR:
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205 | 008ff9d7 | j_mayer | ret = uic->uicpr; |
206 | 008ff9d7 | j_mayer | break;
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207 | 008ff9d7 | j_mayer | case DCR_UICTR:
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208 | 008ff9d7 | j_mayer | ret = uic->uictr; |
209 | 008ff9d7 | j_mayer | break;
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210 | 008ff9d7 | j_mayer | case DCR_UICMSR:
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211 | 008ff9d7 | j_mayer | ret = uic->uicsr & uic->uicer; |
212 | 008ff9d7 | j_mayer | break;
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213 | 008ff9d7 | j_mayer | case DCR_UICVR:
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214 | 008ff9d7 | j_mayer | if (!uic->use_vectors)
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215 | 008ff9d7 | j_mayer | goto no_read;
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216 | 008ff9d7 | j_mayer | ret = uic->uicvr; |
217 | 008ff9d7 | j_mayer | break;
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218 | 008ff9d7 | j_mayer | case DCR_UICVCR:
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219 | 008ff9d7 | j_mayer | if (!uic->use_vectors)
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220 | 008ff9d7 | j_mayer | goto no_read;
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221 | 008ff9d7 | j_mayer | ret = uic->uicvcr; |
222 | 008ff9d7 | j_mayer | break;
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223 | 008ff9d7 | j_mayer | default:
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224 | 008ff9d7 | j_mayer | no_read:
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225 | 008ff9d7 | j_mayer | ret = 0x00000000;
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226 | 008ff9d7 | j_mayer | break;
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227 | 008ff9d7 | j_mayer | } |
228 | 008ff9d7 | j_mayer | |
229 | 008ff9d7 | j_mayer | return ret;
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230 | 008ff9d7 | j_mayer | } |
231 | 008ff9d7 | j_mayer | |
232 | 008ff9d7 | j_mayer | static void dcr_write_uic (void *opaque, int dcrn, target_ulong val) |
233 | 008ff9d7 | j_mayer | { |
234 | c227f099 | Anthony Liguori | ppcuic_t *uic; |
235 | 008ff9d7 | j_mayer | |
236 | 008ff9d7 | j_mayer | uic = opaque; |
237 | 008ff9d7 | j_mayer | dcrn -= uic->dcr_base; |
238 | 90e189ec | Blue Swirl | LOG_UIC("%s: dcr %d val " TARGET_FMT_lx "\n", __func__, dcrn, val); |
239 | 008ff9d7 | j_mayer | switch (dcrn) {
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240 | 008ff9d7 | j_mayer | case DCR_UICSR:
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241 | 008ff9d7 | j_mayer | uic->uicsr &= ~val; |
242 | 4c54e875 | aurel32 | uic->uicsr |= uic->level; |
243 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
244 | 008ff9d7 | j_mayer | break;
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245 | 008ff9d7 | j_mayer | case DCR_UICSRS:
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246 | 008ff9d7 | j_mayer | uic->uicsr |= val; |
247 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
248 | 008ff9d7 | j_mayer | break;
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249 | 008ff9d7 | j_mayer | case DCR_UICER:
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250 | 008ff9d7 | j_mayer | uic->uicer = val; |
251 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
252 | 008ff9d7 | j_mayer | break;
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253 | 008ff9d7 | j_mayer | case DCR_UICCR:
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254 | 008ff9d7 | j_mayer | uic->uiccr = val; |
255 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
256 | 008ff9d7 | j_mayer | break;
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257 | 008ff9d7 | j_mayer | case DCR_UICPR:
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258 | 008ff9d7 | j_mayer | uic->uicpr = val; |
259 | 008ff9d7 | j_mayer | break;
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260 | 008ff9d7 | j_mayer | case DCR_UICTR:
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261 | 008ff9d7 | j_mayer | uic->uictr = val; |
262 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
263 | 008ff9d7 | j_mayer | break;
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264 | 008ff9d7 | j_mayer | case DCR_UICMSR:
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265 | 008ff9d7 | j_mayer | break;
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266 | 008ff9d7 | j_mayer | case DCR_UICVR:
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267 | 008ff9d7 | j_mayer | break;
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268 | 008ff9d7 | j_mayer | case DCR_UICVCR:
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269 | 008ff9d7 | j_mayer | uic->uicvcr = val & 0xFFFFFFFD;
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270 | 008ff9d7 | j_mayer | ppcuic_trigger_irq(uic); |
271 | 008ff9d7 | j_mayer | break;
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272 | 008ff9d7 | j_mayer | } |
273 | 008ff9d7 | j_mayer | } |
274 | 008ff9d7 | j_mayer | |
275 | 008ff9d7 | j_mayer | static void ppcuic_reset (void *opaque) |
276 | 008ff9d7 | j_mayer | { |
277 | c227f099 | Anthony Liguori | ppcuic_t *uic; |
278 | 008ff9d7 | j_mayer | |
279 | 008ff9d7 | j_mayer | uic = opaque; |
280 | 008ff9d7 | j_mayer | uic->uiccr = 0x00000000;
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281 | 008ff9d7 | j_mayer | uic->uicer = 0x00000000;
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282 | 008ff9d7 | j_mayer | uic->uicpr = 0x00000000;
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283 | 008ff9d7 | j_mayer | uic->uicsr = 0x00000000;
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284 | 008ff9d7 | j_mayer | uic->uictr = 0x00000000;
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285 | 008ff9d7 | j_mayer | if (uic->use_vectors) {
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286 | 008ff9d7 | j_mayer | uic->uicvcr = 0x00000000;
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287 | 008ff9d7 | j_mayer | uic->uicvr = 0x0000000;
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288 | 008ff9d7 | j_mayer | } |
289 | 008ff9d7 | j_mayer | } |
290 | 008ff9d7 | j_mayer | |
291 | 008ff9d7 | j_mayer | qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, |
292 | 008ff9d7 | j_mayer | uint32_t dcr_base, int has_ssr, int has_vr) |
293 | 008ff9d7 | j_mayer | { |
294 | c227f099 | Anthony Liguori | ppcuic_t *uic; |
295 | 008ff9d7 | j_mayer | int i;
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296 | 008ff9d7 | j_mayer | |
297 | c227f099 | Anthony Liguori | uic = qemu_mallocz(sizeof(ppcuic_t));
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298 | 487414f1 | aliguori | uic->dcr_base = dcr_base; |
299 | 487414f1 | aliguori | uic->irqs = irqs; |
300 | 487414f1 | aliguori | if (has_vr)
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301 | 487414f1 | aliguori | uic->use_vectors = 1;
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302 | 487414f1 | aliguori | for (i = 0; i < DCR_UICMAX; i++) { |
303 | 487414f1 | aliguori | ppc_dcr_register(env, dcr_base + i, uic, |
304 | 487414f1 | aliguori | &dcr_read_uic, &dcr_write_uic); |
305 | 008ff9d7 | j_mayer | } |
306 | a08d4367 | Jan Kiszka | qemu_register_reset(ppcuic_reset, uic); |
307 | 008ff9d7 | j_mayer | |
308 | 008ff9d7 | j_mayer | return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
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309 | 008ff9d7 | j_mayer | } |
310 | 61b24405 | aurel32 | |
311 | 61b24405 | aurel32 | /*****************************************************************************/
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312 | 61b24405 | aurel32 | /* SDRAM controller */
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313 | c227f099 | Anthony Liguori | typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; |
314 | c227f099 | Anthony Liguori | struct ppc4xx_sdram_t {
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315 | 61b24405 | aurel32 | uint32_t addr; |
316 | 61b24405 | aurel32 | int nbanks;
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317 | c227f099 | Anthony Liguori | target_phys_addr_t ram_bases[4];
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318 | c227f099 | Anthony Liguori | target_phys_addr_t ram_sizes[4];
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319 | 61b24405 | aurel32 | uint32_t besr0; |
320 | 61b24405 | aurel32 | uint32_t besr1; |
321 | 61b24405 | aurel32 | uint32_t bear; |
322 | 61b24405 | aurel32 | uint32_t cfg; |
323 | 61b24405 | aurel32 | uint32_t status; |
324 | 61b24405 | aurel32 | uint32_t rtr; |
325 | 61b24405 | aurel32 | uint32_t pmit; |
326 | 61b24405 | aurel32 | uint32_t bcr[4];
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327 | 61b24405 | aurel32 | uint32_t tr; |
328 | 61b24405 | aurel32 | uint32_t ecccfg; |
329 | 61b24405 | aurel32 | uint32_t eccesr; |
330 | 61b24405 | aurel32 | qemu_irq irq; |
331 | 61b24405 | aurel32 | }; |
332 | 61b24405 | aurel32 | |
333 | 61b24405 | aurel32 | enum {
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334 | 61b24405 | aurel32 | SDRAM0_CFGADDR = 0x010,
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335 | 61b24405 | aurel32 | SDRAM0_CFGDATA = 0x011,
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336 | 61b24405 | aurel32 | }; |
337 | 61b24405 | aurel32 | |
338 | 61b24405 | aurel32 | /* XXX: TOFIX: some patches have made this code become inconsistent:
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339 | c227f099 | Anthony Liguori | * there are type inconsistencies, mixing target_phys_addr_t, target_ulong
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340 | 61b24405 | aurel32 | * and uint32_t
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341 | 61b24405 | aurel32 | */
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342 | c227f099 | Anthony Liguori | static uint32_t sdram_bcr (target_phys_addr_t ram_base,
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343 | c227f099 | Anthony Liguori | target_phys_addr_t ram_size) |
344 | 61b24405 | aurel32 | { |
345 | 61b24405 | aurel32 | uint32_t bcr; |
346 | 61b24405 | aurel32 | |
347 | 61b24405 | aurel32 | switch (ram_size) {
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348 | 61b24405 | aurel32 | case (4 * 1024 * 1024): |
349 | 61b24405 | aurel32 | bcr = 0x00000000;
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350 | 61b24405 | aurel32 | break;
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351 | 61b24405 | aurel32 | case (8 * 1024 * 1024): |
352 | 61b24405 | aurel32 | bcr = 0x00020000;
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353 | 61b24405 | aurel32 | break;
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354 | 61b24405 | aurel32 | case (16 * 1024 * 1024): |
355 | 61b24405 | aurel32 | bcr = 0x00040000;
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356 | 61b24405 | aurel32 | break;
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357 | 61b24405 | aurel32 | case (32 * 1024 * 1024): |
358 | 61b24405 | aurel32 | bcr = 0x00060000;
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359 | 61b24405 | aurel32 | break;
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360 | 61b24405 | aurel32 | case (64 * 1024 * 1024): |
361 | 61b24405 | aurel32 | bcr = 0x00080000;
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362 | 61b24405 | aurel32 | break;
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363 | 61b24405 | aurel32 | case (128 * 1024 * 1024): |
364 | 61b24405 | aurel32 | bcr = 0x000A0000;
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365 | 61b24405 | aurel32 | break;
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366 | 61b24405 | aurel32 | case (256 * 1024 * 1024): |
367 | 61b24405 | aurel32 | bcr = 0x000C0000;
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368 | 61b24405 | aurel32 | break;
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369 | 61b24405 | aurel32 | default:
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370 | 90e189ec | Blue Swirl | printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__, |
371 | 90e189ec | Blue Swirl | ram_size); |
372 | 61b24405 | aurel32 | return 0x00000000; |
373 | 61b24405 | aurel32 | } |
374 | 61b24405 | aurel32 | bcr |= ram_base & 0xFF800000;
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375 | 61b24405 | aurel32 | bcr |= 1;
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376 | 61b24405 | aurel32 | |
377 | 61b24405 | aurel32 | return bcr;
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378 | 61b24405 | aurel32 | } |
379 | 61b24405 | aurel32 | |
380 | c227f099 | Anthony Liguori | static inline target_phys_addr_t sdram_base(uint32_t bcr) |
381 | 61b24405 | aurel32 | { |
382 | 61b24405 | aurel32 | return bcr & 0xFF800000; |
383 | 61b24405 | aurel32 | } |
384 | 61b24405 | aurel32 | |
385 | 61b24405 | aurel32 | static target_ulong sdram_size (uint32_t bcr)
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386 | 61b24405 | aurel32 | { |
387 | 61b24405 | aurel32 | target_ulong size; |
388 | 61b24405 | aurel32 | int sh;
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389 | 61b24405 | aurel32 | |
390 | 61b24405 | aurel32 | sh = (bcr >> 17) & 0x7; |
391 | 61b24405 | aurel32 | if (sh == 7) |
392 | 61b24405 | aurel32 | size = -1;
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393 | 61b24405 | aurel32 | else
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394 | 61b24405 | aurel32 | size = (4 * 1024 * 1024) << sh; |
395 | 61b24405 | aurel32 | |
396 | 61b24405 | aurel32 | return size;
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397 | 61b24405 | aurel32 | } |
398 | 61b24405 | aurel32 | |
399 | 61b24405 | aurel32 | static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) |
400 | 61b24405 | aurel32 | { |
401 | 61b24405 | aurel32 | if (*bcrp & 0x00000001) { |
402 | 61b24405 | aurel32 | /* Unmap RAM */
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403 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
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404 | 90e189ec | Blue Swirl | printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
405 | 61b24405 | aurel32 | __func__, sdram_base(*bcrp), sdram_size(*bcrp)); |
406 | 61b24405 | aurel32 | #endif
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407 | 61b24405 | aurel32 | cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp), |
408 | 61b24405 | aurel32 | IO_MEM_UNASSIGNED); |
409 | 61b24405 | aurel32 | } |
410 | 61b24405 | aurel32 | *bcrp = bcr & 0xFFDEE001;
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411 | 61b24405 | aurel32 | if (enabled && (bcr & 0x00000001)) { |
412 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
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413 | 90e189ec | Blue Swirl | printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
414 | 61b24405 | aurel32 | __func__, sdram_base(bcr), sdram_size(bcr)); |
415 | 61b24405 | aurel32 | #endif
|
416 | 61b24405 | aurel32 | cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), |
417 | 61b24405 | aurel32 | sdram_base(bcr) | IO_MEM_RAM); |
418 | 61b24405 | aurel32 | } |
419 | 61b24405 | aurel32 | } |
420 | 61b24405 | aurel32 | |
421 | c227f099 | Anthony Liguori | static void sdram_map_bcr (ppc4xx_sdram_t *sdram) |
422 | 61b24405 | aurel32 | { |
423 | 61b24405 | aurel32 | int i;
|
424 | 61b24405 | aurel32 | |
425 | 61b24405 | aurel32 | for (i = 0; i < sdram->nbanks; i++) { |
426 | 61b24405 | aurel32 | if (sdram->ram_sizes[i] != 0) { |
427 | 61b24405 | aurel32 | sdram_set_bcr(&sdram->bcr[i], |
428 | 61b24405 | aurel32 | sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), |
429 | 61b24405 | aurel32 | 1);
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430 | 61b24405 | aurel32 | } else {
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431 | 61b24405 | aurel32 | sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0); |
432 | 61b24405 | aurel32 | } |
433 | 61b24405 | aurel32 | } |
434 | 61b24405 | aurel32 | } |
435 | 61b24405 | aurel32 | |
436 | c227f099 | Anthony Liguori | static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) |
437 | 61b24405 | aurel32 | { |
438 | 61b24405 | aurel32 | int i;
|
439 | 61b24405 | aurel32 | |
440 | 61b24405 | aurel32 | for (i = 0; i < sdram->nbanks; i++) { |
441 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
442 | 90e189ec | Blue Swirl | printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
443 | 61b24405 | aurel32 | __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); |
444 | 61b24405 | aurel32 | #endif
|
445 | 61b24405 | aurel32 | cpu_register_physical_memory(sdram_base(sdram->bcr[i]), |
446 | 61b24405 | aurel32 | sdram_size(sdram->bcr[i]), |
447 | 61b24405 | aurel32 | IO_MEM_UNASSIGNED); |
448 | 61b24405 | aurel32 | } |
449 | 61b24405 | aurel32 | } |
450 | 61b24405 | aurel32 | |
451 | 61b24405 | aurel32 | static target_ulong dcr_read_sdram (void *opaque, int dcrn) |
452 | 61b24405 | aurel32 | { |
453 | c227f099 | Anthony Liguori | ppc4xx_sdram_t *sdram; |
454 | 61b24405 | aurel32 | target_ulong ret; |
455 | 61b24405 | aurel32 | |
456 | 61b24405 | aurel32 | sdram = opaque; |
457 | 61b24405 | aurel32 | switch (dcrn) {
|
458 | 61b24405 | aurel32 | case SDRAM0_CFGADDR:
|
459 | 61b24405 | aurel32 | ret = sdram->addr; |
460 | 61b24405 | aurel32 | break;
|
461 | 61b24405 | aurel32 | case SDRAM0_CFGDATA:
|
462 | 61b24405 | aurel32 | switch (sdram->addr) {
|
463 | 61b24405 | aurel32 | case 0x00: /* SDRAM_BESR0 */ |
464 | 61b24405 | aurel32 | ret = sdram->besr0; |
465 | 61b24405 | aurel32 | break;
|
466 | 61b24405 | aurel32 | case 0x08: /* SDRAM_BESR1 */ |
467 | 61b24405 | aurel32 | ret = sdram->besr1; |
468 | 61b24405 | aurel32 | break;
|
469 | 61b24405 | aurel32 | case 0x10: /* SDRAM_BEAR */ |
470 | 61b24405 | aurel32 | ret = sdram->bear; |
471 | 61b24405 | aurel32 | break;
|
472 | 61b24405 | aurel32 | case 0x20: /* SDRAM_CFG */ |
473 | 61b24405 | aurel32 | ret = sdram->cfg; |
474 | 61b24405 | aurel32 | break;
|
475 | 61b24405 | aurel32 | case 0x24: /* SDRAM_STATUS */ |
476 | 61b24405 | aurel32 | ret = sdram->status; |
477 | 61b24405 | aurel32 | break;
|
478 | 61b24405 | aurel32 | case 0x30: /* SDRAM_RTR */ |
479 | 61b24405 | aurel32 | ret = sdram->rtr; |
480 | 61b24405 | aurel32 | break;
|
481 | 61b24405 | aurel32 | case 0x34: /* SDRAM_PMIT */ |
482 | 61b24405 | aurel32 | ret = sdram->pmit; |
483 | 61b24405 | aurel32 | break;
|
484 | 61b24405 | aurel32 | case 0x40: /* SDRAM_B0CR */ |
485 | 61b24405 | aurel32 | ret = sdram->bcr[0];
|
486 | 61b24405 | aurel32 | break;
|
487 | 61b24405 | aurel32 | case 0x44: /* SDRAM_B1CR */ |
488 | 61b24405 | aurel32 | ret = sdram->bcr[1];
|
489 | 61b24405 | aurel32 | break;
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490 | 61b24405 | aurel32 | case 0x48: /* SDRAM_B2CR */ |
491 | 61b24405 | aurel32 | ret = sdram->bcr[2];
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492 | 61b24405 | aurel32 | break;
|
493 | 61b24405 | aurel32 | case 0x4C: /* SDRAM_B3CR */ |
494 | 61b24405 | aurel32 | ret = sdram->bcr[3];
|
495 | 61b24405 | aurel32 | break;
|
496 | 61b24405 | aurel32 | case 0x80: /* SDRAM_TR */ |
497 | 61b24405 | aurel32 | ret = -1; /* ? */ |
498 | 61b24405 | aurel32 | break;
|
499 | 61b24405 | aurel32 | case 0x94: /* SDRAM_ECCCFG */ |
500 | 61b24405 | aurel32 | ret = sdram->ecccfg; |
501 | 61b24405 | aurel32 | break;
|
502 | 61b24405 | aurel32 | case 0x98: /* SDRAM_ECCESR */ |
503 | 61b24405 | aurel32 | ret = sdram->eccesr; |
504 | 61b24405 | aurel32 | break;
|
505 | 61b24405 | aurel32 | default: /* Error */ |
506 | 61b24405 | aurel32 | ret = -1;
|
507 | 61b24405 | aurel32 | break;
|
508 | 61b24405 | aurel32 | } |
509 | 61b24405 | aurel32 | break;
|
510 | 61b24405 | aurel32 | default:
|
511 | 61b24405 | aurel32 | /* Avoid gcc warning */
|
512 | 61b24405 | aurel32 | ret = 0x00000000;
|
513 | 61b24405 | aurel32 | break;
|
514 | 61b24405 | aurel32 | } |
515 | 61b24405 | aurel32 | |
516 | 61b24405 | aurel32 | return ret;
|
517 | 61b24405 | aurel32 | } |
518 | 61b24405 | aurel32 | |
519 | 61b24405 | aurel32 | static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val) |
520 | 61b24405 | aurel32 | { |
521 | c227f099 | Anthony Liguori | ppc4xx_sdram_t *sdram; |
522 | 61b24405 | aurel32 | |
523 | 61b24405 | aurel32 | sdram = opaque; |
524 | 61b24405 | aurel32 | switch (dcrn) {
|
525 | 61b24405 | aurel32 | case SDRAM0_CFGADDR:
|
526 | 61b24405 | aurel32 | sdram->addr = val; |
527 | 61b24405 | aurel32 | break;
|
528 | 61b24405 | aurel32 | case SDRAM0_CFGDATA:
|
529 | 61b24405 | aurel32 | switch (sdram->addr) {
|
530 | 61b24405 | aurel32 | case 0x00: /* SDRAM_BESR0 */ |
531 | 61b24405 | aurel32 | sdram->besr0 &= ~val; |
532 | 61b24405 | aurel32 | break;
|
533 | 61b24405 | aurel32 | case 0x08: /* SDRAM_BESR1 */ |
534 | 61b24405 | aurel32 | sdram->besr1 &= ~val; |
535 | 61b24405 | aurel32 | break;
|
536 | 61b24405 | aurel32 | case 0x10: /* SDRAM_BEAR */ |
537 | 61b24405 | aurel32 | sdram->bear = val; |
538 | 61b24405 | aurel32 | break;
|
539 | 61b24405 | aurel32 | case 0x20: /* SDRAM_CFG */ |
540 | 61b24405 | aurel32 | val &= 0xFFE00000;
|
541 | 61b24405 | aurel32 | if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { |
542 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
543 | 61b24405 | aurel32 | printf("%s: enable SDRAM controller\n", __func__);
|
544 | 61b24405 | aurel32 | #endif
|
545 | 61b24405 | aurel32 | /* validate all RAM mappings */
|
546 | 61b24405 | aurel32 | sdram_map_bcr(sdram); |
547 | 61b24405 | aurel32 | sdram->status &= ~0x80000000;
|
548 | 61b24405 | aurel32 | } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { |
549 | 61b24405 | aurel32 | #ifdef DEBUG_SDRAM
|
550 | 61b24405 | aurel32 | printf("%s: disable SDRAM controller\n", __func__);
|
551 | 61b24405 | aurel32 | #endif
|
552 | 61b24405 | aurel32 | /* invalidate all RAM mappings */
|
553 | 61b24405 | aurel32 | sdram_unmap_bcr(sdram); |
554 | 61b24405 | aurel32 | sdram->status |= 0x80000000;
|
555 | 61b24405 | aurel32 | } |
556 | 61b24405 | aurel32 | if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) |
557 | 61b24405 | aurel32 | sdram->status |= 0x40000000;
|
558 | 61b24405 | aurel32 | else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) |
559 | 61b24405 | aurel32 | sdram->status &= ~0x40000000;
|
560 | 61b24405 | aurel32 | sdram->cfg = val; |
561 | 61b24405 | aurel32 | break;
|
562 | 61b24405 | aurel32 | case 0x24: /* SDRAM_STATUS */ |
563 | 61b24405 | aurel32 | /* Read-only register */
|
564 | 61b24405 | aurel32 | break;
|
565 | 61b24405 | aurel32 | case 0x30: /* SDRAM_RTR */ |
566 | 61b24405 | aurel32 | sdram->rtr = val & 0x3FF80000;
|
567 | 61b24405 | aurel32 | break;
|
568 | 61b24405 | aurel32 | case 0x34: /* SDRAM_PMIT */ |
569 | 61b24405 | aurel32 | sdram->pmit = (val & 0xF8000000) | 0x07C00000; |
570 | 61b24405 | aurel32 | break;
|
571 | 61b24405 | aurel32 | case 0x40: /* SDRAM_B0CR */ |
572 | 61b24405 | aurel32 | sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000); |
573 | 61b24405 | aurel32 | break;
|
574 | 61b24405 | aurel32 | case 0x44: /* SDRAM_B1CR */ |
575 | 61b24405 | aurel32 | sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000); |
576 | 61b24405 | aurel32 | break;
|
577 | 61b24405 | aurel32 | case 0x48: /* SDRAM_B2CR */ |
578 | 61b24405 | aurel32 | sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000); |
579 | 61b24405 | aurel32 | break;
|
580 | 61b24405 | aurel32 | case 0x4C: /* SDRAM_B3CR */ |
581 | 61b24405 | aurel32 | sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000); |
582 | 61b24405 | aurel32 | break;
|
583 | 61b24405 | aurel32 | case 0x80: /* SDRAM_TR */ |
584 | 61b24405 | aurel32 | sdram->tr = val & 0x018FC01F;
|
585 | 61b24405 | aurel32 | break;
|
586 | 61b24405 | aurel32 | case 0x94: /* SDRAM_ECCCFG */ |
587 | 61b24405 | aurel32 | sdram->ecccfg = val & 0x00F00000;
|
588 | 61b24405 | aurel32 | break;
|
589 | 61b24405 | aurel32 | case 0x98: /* SDRAM_ECCESR */ |
590 | 61b24405 | aurel32 | val &= 0xFFF0F000;
|
591 | 61b24405 | aurel32 | if (sdram->eccesr == 0 && val != 0) |
592 | 61b24405 | aurel32 | qemu_irq_raise(sdram->irq); |
593 | 61b24405 | aurel32 | else if (sdram->eccesr != 0 && val == 0) |
594 | 61b24405 | aurel32 | qemu_irq_lower(sdram->irq); |
595 | 61b24405 | aurel32 | sdram->eccesr = val; |
596 | 61b24405 | aurel32 | break;
|
597 | 61b24405 | aurel32 | default: /* Error */ |
598 | 61b24405 | aurel32 | break;
|
599 | 61b24405 | aurel32 | } |
600 | 61b24405 | aurel32 | break;
|
601 | 61b24405 | aurel32 | } |
602 | 61b24405 | aurel32 | } |
603 | 61b24405 | aurel32 | |
604 | 61b24405 | aurel32 | static void sdram_reset (void *opaque) |
605 | 61b24405 | aurel32 | { |
606 | c227f099 | Anthony Liguori | ppc4xx_sdram_t *sdram; |
607 | 61b24405 | aurel32 | |
608 | 61b24405 | aurel32 | sdram = opaque; |
609 | 61b24405 | aurel32 | sdram->addr = 0x00000000;
|
610 | 61b24405 | aurel32 | sdram->bear = 0x00000000;
|
611 | 61b24405 | aurel32 | sdram->besr0 = 0x00000000; /* No error */ |
612 | 61b24405 | aurel32 | sdram->besr1 = 0x00000000; /* No error */ |
613 | 61b24405 | aurel32 | sdram->cfg = 0x00000000;
|
614 | 61b24405 | aurel32 | sdram->ecccfg = 0x00000000; /* No ECC */ |
615 | 61b24405 | aurel32 | sdram->eccesr = 0x00000000; /* No error */ |
616 | 61b24405 | aurel32 | sdram->pmit = 0x07C00000;
|
617 | 61b24405 | aurel32 | sdram->rtr = 0x05F00000;
|
618 | 61b24405 | aurel32 | sdram->tr = 0x00854009;
|
619 | 61b24405 | aurel32 | /* We pre-initialize RAM banks */
|
620 | 61b24405 | aurel32 | sdram->status = 0x00000000;
|
621 | 61b24405 | aurel32 | sdram->cfg = 0x00800000;
|
622 | 61b24405 | aurel32 | sdram_unmap_bcr(sdram); |
623 | 61b24405 | aurel32 | } |
624 | 61b24405 | aurel32 | |
625 | 80e8bd2b | aurel32 | void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
626 | c227f099 | Anthony Liguori | target_phys_addr_t *ram_bases, |
627 | c227f099 | Anthony Liguori | target_phys_addr_t *ram_sizes, |
628 | 61b24405 | aurel32 | int do_init)
|
629 | 61b24405 | aurel32 | { |
630 | c227f099 | Anthony Liguori | ppc4xx_sdram_t *sdram; |
631 | 61b24405 | aurel32 | |
632 | c227f099 | Anthony Liguori | sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
|
633 | 487414f1 | aliguori | sdram->irq = irq; |
634 | 487414f1 | aliguori | sdram->nbanks = nbanks; |
635 | c227f099 | Anthony Liguori | memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); |
636 | 487414f1 | aliguori | memcpy(sdram->ram_bases, ram_bases, |
637 | c227f099 | Anthony Liguori | nbanks * sizeof(target_phys_addr_t));
|
638 | c227f099 | Anthony Liguori | memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); |
639 | 487414f1 | aliguori | memcpy(sdram->ram_sizes, ram_sizes, |
640 | c227f099 | Anthony Liguori | nbanks * sizeof(target_phys_addr_t));
|
641 | a08d4367 | Jan Kiszka | qemu_register_reset(&sdram_reset, sdram); |
642 | 487414f1 | aliguori | ppc_dcr_register(env, SDRAM0_CFGADDR, |
643 | 487414f1 | aliguori | sdram, &dcr_read_sdram, &dcr_write_sdram); |
644 | 487414f1 | aliguori | ppc_dcr_register(env, SDRAM0_CFGDATA, |
645 | 487414f1 | aliguori | sdram, &dcr_read_sdram, &dcr_write_sdram); |
646 | 487414f1 | aliguori | if (do_init)
|
647 | 487414f1 | aliguori | sdram_map_bcr(sdram); |
648 | 61b24405 | aurel32 | } |
649 | b7da58fd | aurel32 | |
650 | b7da58fd | aurel32 | /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
|
651 | b7da58fd | aurel32 | *
|
652 | b7da58fd | aurel32 | * sdram_bank_sizes[] must be 0-terminated.
|
653 | b7da58fd | aurel32 | *
|
654 | b7da58fd | aurel32 | * The 4xx SDRAM controller supports a small number of banks, and each bank
|
655 | b7da58fd | aurel32 | * must be one of a small set of sizes. The number of banks and the supported
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656 | b7da58fd | aurel32 | * sizes varies by SoC. */
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657 | c227f099 | Anthony Liguori | ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
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658 | c227f099 | Anthony Liguori | target_phys_addr_t ram_bases[], |
659 | c227f099 | Anthony Liguori | target_phys_addr_t ram_sizes[], |
660 | b7da58fd | aurel32 | const unsigned int sdram_bank_sizes[]) |
661 | b7da58fd | aurel32 | { |
662 | c227f099 | Anthony Liguori | ram_addr_t size_left = ram_size; |
663 | b7da58fd | aurel32 | int i;
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664 | b7da58fd | aurel32 | int j;
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665 | b7da58fd | aurel32 | |
666 | b7da58fd | aurel32 | for (i = 0; i < nr_banks; i++) { |
667 | b7da58fd | aurel32 | for (j = 0; sdram_bank_sizes[j] != 0; j++) { |
668 | b7da58fd | aurel32 | unsigned int bank_size = sdram_bank_sizes[j]; |
669 | b7da58fd | aurel32 | |
670 | 5c130f65 | pbrook | if (bank_size <= size_left) {
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671 | 5c130f65 | pbrook | ram_bases[i] = qemu_ram_alloc(bank_size); |
672 | b7da58fd | aurel32 | ram_sizes[i] = bank_size; |
673 | 5c130f65 | pbrook | size_left -= bank_size; |
674 | b7da58fd | aurel32 | break;
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675 | b7da58fd | aurel32 | } |
676 | b7da58fd | aurel32 | } |
677 | b7da58fd | aurel32 | |
678 | 5c130f65 | pbrook | if (!size_left) {
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679 | b7da58fd | aurel32 | /* No need to use the remaining banks. */
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680 | b7da58fd | aurel32 | break;
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681 | b7da58fd | aurel32 | } |
682 | b7da58fd | aurel32 | } |
683 | b7da58fd | aurel32 | |
684 | 5c130f65 | pbrook | ram_size -= size_left; |
685 | b7da58fd | aurel32 | if (ram_size)
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686 | b7da58fd | aurel32 | printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
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687 | 5c130f65 | pbrook | (int)(ram_size >> 20)); |
688 | b7da58fd | aurel32 | |
689 | 5c130f65 | pbrook | return ram_size;
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690 | b7da58fd | aurel32 | } |