root / hw / sun4m.c @ b4b784fe
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1 | 420557e8 | bellard | /*
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2 | ee76f82e | blueswir1 | * QEMU Sun4m & Sun4d & Sun4c System Emulator
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3 | 5fafdf24 | ths | *
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4 | b81b3b10 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 9d07d757 | Paul Brook | #include "sysbus.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sun4m.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 87ecb68b | pbrook | #include "sysemu.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 1cd3af54 | Gerd Hoffmann | #include "esp.h" |
35 | 22548760 | blueswir1 | #include "pc.h" |
36 | 22548760 | blueswir1 | #include "isa.h" |
37 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
38 | b4ed08e0 | blueswir1 | #include "escc.h" |
39 | 4b48bf05 | Blue Swirl | #include "qdev-addr.h" |
40 | ca20cf32 | Blue Swirl | #include "loader.h" |
41 | ca20cf32 | Blue Swirl | #include "elf.h" |
42 | d2c63fc1 | blueswir1 | |
43 | b3a23197 | blueswir1 | //#define DEBUG_IRQ
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44 | 420557e8 | bellard | |
45 | 36cd9210 | blueswir1 | /*
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46 | 36cd9210 | blueswir1 | * Sun4m architecture was used in the following machines:
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47 | 36cd9210 | blueswir1 | *
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48 | 36cd9210 | blueswir1 | * SPARCserver 6xxMP/xx
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49 | 77f193da | blueswir1 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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50 | 77f193da | blueswir1 | * SPARCclassic X (4/10)
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51 | 36cd9210 | blueswir1 | * SPARCstation LX/ZX (4/30)
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52 | 36cd9210 | blueswir1 | * SPARCstation Voyager
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53 | 36cd9210 | blueswir1 | * SPARCstation 10/xx, SPARCserver 10/xx
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54 | 36cd9210 | blueswir1 | * SPARCstation 5, SPARCserver 5
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55 | 36cd9210 | blueswir1 | * SPARCstation 20/xx, SPARCserver 20
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56 | 36cd9210 | blueswir1 | * SPARCstation 4
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57 | 36cd9210 | blueswir1 | *
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58 | 7d85892b | blueswir1 | * Sun4d architecture was used in the following machines:
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59 | 7d85892b | blueswir1 | *
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60 | 7d85892b | blueswir1 | * SPARCcenter 2000
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61 | 7d85892b | blueswir1 | * SPARCserver 1000
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62 | 7d85892b | blueswir1 | *
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63 | ee76f82e | blueswir1 | * Sun4c architecture was used in the following machines:
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64 | ee76f82e | blueswir1 | * SPARCstation 1/1+, SPARCserver 1/1+
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65 | ee76f82e | blueswir1 | * SPARCstation SLC
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66 | ee76f82e | blueswir1 | * SPARCstation IPC
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67 | ee76f82e | blueswir1 | * SPARCstation ELC
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68 | ee76f82e | blueswir1 | * SPARCstation IPX
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69 | ee76f82e | blueswir1 | *
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70 | 36cd9210 | blueswir1 | * See for example: http://www.sunhelp.org/faq/sunref1.html
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71 | 36cd9210 | blueswir1 | */
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72 | 36cd9210 | blueswir1 | |
73 | b3a23197 | blueswir1 | #ifdef DEBUG_IRQ
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74 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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75 | 001faf32 | Blue Swirl | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
76 | b3a23197 | blueswir1 | #else
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77 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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78 | b3a23197 | blueswir1 | #endif
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79 | b3a23197 | blueswir1 | |
80 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
81 | b6f479d3 | bellard | #define CMDLINE_ADDR 0x007ff000 |
82 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
83 | a7227727 | blueswir1 | #define PROM_SIZE_MAX (1024 * 1024) |
84 | 40ce0a9a | blueswir1 | #define PROM_VADDR 0xffd00000 |
85 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc32" |
86 | 3cce6243 | blueswir1 | #define CFG_ADDR 0xd00000510ULL |
87 | fbfcf955 | blueswir1 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
88 | b8174937 | bellard | |
89 | ba3c64fb | bellard | #define MAX_CPUS 16 |
90 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
91 | 420557e8 | bellard | |
92 | b4ed08e0 | blueswir1 | #define ESCC_CLOCK 4915200 |
93 | b4ed08e0 | blueswir1 | |
94 | 8137cde8 | blueswir1 | struct sun4m_hwdef {
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95 | c227f099 | Anthony Liguori | target_phys_addr_t iommu_base, slavio_base; |
96 | c227f099 | Anthony Liguori | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
97 | c227f099 | Anthony Liguori | target_phys_addr_t serial_base, fd_base; |
98 | c5de386a | Artyom Tarasenko | target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base; |
99 | c227f099 | Anthony Liguori | target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
100 | c227f099 | Anthony Liguori | target_phys_addr_t ecc_base; |
101 | 7eb0c8e8 | blueswir1 | uint32_t ecc_version; |
102 | 905fdcb5 | blueswir1 | uint8_t nvram_machine_id; |
103 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
104 | 7fbfb139 | blueswir1 | uint32_t iommu_version; |
105 | 3ebf5aaf | blueswir1 | uint64_t max_mem; |
106 | 3ebf5aaf | blueswir1 | const char * const default_cpu_model; |
107 | 36cd9210 | blueswir1 | }; |
108 | 36cd9210 | blueswir1 | |
109 | 7d85892b | blueswir1 | #define MAX_IOUNITS 5 |
110 | 7d85892b | blueswir1 | |
111 | 7d85892b | blueswir1 | struct sun4d_hwdef {
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112 | c227f099 | Anthony Liguori | target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; |
113 | c227f099 | Anthony Liguori | target_phys_addr_t counter_base, nvram_base, ms_kb_base; |
114 | c227f099 | Anthony Liguori | target_phys_addr_t serial_base; |
115 | c227f099 | Anthony Liguori | target_phys_addr_t espdma_base, esp_base; |
116 | c227f099 | Anthony Liguori | target_phys_addr_t ledma_base, le_base; |
117 | c227f099 | Anthony Liguori | target_phys_addr_t tcx_base; |
118 | c227f099 | Anthony Liguori | target_phys_addr_t sbi_base; |
119 | 905fdcb5 | blueswir1 | uint8_t nvram_machine_id; |
120 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
121 | 7d85892b | blueswir1 | uint32_t iounit_version; |
122 | 7d85892b | blueswir1 | uint64_t max_mem; |
123 | 7d85892b | blueswir1 | const char * const default_cpu_model; |
124 | 7d85892b | blueswir1 | }; |
125 | 7d85892b | blueswir1 | |
126 | 8137cde8 | blueswir1 | struct sun4c_hwdef {
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127 | c227f099 | Anthony Liguori | target_phys_addr_t iommu_base, slavio_base; |
128 | c227f099 | Anthony Liguori | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; |
129 | c227f099 | Anthony Liguori | target_phys_addr_t serial_base, fd_base; |
130 | c227f099 | Anthony Liguori | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
131 | c227f099 | Anthony Liguori | target_phys_addr_t tcx_base, aux1_base; |
132 | 8137cde8 | blueswir1 | uint8_t nvram_machine_id; |
133 | 8137cde8 | blueswir1 | uint16_t machine_id; |
134 | 8137cde8 | blueswir1 | uint32_t iommu_version; |
135 | 8137cde8 | blueswir1 | uint64_t max_mem; |
136 | 8137cde8 | blueswir1 | const char * const default_cpu_model; |
137 | 8137cde8 | blueswir1 | }; |
138 | 8137cde8 | blueswir1 | |
139 | 6f7e9aec | bellard | int DMA_get_channel_mode (int nchan) |
140 | 6f7e9aec | bellard | { |
141 | 6f7e9aec | bellard | return 0; |
142 | 6f7e9aec | bellard | } |
143 | 6f7e9aec | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
144 | 6f7e9aec | bellard | { |
145 | 6f7e9aec | bellard | return 0; |
146 | 6f7e9aec | bellard | } |
147 | 6f7e9aec | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
148 | 6f7e9aec | bellard | { |
149 | 6f7e9aec | bellard | return 0; |
150 | 6f7e9aec | bellard | } |
151 | 6f7e9aec | bellard | void DMA_hold_DREQ (int nchan) {} |
152 | 6f7e9aec | bellard | void DMA_release_DREQ (int nchan) {} |
153 | 6f7e9aec | bellard | void DMA_schedule(int nchan) {} |
154 | 6f7e9aec | bellard | void DMA_init (int high_page_enable) {} |
155 | 6f7e9aec | bellard | void DMA_register_channel (int nchan, |
156 | 6f7e9aec | bellard | DMA_transfer_handler transfer_handler, |
157 | 6f7e9aec | bellard | void *opaque)
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158 | 6f7e9aec | bellard | { |
159 | 6f7e9aec | bellard | } |
160 | 6f7e9aec | bellard | |
161 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
162 | 81864572 | blueswir1 | { |
163 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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164 | 81864572 | blueswir1 | return 0; |
165 | 81864572 | blueswir1 | } |
166 | 81864572 | blueswir1 | |
167 | c227f099 | Anthony Liguori | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
168 | c227f099 | Anthony Liguori | const char *boot_devices, ram_addr_t RAM_size, |
169 | f930d07e | blueswir1 | uint32_t kernel_size, |
170 | f930d07e | blueswir1 | int width, int height, int depth, |
171 | 905fdcb5 | blueswir1 | int nvram_machine_id, const char *arch) |
172 | e80cfcfc | bellard | { |
173 | d2c63fc1 | blueswir1 | unsigned int i; |
174 | 66508601 | blueswir1 | uint32_t start, end; |
175 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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176 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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177 | d2c63fc1 | blueswir1 | |
178 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
179 | e80cfcfc | bellard | |
180 | 513f789f | blueswir1 | start = 0;
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181 | b6f479d3 | bellard | |
182 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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183 | 66508601 | blueswir1 | // Variable partition
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184 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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185 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
186 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
187 | 66508601 | blueswir1 | |
188 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
189 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
190 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
191 | d2c63fc1 | blueswir1 | |
192 | d2c63fc1 | blueswir1 | // End marker
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193 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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194 | 66508601 | blueswir1 | |
195 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
196 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
197 | 66508601 | blueswir1 | |
198 | 66508601 | blueswir1 | // free partition
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199 | 66508601 | blueswir1 | start = end; |
200 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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201 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
202 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
203 | 66508601 | blueswir1 | |
204 | 66508601 | blueswir1 | end = 0x1fd0;
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205 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
206 | d2c63fc1 | blueswir1 | |
207 | 905fdcb5 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
208 | 905fdcb5 | blueswir1 | nvram_machine_id); |
209 | d2c63fc1 | blueswir1 | |
210 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
211 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
212 | e80cfcfc | bellard | } |
213 | e80cfcfc | bellard | |
214 | d453c2c3 | Blue Swirl | static DeviceState *slavio_intctl;
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215 | e80cfcfc | bellard | |
216 | 376253ec | aliguori | void pic_info(Monitor *mon)
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217 | e80cfcfc | bellard | { |
218 | 7d85892b | blueswir1 | if (slavio_intctl)
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219 | 376253ec | aliguori | slavio_pic_info(mon, slavio_intctl); |
220 | e80cfcfc | bellard | } |
221 | e80cfcfc | bellard | |
222 | 376253ec | aliguori | void irq_info(Monitor *mon)
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223 | e80cfcfc | bellard | { |
224 | 7d85892b | blueswir1 | if (slavio_intctl)
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225 | 376253ec | aliguori | slavio_irq_info(mon, slavio_intctl); |
226 | e80cfcfc | bellard | } |
227 | e80cfcfc | bellard | |
228 | 327ac2e7 | blueswir1 | void cpu_check_irqs(CPUState *env)
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229 | 327ac2e7 | blueswir1 | { |
230 | 327ac2e7 | blueswir1 | if (env->pil_in && (env->interrupt_index == 0 || |
231 | 327ac2e7 | blueswir1 | (env->interrupt_index & ~15) == TT_EXTINT)) {
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232 | 327ac2e7 | blueswir1 | unsigned int i; |
233 | 327ac2e7 | blueswir1 | |
234 | 327ac2e7 | blueswir1 | for (i = 15; i > 0; i--) { |
235 | 327ac2e7 | blueswir1 | if (env->pil_in & (1 << i)) { |
236 | 327ac2e7 | blueswir1 | int old_interrupt = env->interrupt_index;
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237 | 327ac2e7 | blueswir1 | |
238 | 327ac2e7 | blueswir1 | env->interrupt_index = TT_EXTINT | i; |
239 | f32d7ec5 | blueswir1 | if (old_interrupt != env->interrupt_index) {
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240 | f32d7ec5 | blueswir1 | DPRINTF("Set CPU IRQ %d\n", i);
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241 | 327ac2e7 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
242 | f32d7ec5 | blueswir1 | } |
243 | 327ac2e7 | blueswir1 | break;
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244 | 327ac2e7 | blueswir1 | } |
245 | 327ac2e7 | blueswir1 | } |
246 | 327ac2e7 | blueswir1 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
247 | f32d7ec5 | blueswir1 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
248 | 327ac2e7 | blueswir1 | env->interrupt_index = 0;
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249 | 327ac2e7 | blueswir1 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
250 | 327ac2e7 | blueswir1 | } |
251 | 327ac2e7 | blueswir1 | } |
252 | 327ac2e7 | blueswir1 | |
253 | b3a23197 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
254 | b3a23197 | blueswir1 | { |
255 | b3a23197 | blueswir1 | CPUState *env = opaque; |
256 | b3a23197 | blueswir1 | |
257 | b3a23197 | blueswir1 | if (level) {
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258 | b3a23197 | blueswir1 | DPRINTF("Raise CPU IRQ %d\n", irq);
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259 | b3a23197 | blueswir1 | env->halted = 0;
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260 | 327ac2e7 | blueswir1 | env->pil_in |= 1 << irq;
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261 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
262 | b3a23197 | blueswir1 | } else {
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263 | b3a23197 | blueswir1 | DPRINTF("Lower CPU IRQ %d\n", irq);
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264 | 327ac2e7 | blueswir1 | env->pil_in &= ~(1 << irq);
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265 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
266 | b3a23197 | blueswir1 | } |
267 | b3a23197 | blueswir1 | } |
268 | b3a23197 | blueswir1 | |
269 | b3a23197 | blueswir1 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
270 | b3a23197 | blueswir1 | { |
271 | b3a23197 | blueswir1 | } |
272 | b3a23197 | blueswir1 | |
273 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
274 | c68ea704 | bellard | { |
275 | c68ea704 | bellard | CPUState *env = opaque; |
276 | 3d29fbef | blueswir1 | |
277 | 3d29fbef | blueswir1 | cpu_reset(env); |
278 | 3d29fbef | blueswir1 | env->halted = 0;
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279 | 3d29fbef | blueswir1 | } |
280 | 3d29fbef | blueswir1 | |
281 | 3d29fbef | blueswir1 | static void secondary_cpu_reset(void *opaque) |
282 | 3d29fbef | blueswir1 | { |
283 | 3d29fbef | blueswir1 | CPUState *env = opaque; |
284 | 3d29fbef | blueswir1 | |
285 | c68ea704 | bellard | cpu_reset(env); |
286 | 3d29fbef | blueswir1 | env->halted = 1;
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287 | c68ea704 | bellard | } |
288 | c68ea704 | bellard | |
289 | 6d0c293d | blueswir1 | static void cpu_halt_signal(void *opaque, int irq, int level) |
290 | 6d0c293d | blueswir1 | { |
291 | 6d0c293d | blueswir1 | if (level && cpu_single_env)
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292 | 6d0c293d | blueswir1 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
293 | 6d0c293d | blueswir1 | } |
294 | 6d0c293d | blueswir1 | |
295 | 3ebf5aaf | blueswir1 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
296 | 293f78bc | blueswir1 | const char *initrd_filename, |
297 | c227f099 | Anthony Liguori | ram_addr_t RAM_size) |
298 | 3ebf5aaf | blueswir1 | { |
299 | 3ebf5aaf | blueswir1 | int linux_boot;
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300 | 3ebf5aaf | blueswir1 | unsigned int i; |
301 | 3ebf5aaf | blueswir1 | long initrd_size, kernel_size;
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302 | 3c178e72 | Gerd Hoffmann | uint8_t *ptr; |
303 | 3ebf5aaf | blueswir1 | |
304 | 3ebf5aaf | blueswir1 | linux_boot = (kernel_filename != NULL);
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305 | 3ebf5aaf | blueswir1 | |
306 | 3ebf5aaf | blueswir1 | kernel_size = 0;
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307 | 3ebf5aaf | blueswir1 | if (linux_boot) {
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308 | ca20cf32 | Blue Swirl | int bswap_needed;
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309 | ca20cf32 | Blue Swirl | |
310 | ca20cf32 | Blue Swirl | #ifdef BSWAP_NEEDED
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311 | ca20cf32 | Blue Swirl | bswap_needed = 1;
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312 | ca20cf32 | Blue Swirl | #else
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313 | ca20cf32 | Blue Swirl | bswap_needed = 0;
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314 | ca20cf32 | Blue Swirl | #endif
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315 | 3ebf5aaf | blueswir1 | kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, |
316 | ca20cf32 | Blue Swirl | NULL, 1, ELF_MACHINE, 0); |
317 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
318 | 293f78bc | blueswir1 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
319 | ca20cf32 | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
320 | ca20cf32 | Blue Swirl | TARGET_PAGE_SIZE); |
321 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
322 | 293f78bc | blueswir1 | kernel_size = load_image_targphys(kernel_filename, |
323 | 293f78bc | blueswir1 | KERNEL_LOAD_ADDR, |
324 | 293f78bc | blueswir1 | RAM_size - KERNEL_LOAD_ADDR); |
325 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) { |
326 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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327 | 3ebf5aaf | blueswir1 | kernel_filename); |
328 | 3ebf5aaf | blueswir1 | exit(1);
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329 | 3ebf5aaf | blueswir1 | } |
330 | 3ebf5aaf | blueswir1 | |
331 | 3ebf5aaf | blueswir1 | /* load initrd */
|
332 | 3ebf5aaf | blueswir1 | initrd_size = 0;
|
333 | 3ebf5aaf | blueswir1 | if (initrd_filename) {
|
334 | 293f78bc | blueswir1 | initrd_size = load_image_targphys(initrd_filename, |
335 | 293f78bc | blueswir1 | INITRD_LOAD_ADDR, |
336 | 293f78bc | blueswir1 | RAM_size - INITRD_LOAD_ADDR); |
337 | 3ebf5aaf | blueswir1 | if (initrd_size < 0) { |
338 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
339 | 3ebf5aaf | blueswir1 | initrd_filename); |
340 | 3ebf5aaf | blueswir1 | exit(1);
|
341 | 3ebf5aaf | blueswir1 | } |
342 | 3ebf5aaf | blueswir1 | } |
343 | 3ebf5aaf | blueswir1 | if (initrd_size > 0) { |
344 | 3ebf5aaf | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
345 | 3c178e72 | Gerd Hoffmann | ptr = rom_ptr(KERNEL_LOAD_ADDR + i); |
346 | 3c178e72 | Gerd Hoffmann | if (ldl_p(ptr) == 0x48647253) { // HdrS |
347 | 3c178e72 | Gerd Hoffmann | stl_p(ptr + 16, INITRD_LOAD_ADDR);
|
348 | 3c178e72 | Gerd Hoffmann | stl_p(ptr + 20, initrd_size);
|
349 | 3ebf5aaf | blueswir1 | break;
|
350 | 3ebf5aaf | blueswir1 | } |
351 | 3ebf5aaf | blueswir1 | } |
352 | 3ebf5aaf | blueswir1 | } |
353 | 3ebf5aaf | blueswir1 | } |
354 | 3ebf5aaf | blueswir1 | return kernel_size;
|
355 | 3ebf5aaf | blueswir1 | } |
356 | 3ebf5aaf | blueswir1 | |
357 | c227f099 | Anthony Liguori | static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq) |
358 | 4b48bf05 | Blue Swirl | { |
359 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
360 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
361 | 4b48bf05 | Blue Swirl | |
362 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "iommu"); |
363 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "version", version);
|
364 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
365 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
366 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
367 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
368 | 4b48bf05 | Blue Swirl | |
369 | 4b48bf05 | Blue Swirl | return s;
|
370 | 4b48bf05 | Blue Swirl | } |
371 | 4b48bf05 | Blue Swirl | |
372 | c227f099 | Anthony Liguori | static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq, |
373 | 74ff8d90 | Blue Swirl | void *iommu, qemu_irq *dev_irq)
|
374 | 74ff8d90 | Blue Swirl | { |
375 | 74ff8d90 | Blue Swirl | DeviceState *dev; |
376 | 74ff8d90 | Blue Swirl | SysBusDevice *s; |
377 | 74ff8d90 | Blue Swirl | |
378 | 74ff8d90 | Blue Swirl | dev = qdev_create(NULL, "sparc32_dma"); |
379 | 74ff8d90 | Blue Swirl | qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
|
380 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
381 | 74ff8d90 | Blue Swirl | s = sysbus_from_qdev(dev); |
382 | 74ff8d90 | Blue Swirl | sysbus_connect_irq(s, 0, parent_irq);
|
383 | 74ff8d90 | Blue Swirl | *dev_irq = qdev_get_gpio_in(dev, 0);
|
384 | 74ff8d90 | Blue Swirl | sysbus_mmio_map(s, 0, daddr);
|
385 | 74ff8d90 | Blue Swirl | |
386 | 74ff8d90 | Blue Swirl | return s;
|
387 | 74ff8d90 | Blue Swirl | } |
388 | 74ff8d90 | Blue Swirl | |
389 | c227f099 | Anthony Liguori | static void lance_init(NICInfo *nd, target_phys_addr_t leaddr, |
390 | 74ff8d90 | Blue Swirl | void *dma_opaque, qemu_irq irq)
|
391 | 9d07d757 | Paul Brook | { |
392 | 9d07d757 | Paul Brook | DeviceState *dev; |
393 | 9d07d757 | Paul Brook | SysBusDevice *s; |
394 | 74ff8d90 | Blue Swirl | qemu_irq reset; |
395 | 9d07d757 | Paul Brook | |
396 | 9d07d757 | Paul Brook | qemu_check_nic_model(&nd_table[0], "lance"); |
397 | 9d07d757 | Paul Brook | |
398 | 9d07d757 | Paul Brook | dev = qdev_create(NULL, "lance"); |
399 | 76224833 | Gerd Hoffmann | qdev_set_nic_properties(dev, nd); |
400 | daa65491 | Blue Swirl | qdev_prop_set_ptr(dev, "dma", dma_opaque);
|
401 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
402 | 9d07d757 | Paul Brook | s = sysbus_from_qdev(dev); |
403 | 9d07d757 | Paul Brook | sysbus_mmio_map(s, 0, leaddr);
|
404 | 9d07d757 | Paul Brook | sysbus_connect_irq(s, 0, irq);
|
405 | 74ff8d90 | Blue Swirl | reset = qdev_get_gpio_in(dev, 0);
|
406 | 74ff8d90 | Blue Swirl | qdev_connect_gpio_out(dma_opaque, 0, reset);
|
407 | 9d07d757 | Paul Brook | } |
408 | 9d07d757 | Paul Brook | |
409 | c227f099 | Anthony Liguori | static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
|
410 | c227f099 | Anthony Liguori | target_phys_addr_t addrg, |
411 | 462eda24 | Blue Swirl | qemu_irq **parent_irq) |
412 | 4b48bf05 | Blue Swirl | { |
413 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
414 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
415 | 4b48bf05 | Blue Swirl | unsigned int i, j; |
416 | 4b48bf05 | Blue Swirl | |
417 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_intctl"); |
418 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
419 | 4b48bf05 | Blue Swirl | |
420 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
421 | 4b48bf05 | Blue Swirl | |
422 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
423 | 4b48bf05 | Blue Swirl | for (j = 0; j < MAX_PILS; j++) { |
424 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); |
425 | 4b48bf05 | Blue Swirl | } |
426 | 4b48bf05 | Blue Swirl | } |
427 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addrg);
|
428 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
429 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
|
430 | 4b48bf05 | Blue Swirl | } |
431 | 4b48bf05 | Blue Swirl | |
432 | 4b48bf05 | Blue Swirl | return dev;
|
433 | 4b48bf05 | Blue Swirl | } |
434 | 4b48bf05 | Blue Swirl | |
435 | 4b48bf05 | Blue Swirl | #define SYS_TIMER_OFFSET 0x10000ULL |
436 | 4b48bf05 | Blue Swirl | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
437 | 4b48bf05 | Blue Swirl | |
438 | c227f099 | Anthony Liguori | static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq, |
439 | 4b48bf05 | Blue Swirl | qemu_irq *cpu_irqs, unsigned int num_cpus) |
440 | 4b48bf05 | Blue Swirl | { |
441 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
442 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
443 | 4b48bf05 | Blue Swirl | unsigned int i; |
444 | 4b48bf05 | Blue Swirl | |
445 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_timer"); |
446 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
|
447 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
448 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
449 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, master_irq);
|
450 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
|
451 | 4b48bf05 | Blue Swirl | |
452 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
453 | c227f099 | Anthony Liguori | sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
|
454 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
|
455 | 4b48bf05 | Blue Swirl | } |
456 | 4b48bf05 | Blue Swirl | } |
457 | 4b48bf05 | Blue Swirl | |
458 | 4b48bf05 | Blue Swirl | #define MISC_LEDS 0x01600000 |
459 | 4b48bf05 | Blue Swirl | #define MISC_CFG 0x01800000 |
460 | 4b48bf05 | Blue Swirl | #define MISC_DIAG 0x01a00000 |
461 | 4b48bf05 | Blue Swirl | #define MISC_MDM 0x01b00000 |
462 | 4b48bf05 | Blue Swirl | #define MISC_SYS 0x01f00000 |
463 | 4b48bf05 | Blue Swirl | |
464 | c227f099 | Anthony Liguori | static void slavio_misc_init(target_phys_addr_t base, |
465 | c227f099 | Anthony Liguori | target_phys_addr_t aux1_base, |
466 | c227f099 | Anthony Liguori | target_phys_addr_t aux2_base, qemu_irq irq, |
467 | b2b6f6ec | Blue Swirl | qemu_irq fdc_tc) |
468 | 4b48bf05 | Blue Swirl | { |
469 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
470 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
471 | 4b48bf05 | Blue Swirl | |
472 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_misc"); |
473 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
474 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
475 | 4b48bf05 | Blue Swirl | if (base) {
|
476 | 4b48bf05 | Blue Swirl | /* 8 bit registers */
|
477 | 4b48bf05 | Blue Swirl | /* Slavio control */
|
478 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, base + MISC_CFG);
|
479 | 4b48bf05 | Blue Swirl | /* Diagnostics */
|
480 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, base + MISC_DIAG);
|
481 | 4b48bf05 | Blue Swirl | /* Modem control */
|
482 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 2, base + MISC_MDM);
|
483 | 4b48bf05 | Blue Swirl | /* 16 bit registers */
|
484 | 4b48bf05 | Blue Swirl | /* ss600mp diag LEDs */
|
485 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 3, base + MISC_LEDS);
|
486 | 4b48bf05 | Blue Swirl | /* 32 bit registers */
|
487 | 4b48bf05 | Blue Swirl | /* System control */
|
488 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, base + MISC_SYS);
|
489 | 4b48bf05 | Blue Swirl | } |
490 | 4b48bf05 | Blue Swirl | if (aux1_base) {
|
491 | 4b48bf05 | Blue Swirl | /* AUX 1 (Misc System Functions) */
|
492 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 5, aux1_base);
|
493 | 4b48bf05 | Blue Swirl | } |
494 | 4b48bf05 | Blue Swirl | if (aux2_base) {
|
495 | 4b48bf05 | Blue Swirl | /* AUX 2 (Software Powerdown Control) */
|
496 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 6, aux2_base);
|
497 | 4b48bf05 | Blue Swirl | } |
498 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
499 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 1, fdc_tc);
|
500 | d9c32310 | Blue Swirl | qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
|
501 | 4b48bf05 | Blue Swirl | } |
502 | 4b48bf05 | Blue Swirl | |
503 | c227f099 | Anthony Liguori | static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
504 | 4b48bf05 | Blue Swirl | { |
505 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
506 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
507 | 4b48bf05 | Blue Swirl | |
508 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "eccmemctl"); |
509 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "version", version);
|
510 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
511 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
512 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
513 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, base);
|
514 | 4b48bf05 | Blue Swirl | if (version == 0) { // SS-600MP only |
515 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, base + 0x1000); |
516 | 4b48bf05 | Blue Swirl | } |
517 | 4b48bf05 | Blue Swirl | } |
518 | 4b48bf05 | Blue Swirl | |
519 | c227f099 | Anthony Liguori | static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt) |
520 | 4b48bf05 | Blue Swirl | { |
521 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
522 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
523 | 4b48bf05 | Blue Swirl | |
524 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "apc"); |
525 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
526 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
527 | 4b48bf05 | Blue Swirl | /* Power management (APC) XXX: not a Slavio device */
|
528 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, power_base);
|
529 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, cpu_halt);
|
530 | 4b48bf05 | Blue Swirl | } |
531 | 4b48bf05 | Blue Swirl | |
532 | c227f099 | Anthony Liguori | static void tcx_init(target_phys_addr_t addr, int vram_size, int width, |
533 | 4b48bf05 | Blue Swirl | int height, int depth) |
534 | 4b48bf05 | Blue Swirl | { |
535 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
536 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
537 | 4b48bf05 | Blue Swirl | |
538 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "SUNW,tcx"); |
539 | 4b48bf05 | Blue Swirl | qdev_prop_set_taddr(dev, "addr", addr);
|
540 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "vram_size", vram_size);
|
541 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "width", width);
|
542 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "height", height);
|
543 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "depth", depth);
|
544 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
545 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
546 | 4b48bf05 | Blue Swirl | /* 8-bit plane */
|
547 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr + 0x00800000ULL); |
548 | 4b48bf05 | Blue Swirl | /* DAC */
|
549 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, addr + 0x00200000ULL); |
550 | 4b48bf05 | Blue Swirl | /* TEC (dummy) */
|
551 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 2, addr + 0x00700000ULL); |
552 | 4b48bf05 | Blue Swirl | /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
|
553 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 3, addr + 0x00301000ULL); |
554 | 4b48bf05 | Blue Swirl | if (depth == 24) { |
555 | 4b48bf05 | Blue Swirl | /* 24-bit plane */
|
556 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, addr + 0x02000000ULL); |
557 | 4b48bf05 | Blue Swirl | /* Control plane */
|
558 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); |
559 | 4b48bf05 | Blue Swirl | } else {
|
560 | 4b48bf05 | Blue Swirl | /* THC 8 bit (dummy) */
|
561 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, addr + 0x00300000ULL); |
562 | 4b48bf05 | Blue Swirl | } |
563 | 4b48bf05 | Blue Swirl | } |
564 | 4b48bf05 | Blue Swirl | |
565 | 325f2747 | Blue Swirl | /* NCR89C100/MACIO Internal ID register */
|
566 | 325f2747 | Blue Swirl | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
567 | 325f2747 | Blue Swirl | |
568 | c227f099 | Anthony Liguori | static void idreg_init(target_phys_addr_t addr) |
569 | 325f2747 | Blue Swirl | { |
570 | 325f2747 | Blue Swirl | DeviceState *dev; |
571 | 325f2747 | Blue Swirl | SysBusDevice *s; |
572 | 325f2747 | Blue Swirl | |
573 | 325f2747 | Blue Swirl | dev = qdev_create(NULL, "macio_idreg"); |
574 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
575 | 325f2747 | Blue Swirl | s = sysbus_from_qdev(dev); |
576 | 325f2747 | Blue Swirl | |
577 | 325f2747 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
578 | 325f2747 | Blue Swirl | cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
|
579 | 325f2747 | Blue Swirl | } |
580 | 325f2747 | Blue Swirl | |
581 | 81a322d4 | Gerd Hoffmann | static int idreg_init1(SysBusDevice *dev) |
582 | 325f2747 | Blue Swirl | { |
583 | c227f099 | Anthony Liguori | ram_addr_t idreg_offset; |
584 | 325f2747 | Blue Swirl | |
585 | 325f2747 | Blue Swirl | idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
|
586 | 325f2747 | Blue Swirl | sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
|
587 | 81a322d4 | Gerd Hoffmann | return 0; |
588 | 325f2747 | Blue Swirl | } |
589 | 325f2747 | Blue Swirl | |
590 | 325f2747 | Blue Swirl | static SysBusDeviceInfo idreg_info = {
|
591 | 325f2747 | Blue Swirl | .init = idreg_init1, |
592 | 325f2747 | Blue Swirl | .qdev.name = "macio_idreg",
|
593 | 325f2747 | Blue Swirl | .qdev.size = sizeof(SysBusDevice),
|
594 | 325f2747 | Blue Swirl | }; |
595 | 325f2747 | Blue Swirl | |
596 | 325f2747 | Blue Swirl | static void idreg_register_devices(void) |
597 | 325f2747 | Blue Swirl | { |
598 | 325f2747 | Blue Swirl | sysbus_register_withprop(&idreg_info); |
599 | 325f2747 | Blue Swirl | } |
600 | 325f2747 | Blue Swirl | |
601 | 325f2747 | Blue Swirl | device_init(idreg_register_devices); |
602 | 325f2747 | Blue Swirl | |
603 | c5de386a | Artyom Tarasenko | /* SS-5 TCX AFX register */
|
604 | c5de386a | Artyom Tarasenko | static void afx_init(target_phys_addr_t addr) |
605 | c5de386a | Artyom Tarasenko | { |
606 | c5de386a | Artyom Tarasenko | DeviceState *dev; |
607 | c5de386a | Artyom Tarasenko | SysBusDevice *s; |
608 | c5de386a | Artyom Tarasenko | |
609 | c5de386a | Artyom Tarasenko | dev = qdev_create(NULL, "tcx_afx"); |
610 | c5de386a | Artyom Tarasenko | qdev_init_nofail(dev); |
611 | c5de386a | Artyom Tarasenko | s = sysbus_from_qdev(dev); |
612 | c5de386a | Artyom Tarasenko | |
613 | c5de386a | Artyom Tarasenko | sysbus_mmio_map(s, 0, addr);
|
614 | c5de386a | Artyom Tarasenko | } |
615 | c5de386a | Artyom Tarasenko | |
616 | c5de386a | Artyom Tarasenko | static int afx_init1(SysBusDevice *dev) |
617 | c5de386a | Artyom Tarasenko | { |
618 | c5de386a | Artyom Tarasenko | ram_addr_t afx_offset; |
619 | c5de386a | Artyom Tarasenko | |
620 | c5de386a | Artyom Tarasenko | afx_offset = qemu_ram_alloc(4);
|
621 | c5de386a | Artyom Tarasenko | sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
|
622 | c5de386a | Artyom Tarasenko | return 0; |
623 | c5de386a | Artyom Tarasenko | } |
624 | c5de386a | Artyom Tarasenko | |
625 | c5de386a | Artyom Tarasenko | static SysBusDeviceInfo afx_info = {
|
626 | c5de386a | Artyom Tarasenko | .init = afx_init1, |
627 | c5de386a | Artyom Tarasenko | .qdev.name = "tcx_afx",
|
628 | c5de386a | Artyom Tarasenko | .qdev.size = sizeof(SysBusDevice),
|
629 | c5de386a | Artyom Tarasenko | }; |
630 | c5de386a | Artyom Tarasenko | |
631 | c5de386a | Artyom Tarasenko | static void afx_register_devices(void) |
632 | c5de386a | Artyom Tarasenko | { |
633 | c5de386a | Artyom Tarasenko | sysbus_register_withprop(&afx_info); |
634 | c5de386a | Artyom Tarasenko | } |
635 | c5de386a | Artyom Tarasenko | |
636 | c5de386a | Artyom Tarasenko | device_init(afx_register_devices); |
637 | c5de386a | Artyom Tarasenko | |
638 | f48f6569 | Blue Swirl | /* Boot PROM (OpenBIOS) */
|
639 | c227f099 | Anthony Liguori | static void prom_init(target_phys_addr_t addr, const char *bios_name) |
640 | f48f6569 | Blue Swirl | { |
641 | f48f6569 | Blue Swirl | DeviceState *dev; |
642 | f48f6569 | Blue Swirl | SysBusDevice *s; |
643 | f48f6569 | Blue Swirl | char *filename;
|
644 | f48f6569 | Blue Swirl | int ret;
|
645 | f48f6569 | Blue Swirl | |
646 | f48f6569 | Blue Swirl | dev = qdev_create(NULL, "openprom"); |
647 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
648 | f48f6569 | Blue Swirl | s = sysbus_from_qdev(dev); |
649 | f48f6569 | Blue Swirl | |
650 | f48f6569 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
651 | f48f6569 | Blue Swirl | |
652 | f48f6569 | Blue Swirl | /* load boot prom */
|
653 | f48f6569 | Blue Swirl | if (bios_name == NULL) { |
654 | f48f6569 | Blue Swirl | bios_name = PROM_FILENAME; |
655 | f48f6569 | Blue Swirl | } |
656 | f48f6569 | Blue Swirl | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
657 | f48f6569 | Blue Swirl | if (filename) {
|
658 | ca20cf32 | Blue Swirl | ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL, |
659 | ca20cf32 | Blue Swirl | 1, ELF_MACHINE, 0); |
660 | f48f6569 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
661 | f48f6569 | Blue Swirl | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
662 | f48f6569 | Blue Swirl | } |
663 | f48f6569 | Blue Swirl | qemu_free(filename); |
664 | f48f6569 | Blue Swirl | } else {
|
665 | f48f6569 | Blue Swirl | ret = -1;
|
666 | f48f6569 | Blue Swirl | } |
667 | f48f6569 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
668 | f48f6569 | Blue Swirl | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
669 | f48f6569 | Blue Swirl | exit(1);
|
670 | f48f6569 | Blue Swirl | } |
671 | f48f6569 | Blue Swirl | } |
672 | f48f6569 | Blue Swirl | |
673 | 81a322d4 | Gerd Hoffmann | static int prom_init1(SysBusDevice *dev) |
674 | f48f6569 | Blue Swirl | { |
675 | c227f099 | Anthony Liguori | ram_addr_t prom_offset; |
676 | f48f6569 | Blue Swirl | |
677 | f48f6569 | Blue Swirl | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
678 | f48f6569 | Blue Swirl | sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); |
679 | 81a322d4 | Gerd Hoffmann | return 0; |
680 | f48f6569 | Blue Swirl | } |
681 | f48f6569 | Blue Swirl | |
682 | f48f6569 | Blue Swirl | static SysBusDeviceInfo prom_info = {
|
683 | f48f6569 | Blue Swirl | .init = prom_init1, |
684 | f48f6569 | Blue Swirl | .qdev.name = "openprom",
|
685 | f48f6569 | Blue Swirl | .qdev.size = sizeof(SysBusDevice),
|
686 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
687 | ee6847d1 | Gerd Hoffmann | {/* end of property list */}
|
688 | f48f6569 | Blue Swirl | } |
689 | f48f6569 | Blue Swirl | }; |
690 | f48f6569 | Blue Swirl | |
691 | f48f6569 | Blue Swirl | static void prom_register_devices(void) |
692 | f48f6569 | Blue Swirl | { |
693 | f48f6569 | Blue Swirl | sysbus_register_withprop(&prom_info); |
694 | f48f6569 | Blue Swirl | } |
695 | f48f6569 | Blue Swirl | |
696 | f48f6569 | Blue Swirl | device_init(prom_register_devices); |
697 | f48f6569 | Blue Swirl | |
698 | ee6847d1 | Gerd Hoffmann | typedef struct RamDevice |
699 | ee6847d1 | Gerd Hoffmann | { |
700 | ee6847d1 | Gerd Hoffmann | SysBusDevice busdev; |
701 | 04843626 | Blue Swirl | uint64_t size; |
702 | ee6847d1 | Gerd Hoffmann | } RamDevice; |
703 | ee6847d1 | Gerd Hoffmann | |
704 | a350db85 | Blue Swirl | /* System RAM */
|
705 | 81a322d4 | Gerd Hoffmann | static int ram_init1(SysBusDevice *dev) |
706 | a350db85 | Blue Swirl | { |
707 | c227f099 | Anthony Liguori | ram_addr_t RAM_size, ram_offset; |
708 | ee6847d1 | Gerd Hoffmann | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
709 | a350db85 | Blue Swirl | |
710 | ee6847d1 | Gerd Hoffmann | RAM_size = d->size; |
711 | a350db85 | Blue Swirl | |
712 | a350db85 | Blue Swirl | ram_offset = qemu_ram_alloc(RAM_size); |
713 | a350db85 | Blue Swirl | sysbus_init_mmio(dev, RAM_size, ram_offset); |
714 | 81a322d4 | Gerd Hoffmann | return 0; |
715 | a350db85 | Blue Swirl | } |
716 | a350db85 | Blue Swirl | |
717 | c227f099 | Anthony Liguori | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size, |
718 | a350db85 | Blue Swirl | uint64_t max_mem) |
719 | a350db85 | Blue Swirl | { |
720 | a350db85 | Blue Swirl | DeviceState *dev; |
721 | a350db85 | Blue Swirl | SysBusDevice *s; |
722 | ee6847d1 | Gerd Hoffmann | RamDevice *d; |
723 | a350db85 | Blue Swirl | |
724 | a350db85 | Blue Swirl | /* allocate RAM */
|
725 | a350db85 | Blue Swirl | if ((uint64_t)RAM_size > max_mem) {
|
726 | a350db85 | Blue Swirl | fprintf(stderr, |
727 | a350db85 | Blue Swirl | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
728 | a350db85 | Blue Swirl | (unsigned int)(RAM_size / (1024 * 1024)), |
729 | a350db85 | Blue Swirl | (unsigned int)(max_mem / (1024 * 1024))); |
730 | a350db85 | Blue Swirl | exit(1);
|
731 | a350db85 | Blue Swirl | } |
732 | a350db85 | Blue Swirl | dev = qdev_create(NULL, "memory"); |
733 | a350db85 | Blue Swirl | s = sysbus_from_qdev(dev); |
734 | a350db85 | Blue Swirl | |
735 | ee6847d1 | Gerd Hoffmann | d = FROM_SYSBUS(RamDevice, s); |
736 | ee6847d1 | Gerd Hoffmann | d->size = RAM_size; |
737 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
738 | ee6847d1 | Gerd Hoffmann | |
739 | a350db85 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
740 | a350db85 | Blue Swirl | } |
741 | a350db85 | Blue Swirl | |
742 | a350db85 | Blue Swirl | static SysBusDeviceInfo ram_info = {
|
743 | a350db85 | Blue Swirl | .init = ram_init1, |
744 | a350db85 | Blue Swirl | .qdev.name = "memory",
|
745 | ee6847d1 | Gerd Hoffmann | .qdev.size = sizeof(RamDevice),
|
746 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
747 | c885159a | Gerd Hoffmann | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
748 | c885159a | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
749 | a350db85 | Blue Swirl | } |
750 | a350db85 | Blue Swirl | }; |
751 | a350db85 | Blue Swirl | |
752 | a350db85 | Blue Swirl | static void ram_register_devices(void) |
753 | a350db85 | Blue Swirl | { |
754 | a350db85 | Blue Swirl | sysbus_register_withprop(&ram_info); |
755 | a350db85 | Blue Swirl | } |
756 | a350db85 | Blue Swirl | |
757 | a350db85 | Blue Swirl | device_init(ram_register_devices); |
758 | a350db85 | Blue Swirl | |
759 | 666713c0 | Blue Swirl | static CPUState *cpu_devinit(const char *cpu_model, unsigned int id, |
760 | 666713c0 | Blue Swirl | uint64_t prom_addr, qemu_irq **cpu_irqs) |
761 | 666713c0 | Blue Swirl | { |
762 | 666713c0 | Blue Swirl | CPUState *env; |
763 | 666713c0 | Blue Swirl | |
764 | 666713c0 | Blue Swirl | env = cpu_init(cpu_model); |
765 | 666713c0 | Blue Swirl | if (!env) {
|
766 | 666713c0 | Blue Swirl | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
767 | 666713c0 | Blue Swirl | exit(1);
|
768 | 666713c0 | Blue Swirl | } |
769 | 666713c0 | Blue Swirl | |
770 | 666713c0 | Blue Swirl | cpu_sparc_set_id(env, id); |
771 | 666713c0 | Blue Swirl | if (id == 0) { |
772 | 666713c0 | Blue Swirl | qemu_register_reset(main_cpu_reset, env); |
773 | 666713c0 | Blue Swirl | } else {
|
774 | 666713c0 | Blue Swirl | qemu_register_reset(secondary_cpu_reset, env); |
775 | 666713c0 | Blue Swirl | env->halted = 1;
|
776 | 666713c0 | Blue Swirl | } |
777 | 666713c0 | Blue Swirl | *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
778 | 666713c0 | Blue Swirl | env->prom_addr = prom_addr; |
779 | 666713c0 | Blue Swirl | |
780 | 666713c0 | Blue Swirl | return env;
|
781 | 666713c0 | Blue Swirl | } |
782 | 666713c0 | Blue Swirl | |
783 | c227f099 | Anthony Liguori | static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
784 | 3ebf5aaf | blueswir1 | const char *boot_device, |
785 | 3023f332 | aliguori | const char *kernel_filename, |
786 | 3ebf5aaf | blueswir1 | const char *kernel_cmdline, |
787 | 3ebf5aaf | blueswir1 | const char *initrd_filename, const char *cpu_model) |
788 | 420557e8 | bellard | { |
789 | 666713c0 | Blue Swirl | CPUState *envs[MAX_CPUS]; |
790 | 713c45fa | bellard | unsigned int i; |
791 | cfb9de9c | Paul Brook | void *iommu, *espdma, *ledma, *nvram;
|
792 | a1961a4b | Blue Swirl | qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
|
793 | 6f6260c7 | Blue Swirl | espdma_irq, ledma_irq; |
794 | 74ff8d90 | Blue Swirl | qemu_irq esp_reset; |
795 | 2582cfa0 | Blue Swirl | qemu_irq fdc_tc; |
796 | 6d0c293d | blueswir1 | qemu_irq *cpu_halt; |
797 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
798 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
799 | 3cce6243 | blueswir1 | void *fw_cfg;
|
800 | 420557e8 | bellard | |
801 | ba3c64fb | bellard | /* init CPUs */
|
802 | 3ebf5aaf | blueswir1 | if (!cpu_model)
|
803 | 3ebf5aaf | blueswir1 | cpu_model = hwdef->default_cpu_model; |
804 | b3a23197 | blueswir1 | |
805 | ba3c64fb | bellard | for(i = 0; i < smp_cpus; i++) { |
806 | 666713c0 | Blue Swirl | envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
807 | ba3c64fb | bellard | } |
808 | b3a23197 | blueswir1 | |
809 | b3a23197 | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
810 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
811 | b3a23197 | blueswir1 | |
812 | 3ebf5aaf | blueswir1 | |
813 | 3ebf5aaf | blueswir1 | /* set up devices */
|
814 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
815 | a350db85 | Blue Swirl | |
816 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
817 | f48f6569 | Blue Swirl | |
818 | d453c2c3 | Blue Swirl | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
819 | d453c2c3 | Blue Swirl | hwdef->intctl_base + 0x10000ULL,
|
820 | 462eda24 | Blue Swirl | cpu_irqs); |
821 | a1961a4b | Blue Swirl | |
822 | a1961a4b | Blue Swirl | for (i = 0; i < 32; i++) { |
823 | d453c2c3 | Blue Swirl | slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
824 | a1961a4b | Blue Swirl | } |
825 | a1961a4b | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
826 | d453c2c3 | Blue Swirl | slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
|
827 | a1961a4b | Blue Swirl | } |
828 | b3a23197 | blueswir1 | |
829 | fe096129 | blueswir1 | if (hwdef->idreg_base) {
|
830 | 325f2747 | Blue Swirl | idreg_init(hwdef->idreg_base); |
831 | 4c2485de | blueswir1 | } |
832 | 4c2485de | blueswir1 | |
833 | c5de386a | Artyom Tarasenko | if (hwdef->afx_base) {
|
834 | c5de386a | Artyom Tarasenko | afx_init(hwdef->afx_base); |
835 | c5de386a | Artyom Tarasenko | } |
836 | c5de386a | Artyom Tarasenko | |
837 | ff403da6 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
838 | c533e0b3 | Blue Swirl | slavio_irq[30]);
|
839 | ff403da6 | blueswir1 | |
840 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
|
841 | 74ff8d90 | Blue Swirl | iommu, &espdma_irq); |
842 | 2d069bab | blueswir1 | |
843 | 5aca8c3b | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
844 | 74ff8d90 | Blue Swirl | slavio_irq[16], iommu, &ledma_irq);
|
845 | ba3c64fb | bellard | |
846 | eee0b836 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
847 | eee0b836 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
848 | eee0b836 | blueswir1 | exit (1);
|
849 | eee0b836 | blueswir1 | } |
850 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
851 | dc828ca1 | pbrook | graphic_depth); |
852 | dbe06e18 | blueswir1 | |
853 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
854 | dbe06e18 | blueswir1 | |
855 | d95d8f1c | Blue Swirl | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
856 | 81732d19 | blueswir1 | |
857 | c533e0b3 | Blue Swirl | slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
|
858 | 81732d19 | blueswir1 | |
859 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
|
860 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
861 | b81b3b10 | bellard | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
862 | b81b3b10 | bellard | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
863 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], |
864 | aeeb69c7 | aurel32 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
865 | 741402f9 | blueswir1 | |
866 | 6d0c293d | blueswir1 | cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
867 | b2b6f6ec | Blue Swirl | slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
868 | b2b6f6ec | Blue Swirl | slavio_irq[30], fdc_tc);
|
869 | b2b6f6ec | Blue Swirl | |
870 | 2582cfa0 | Blue Swirl | if (hwdef->apc_base) {
|
871 | 2582cfa0 | Blue Swirl | apc_init(hwdef->apc_base, cpu_halt[0]);
|
872 | 2582cfa0 | Blue Swirl | } |
873 | 2be17ebd | blueswir1 | |
874 | fe096129 | blueswir1 | if (hwdef->fd_base) {
|
875 | e4bcb14c | ths | /* there is zero or one floppy drive */
|
876 | 309e60bd | blueswir1 | memset(fd, 0, sizeof(fd)); |
877 | fd8014e1 | Gerd Hoffmann | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
878 | c533e0b3 | Blue Swirl | sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
|
879 | 2582cfa0 | Blue Swirl | &fdc_tc); |
880 | e4bcb14c | ths | } |
881 | e4bcb14c | ths | |
882 | e4bcb14c | ths | if (drive_get_max_bus(IF_SCSI) > 0) { |
883 | e4bcb14c | ths | fprintf(stderr, "qemu: too many SCSI bus\n");
|
884 | e4bcb14c | ths | exit(1);
|
885 | e4bcb14c | ths | } |
886 | e4bcb14c | ths | |
887 | 74ff8d90 | Blue Swirl | esp_reset = qdev_get_gpio_in(espdma, 0);
|
888 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
889 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
890 | 74ff8d90 | Blue Swirl | espdma, espdma_irq, &esp_reset); |
891 | 74ff8d90 | Blue Swirl | |
892 | f1587550 | ths | |
893 | fa28ec52 | Blue Swirl | if (hwdef->cs_base) {
|
894 | fa28ec52 | Blue Swirl | sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
|
895 | c533e0b3 | Blue Swirl | slavio_irq[5]);
|
896 | fa28ec52 | Blue Swirl | } |
897 | b3ceef24 | blueswir1 | |
898 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
899 | 293f78bc | blueswir1 | RAM_size); |
900 | 36cd9210 | blueswir1 | |
901 | 36cd9210 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
902 | b3ceef24 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
903 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
904 | 905fdcb5 | blueswir1 | "Sun4m");
|
905 | 7eb0c8e8 | blueswir1 | |
906 | fe096129 | blueswir1 | if (hwdef->ecc_base)
|
907 | c533e0b3 | Blue Swirl | ecc_init(hwdef->ecc_base, slavio_irq[28],
|
908 | e42c20b4 | blueswir1 | hwdef->ecc_version); |
909 | 3cce6243 | blueswir1 | |
910 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
911 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
912 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
913 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
914 | fbfcf955 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
915 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
916 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
917 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
918 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
919 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
920 | 513f789f | blueswir1 | } else {
|
921 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
922 | 513f789f | blueswir1 | } |
923 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
924 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
925 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
926 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
927 | 36cd9210 | blueswir1 | } |
928 | 36cd9210 | blueswir1 | |
929 | 905fdcb5 | blueswir1 | enum {
|
930 | 905fdcb5 | blueswir1 | ss2_id = 0,
|
931 | 905fdcb5 | blueswir1 | ss5_id = 32,
|
932 | 905fdcb5 | blueswir1 | vger_id, |
933 | 905fdcb5 | blueswir1 | lx_id, |
934 | 905fdcb5 | blueswir1 | ss4_id, |
935 | 905fdcb5 | blueswir1 | scls_id, |
936 | 905fdcb5 | blueswir1 | sbook_id, |
937 | 905fdcb5 | blueswir1 | ss10_id = 64,
|
938 | 905fdcb5 | blueswir1 | ss20_id, |
939 | 905fdcb5 | blueswir1 | ss600mp_id, |
940 | 905fdcb5 | blueswir1 | ss1000_id = 96,
|
941 | 905fdcb5 | blueswir1 | ss2000_id, |
942 | 905fdcb5 | blueswir1 | }; |
943 | 905fdcb5 | blueswir1 | |
944 | 8137cde8 | blueswir1 | static const struct sun4m_hwdef sun4m_hwdefs[] = { |
945 | 36cd9210 | blueswir1 | /* SS-5 */
|
946 | 36cd9210 | blueswir1 | { |
947 | 36cd9210 | blueswir1 | .iommu_base = 0x10000000,
|
948 | 36cd9210 | blueswir1 | .tcx_base = 0x50000000,
|
949 | 36cd9210 | blueswir1 | .cs_base = 0x6c000000,
|
950 | 384ccb5d | blueswir1 | .slavio_base = 0x70000000,
|
951 | 36cd9210 | blueswir1 | .ms_kb_base = 0x71000000,
|
952 | 36cd9210 | blueswir1 | .serial_base = 0x71100000,
|
953 | 36cd9210 | blueswir1 | .nvram_base = 0x71200000,
|
954 | 36cd9210 | blueswir1 | .fd_base = 0x71400000,
|
955 | 36cd9210 | blueswir1 | .counter_base = 0x71d00000,
|
956 | 36cd9210 | blueswir1 | .intctl_base = 0x71e00000,
|
957 | 4c2485de | blueswir1 | .idreg_base = 0x78000000,
|
958 | 36cd9210 | blueswir1 | .dma_base = 0x78400000,
|
959 | 36cd9210 | blueswir1 | .esp_base = 0x78800000,
|
960 | 36cd9210 | blueswir1 | .le_base = 0x78c00000,
|
961 | 127fc407 | blueswir1 | .apc_base = 0x6a000000,
|
962 | c5de386a | Artyom Tarasenko | .afx_base = 0x6e000000,
|
963 | 0019ad53 | blueswir1 | .aux1_base = 0x71900000,
|
964 | 0019ad53 | blueswir1 | .aux2_base = 0x71910000,
|
965 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
966 | 905fdcb5 | blueswir1 | .machine_id = ss5_id, |
967 | cf3102ac | blueswir1 | .iommu_version = 0x05000000,
|
968 | 3ebf5aaf | blueswir1 | .max_mem = 0x10000000,
|
969 | 3ebf5aaf | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
970 | e0353fe2 | blueswir1 | }, |
971 | e0353fe2 | blueswir1 | /* SS-10 */
|
972 | e0353fe2 | blueswir1 | { |
973 | 5dcb6b91 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
974 | 5dcb6b91 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
975 | 5dcb6b91 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
976 | 5dcb6b91 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
977 | 5dcb6b91 | blueswir1 | .serial_base = 0xff1100000ULL,
|
978 | 5dcb6b91 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
979 | 5dcb6b91 | blueswir1 | .fd_base = 0xff1700000ULL,
|
980 | 5dcb6b91 | blueswir1 | .counter_base = 0xff1300000ULL,
|
981 | 5dcb6b91 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
982 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
983 | 5dcb6b91 | blueswir1 | .dma_base = 0xef0400000ULL,
|
984 | 5dcb6b91 | blueswir1 | .esp_base = 0xef0800000ULL,
|
985 | 5dcb6b91 | blueswir1 | .le_base = 0xef0c00000ULL,
|
986 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
987 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
988 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
989 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
990 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x10000000, // version 0, implementation 1 |
991 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
992 | 905fdcb5 | blueswir1 | .machine_id = ss10_id, |
993 | 7fbfb139 | blueswir1 | .iommu_version = 0x03000000,
|
994 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
995 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
996 | 36cd9210 | blueswir1 | }, |
997 | 6a3b9cc9 | blueswir1 | /* SS-600MP */
|
998 | 6a3b9cc9 | blueswir1 | { |
999 | 6a3b9cc9 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
1000 | 6a3b9cc9 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
1001 | 6a3b9cc9 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
1002 | 6a3b9cc9 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
1003 | 6a3b9cc9 | blueswir1 | .serial_base = 0xff1100000ULL,
|
1004 | 6a3b9cc9 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
1005 | 6a3b9cc9 | blueswir1 | .counter_base = 0xff1300000ULL,
|
1006 | 6a3b9cc9 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
1007 | 6a3b9cc9 | blueswir1 | .dma_base = 0xef0081000ULL,
|
1008 | 6a3b9cc9 | blueswir1 | .esp_base = 0xef0080000ULL,
|
1009 | 6a3b9cc9 | blueswir1 | .le_base = 0xef0060000ULL,
|
1010 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
1011 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
1012 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL, // XXX should not exist |
1013 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
1014 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x00000000, // version 0, implementation 0 |
1015 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x71,
|
1016 | 905fdcb5 | blueswir1 | .machine_id = ss600mp_id, |
1017 | 7fbfb139 | blueswir1 | .iommu_version = 0x01000000,
|
1018 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1019 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1020 | 6a3b9cc9 | blueswir1 | }, |
1021 | ae40972f | blueswir1 | /* SS-20 */
|
1022 | ae40972f | blueswir1 | { |
1023 | ae40972f | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
1024 | ae40972f | blueswir1 | .tcx_base = 0xe20000000ULL,
|
1025 | ae40972f | blueswir1 | .slavio_base = 0xff0000000ULL,
|
1026 | ae40972f | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
1027 | ae40972f | blueswir1 | .serial_base = 0xff1100000ULL,
|
1028 | ae40972f | blueswir1 | .nvram_base = 0xff1200000ULL,
|
1029 | ae40972f | blueswir1 | .fd_base = 0xff1700000ULL,
|
1030 | ae40972f | blueswir1 | .counter_base = 0xff1300000ULL,
|
1031 | ae40972f | blueswir1 | .intctl_base = 0xff1400000ULL,
|
1032 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
1033 | ae40972f | blueswir1 | .dma_base = 0xef0400000ULL,
|
1034 | ae40972f | blueswir1 | .esp_base = 0xef0800000ULL,
|
1035 | ae40972f | blueswir1 | .le_base = 0xef0c00000ULL,
|
1036 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
1037 | 577d8dd4 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
1038 | 577d8dd4 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
1039 | ae40972f | blueswir1 | .ecc_base = 0xf00000000ULL,
|
1040 | ae40972f | blueswir1 | .ecc_version = 0x20000000, // version 0, implementation 2 |
1041 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
1042 | 905fdcb5 | blueswir1 | .machine_id = ss20_id, |
1043 | ae40972f | blueswir1 | .iommu_version = 0x13000000,
|
1044 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1045 | ae40972f | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1046 | ae40972f | blueswir1 | }, |
1047 | a526a31c | blueswir1 | /* Voyager */
|
1048 | a526a31c | blueswir1 | { |
1049 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1050 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1051 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1052 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1053 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1054 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1055 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1056 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1057 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1058 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1059 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1060 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1061 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1062 | a526a31c | blueswir1 | .apc_base = 0x71300000, // pmc |
1063 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1064 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1065 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1066 | 905fdcb5 | blueswir1 | .machine_id = vger_id, |
1067 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1068 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1069 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1070 | a526a31c | blueswir1 | }, |
1071 | a526a31c | blueswir1 | /* LX */
|
1072 | a526a31c | blueswir1 | { |
1073 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1074 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1075 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1076 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1077 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1078 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1079 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1080 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1081 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1082 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1083 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1084 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1085 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1086 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1087 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1088 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1089 | 905fdcb5 | blueswir1 | .machine_id = lx_id, |
1090 | a526a31c | blueswir1 | .iommu_version = 0x04000000,
|
1091 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1092 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1093 | a526a31c | blueswir1 | }, |
1094 | a526a31c | blueswir1 | /* SS-4 */
|
1095 | a526a31c | blueswir1 | { |
1096 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1097 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1098 | a526a31c | blueswir1 | .cs_base = 0x6c000000,
|
1099 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1100 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1101 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1102 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1103 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1104 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1105 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1106 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1107 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1108 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1109 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1110 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1111 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1112 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1113 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1114 | 905fdcb5 | blueswir1 | .machine_id = ss4_id, |
1115 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1116 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1117 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1118 | a526a31c | blueswir1 | }, |
1119 | a526a31c | blueswir1 | /* SPARCClassic */
|
1120 | a526a31c | blueswir1 | { |
1121 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1122 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1123 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1124 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1125 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1126 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1127 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1128 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1129 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1130 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1131 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1132 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1133 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1134 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1135 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1136 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1137 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1138 | 905fdcb5 | blueswir1 | .machine_id = scls_id, |
1139 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1140 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1141 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1142 | a526a31c | blueswir1 | }, |
1143 | a526a31c | blueswir1 | /* SPARCbook */
|
1144 | a526a31c | blueswir1 | { |
1145 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1146 | a526a31c | blueswir1 | .tcx_base = 0x50000000, // XXX |
1147 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1148 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1149 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1150 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1151 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1152 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1153 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1154 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1155 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1156 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1157 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1158 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1159 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1160 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1161 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1162 | 905fdcb5 | blueswir1 | .machine_id = sbook_id, |
1163 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1164 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1165 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1166 | a526a31c | blueswir1 | }, |
1167 | 36cd9210 | blueswir1 | }; |
1168 | 36cd9210 | blueswir1 | |
1169 | 36cd9210 | blueswir1 | /* SPARCstation 5 hardware initialisation */
|
1170 | c227f099 | Anthony Liguori | static void ss5_init(ram_addr_t RAM_size, |
1171 | 3023f332 | aliguori | const char *boot_device, |
1172 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1173 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1174 | 36cd9210 | blueswir1 | { |
1175 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1176 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1177 | 420557e8 | bellard | } |
1178 | c0e564d5 | bellard | |
1179 | e0353fe2 | blueswir1 | /* SPARCstation 10 hardware initialisation */
|
1180 | c227f099 | Anthony Liguori | static void ss10_init(ram_addr_t RAM_size, |
1181 | 3023f332 | aliguori | const char *boot_device, |
1182 | b881c2c6 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1183 | b881c2c6 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1184 | e0353fe2 | blueswir1 | { |
1185 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1186 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1187 | e0353fe2 | blueswir1 | } |
1188 | e0353fe2 | blueswir1 | |
1189 | 6a3b9cc9 | blueswir1 | /* SPARCserver 600MP hardware initialisation */
|
1190 | c227f099 | Anthony Liguori | static void ss600mp_init(ram_addr_t RAM_size, |
1191 | 3023f332 | aliguori | const char *boot_device, |
1192 | 77f193da | blueswir1 | const char *kernel_filename, |
1193 | 77f193da | blueswir1 | const char *kernel_cmdline, |
1194 | 6a3b9cc9 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1195 | 6a3b9cc9 | blueswir1 | { |
1196 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
|
1197 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1198 | 6a3b9cc9 | blueswir1 | } |
1199 | 6a3b9cc9 | blueswir1 | |
1200 | ae40972f | blueswir1 | /* SPARCstation 20 hardware initialisation */
|
1201 | c227f099 | Anthony Liguori | static void ss20_init(ram_addr_t RAM_size, |
1202 | 3023f332 | aliguori | const char *boot_device, |
1203 | ae40972f | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1204 | ae40972f | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1205 | ae40972f | blueswir1 | { |
1206 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
|
1207 | ee76f82e | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1208 | ee76f82e | blueswir1 | } |
1209 | ee76f82e | blueswir1 | |
1210 | a526a31c | blueswir1 | /* SPARCstation Voyager hardware initialisation */
|
1211 | c227f099 | Anthony Liguori | static void vger_init(ram_addr_t RAM_size, |
1212 | 3023f332 | aliguori | const char *boot_device, |
1213 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1214 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1215 | a526a31c | blueswir1 | { |
1216 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
|
1217 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1218 | a526a31c | blueswir1 | } |
1219 | a526a31c | blueswir1 | |
1220 | a526a31c | blueswir1 | /* SPARCstation LX hardware initialisation */
|
1221 | c227f099 | Anthony Liguori | static void ss_lx_init(ram_addr_t RAM_size, |
1222 | 3023f332 | aliguori | const char *boot_device, |
1223 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1224 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1225 | a526a31c | blueswir1 | { |
1226 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
|
1227 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1228 | a526a31c | blueswir1 | } |
1229 | a526a31c | blueswir1 | |
1230 | a526a31c | blueswir1 | /* SPARCstation 4 hardware initialisation */
|
1231 | c227f099 | Anthony Liguori | static void ss4_init(ram_addr_t RAM_size, |
1232 | 3023f332 | aliguori | const char *boot_device, |
1233 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1234 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1235 | a526a31c | blueswir1 | { |
1236 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
|
1237 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1238 | a526a31c | blueswir1 | } |
1239 | a526a31c | blueswir1 | |
1240 | a526a31c | blueswir1 | /* SPARCClassic hardware initialisation */
|
1241 | c227f099 | Anthony Liguori | static void scls_init(ram_addr_t RAM_size, |
1242 | 3023f332 | aliguori | const char *boot_device, |
1243 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1244 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1245 | a526a31c | blueswir1 | { |
1246 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
|
1247 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1248 | a526a31c | blueswir1 | } |
1249 | a526a31c | blueswir1 | |
1250 | a526a31c | blueswir1 | /* SPARCbook hardware initialisation */
|
1251 | c227f099 | Anthony Liguori | static void sbook_init(ram_addr_t RAM_size, |
1252 | 3023f332 | aliguori | const char *boot_device, |
1253 | a526a31c | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1254 | a526a31c | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1255 | a526a31c | blueswir1 | { |
1256 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
|
1257 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1258 | a526a31c | blueswir1 | } |
1259 | a526a31c | blueswir1 | |
1260 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss5_machine = {
|
1261 | 66de733b | blueswir1 | .name = "SS-5",
|
1262 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 5",
|
1263 | 66de733b | blueswir1 | .init = ss5_init, |
1264 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1265 | 0c257437 | Anthony Liguori | .is_default = 1,
|
1266 | c0e564d5 | bellard | }; |
1267 | e0353fe2 | blueswir1 | |
1268 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss10_machine = {
|
1269 | 66de733b | blueswir1 | .name = "SS-10",
|
1270 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 10",
|
1271 | 66de733b | blueswir1 | .init = ss10_init, |
1272 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1273 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1274 | e0353fe2 | blueswir1 | }; |
1275 | 6a3b9cc9 | blueswir1 | |
1276 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss600mp_machine = {
|
1277 | 66de733b | blueswir1 | .name = "SS-600MP",
|
1278 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCserver 600MP",
|
1279 | 66de733b | blueswir1 | .init = ss600mp_init, |
1280 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1281 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1282 | 6a3b9cc9 | blueswir1 | }; |
1283 | ae40972f | blueswir1 | |
1284 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss20_machine = {
|
1285 | 66de733b | blueswir1 | .name = "SS-20",
|
1286 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 20",
|
1287 | 66de733b | blueswir1 | .init = ss20_init, |
1288 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1289 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1290 | ae40972f | blueswir1 | }; |
1291 | ae40972f | blueswir1 | |
1292 | f80f9ec9 | Anthony Liguori | static QEMUMachine voyager_machine = {
|
1293 | 66de733b | blueswir1 | .name = "Voyager",
|
1294 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation Voyager",
|
1295 | 66de733b | blueswir1 | .init = vger_init, |
1296 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1297 | a526a31c | blueswir1 | }; |
1298 | a526a31c | blueswir1 | |
1299 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss_lx_machine = {
|
1300 | 66de733b | blueswir1 | .name = "LX",
|
1301 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation LX",
|
1302 | 66de733b | blueswir1 | .init = ss_lx_init, |
1303 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1304 | a526a31c | blueswir1 | }; |
1305 | a526a31c | blueswir1 | |
1306 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss4_machine = {
|
1307 | 66de733b | blueswir1 | .name = "SS-4",
|
1308 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 4",
|
1309 | 66de733b | blueswir1 | .init = ss4_init, |
1310 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1311 | a526a31c | blueswir1 | }; |
1312 | a526a31c | blueswir1 | |
1313 | f80f9ec9 | Anthony Liguori | static QEMUMachine scls_machine = {
|
1314 | 66de733b | blueswir1 | .name = "SPARCClassic",
|
1315 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCClassic",
|
1316 | 66de733b | blueswir1 | .init = scls_init, |
1317 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1318 | a526a31c | blueswir1 | }; |
1319 | a526a31c | blueswir1 | |
1320 | f80f9ec9 | Anthony Liguori | static QEMUMachine sbook_machine = {
|
1321 | 66de733b | blueswir1 | .name = "SPARCbook",
|
1322 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCbook",
|
1323 | 66de733b | blueswir1 | .init = sbook_init, |
1324 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1325 | a526a31c | blueswir1 | }; |
1326 | a526a31c | blueswir1 | |
1327 | 7d85892b | blueswir1 | static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1328 | 7d85892b | blueswir1 | /* SS-1000 */
|
1329 | 7d85892b | blueswir1 | { |
1330 | 7d85892b | blueswir1 | .iounit_bases = { |
1331 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1332 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1333 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1334 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1335 | 7d85892b | blueswir1 | -1,
|
1336 | 7d85892b | blueswir1 | }, |
1337 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1338 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1339 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1340 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1341 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1342 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1343 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1344 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1345 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1346 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1347 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1348 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1349 | 905fdcb5 | blueswir1 | .machine_id = ss1000_id, |
1350 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1351 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1352 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1353 | 7d85892b | blueswir1 | }, |
1354 | 7d85892b | blueswir1 | /* SS-2000 */
|
1355 | 7d85892b | blueswir1 | { |
1356 | 7d85892b | blueswir1 | .iounit_bases = { |
1357 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1358 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1359 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1360 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1361 | 7d85892b | blueswir1 | 0xfe4200000ULL,
|
1362 | 7d85892b | blueswir1 | }, |
1363 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1364 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1365 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1366 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1367 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1368 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1369 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1370 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1371 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1372 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1373 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1374 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1375 | 905fdcb5 | blueswir1 | .machine_id = ss2000_id, |
1376 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1377 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1378 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1379 | 7d85892b | blueswir1 | }, |
1380 | 7d85892b | blueswir1 | }; |
1381 | 7d85892b | blueswir1 | |
1382 | c227f099 | Anthony Liguori | static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
|
1383 | 4b48bf05 | Blue Swirl | { |
1384 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
1385 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
1386 | 4b48bf05 | Blue Swirl | unsigned int i; |
1387 | 4b48bf05 | Blue Swirl | |
1388 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "sbi"); |
1389 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1390 | 4b48bf05 | Blue Swirl | |
1391 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
1392 | 4b48bf05 | Blue Swirl | |
1393 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
1394 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i, *parent_irq[i]); |
1395 | 4b48bf05 | Blue Swirl | } |
1396 | 4b48bf05 | Blue Swirl | |
1397 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
1398 | 4b48bf05 | Blue Swirl | |
1399 | 4b48bf05 | Blue Swirl | return dev;
|
1400 | 4b48bf05 | Blue Swirl | } |
1401 | 4b48bf05 | Blue Swirl | |
1402 | c227f099 | Anthony Liguori | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
1403 | 7d85892b | blueswir1 | const char *boot_device, |
1404 | 3023f332 | aliguori | const char *kernel_filename, |
1405 | 7d85892b | blueswir1 | const char *kernel_cmdline, |
1406 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1407 | 7d85892b | blueswir1 | { |
1408 | 666713c0 | Blue Swirl | CPUState *envs[MAX_CPUS]; |
1409 | 7d85892b | blueswir1 | unsigned int i; |
1410 | 7fc06735 | Blue Swirl | void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
|
1411 | 7fc06735 | Blue Swirl | qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
|
1412 | 6f6260c7 | Blue Swirl | espdma_irq, ledma_irq; |
1413 | 74ff8d90 | Blue Swirl | qemu_irq esp_reset; |
1414 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
1415 | 3cce6243 | blueswir1 | void *fw_cfg;
|
1416 | 7fc06735 | Blue Swirl | DeviceState *dev; |
1417 | 7d85892b | blueswir1 | |
1418 | 7d85892b | blueswir1 | /* init CPUs */
|
1419 | 7d85892b | blueswir1 | if (!cpu_model)
|
1420 | 7d85892b | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1421 | 7d85892b | blueswir1 | |
1422 | 666713c0 | Blue Swirl | for(i = 0; i < smp_cpus; i++) { |
1423 | 666713c0 | Blue Swirl | envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
1424 | 7d85892b | blueswir1 | } |
1425 | 7d85892b | blueswir1 | |
1426 | 7d85892b | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
1427 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1428 | 7d85892b | blueswir1 | |
1429 | 7d85892b | blueswir1 | /* set up devices */
|
1430 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
1431 | a350db85 | Blue Swirl | |
1432 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
1433 | f48f6569 | Blue Swirl | |
1434 | 7fc06735 | Blue Swirl | dev = sbi_init(hwdef->sbi_base, cpu_irqs); |
1435 | 7fc06735 | Blue Swirl | |
1436 | 7fc06735 | Blue Swirl | for (i = 0; i < 32; i++) { |
1437 | 7fc06735 | Blue Swirl | sbi_irq[i] = qdev_get_gpio_in(dev, i); |
1438 | 7fc06735 | Blue Swirl | } |
1439 | 7fc06735 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
1440 | 7fc06735 | Blue Swirl | sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
|
1441 | 7fc06735 | Blue Swirl | } |
1442 | 7d85892b | blueswir1 | |
1443 | 7d85892b | blueswir1 | for (i = 0; i < MAX_IOUNITS; i++) |
1444 | c227f099 | Anthony Liguori | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) |
1445 | ff403da6 | blueswir1 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1446 | ff403da6 | blueswir1 | hwdef->iounit_version, |
1447 | c533e0b3 | Blue Swirl | sbi_irq[0]);
|
1448 | 7d85892b | blueswir1 | |
1449 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
|
1450 | 74ff8d90 | Blue Swirl | iounits[0], &espdma_irq);
|
1451 | 7d85892b | blueswir1 | |
1452 | c533e0b3 | Blue Swirl | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
|
1453 | 74ff8d90 | Blue Swirl | iounits[0], &ledma_irq);
|
1454 | 7d85892b | blueswir1 | |
1455 | 7d85892b | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1456 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1457 | 7d85892b | blueswir1 | exit (1);
|
1458 | 7d85892b | blueswir1 | } |
1459 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1460 | dc828ca1 | pbrook | graphic_depth); |
1461 | 7d85892b | blueswir1 | |
1462 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1463 | 7d85892b | blueswir1 | |
1464 | d95d8f1c | Blue Swirl | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
1465 | 7d85892b | blueswir1 | |
1466 | c533e0b3 | Blue Swirl | slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
|
1467 | 7d85892b | blueswir1 | |
1468 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
|
1469 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1470 | 7d85892b | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1471 | 7d85892b | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1472 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12], |
1473 | aeeb69c7 | aurel32 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
1474 | 7d85892b | blueswir1 | |
1475 | 7d85892b | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1476 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1477 | 7d85892b | blueswir1 | exit(1);
|
1478 | 7d85892b | blueswir1 | } |
1479 | 7d85892b | blueswir1 | |
1480 | 74ff8d90 | Blue Swirl | esp_reset = qdev_get_gpio_in(espdma, 0);
|
1481 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
1482 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
1483 | 74ff8d90 | Blue Swirl | espdma, espdma_irq, &esp_reset); |
1484 | 7d85892b | blueswir1 | |
1485 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1486 | 293f78bc | blueswir1 | RAM_size); |
1487 | 7d85892b | blueswir1 | |
1488 | 7d85892b | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1489 | 7d85892b | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1490 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1491 | 905fdcb5 | blueswir1 | "Sun4d");
|
1492 | 3cce6243 | blueswir1 | |
1493 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1494 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1495 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1496 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1497 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1498 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1499 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1500 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1501 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1502 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
1503 | 513f789f | blueswir1 | } else {
|
1504 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1505 | 513f789f | blueswir1 | } |
1506 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1507 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1508 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1509 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1510 | 7d85892b | blueswir1 | } |
1511 | 7d85892b | blueswir1 | |
1512 | 7d85892b | blueswir1 | /* SPARCserver 1000 hardware initialisation */
|
1513 | c227f099 | Anthony Liguori | static void ss1000_init(ram_addr_t RAM_size, |
1514 | 3023f332 | aliguori | const char *boot_device, |
1515 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1516 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1517 | 7d85892b | blueswir1 | { |
1518 | 3023f332 | aliguori | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1519 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1520 | 7d85892b | blueswir1 | } |
1521 | 7d85892b | blueswir1 | |
1522 | 7d85892b | blueswir1 | /* SPARCcenter 2000 hardware initialisation */
|
1523 | c227f099 | Anthony Liguori | static void ss2000_init(ram_addr_t RAM_size, |
1524 | 3023f332 | aliguori | const char *boot_device, |
1525 | 7d85892b | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1526 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1527 | 7d85892b | blueswir1 | { |
1528 | 3023f332 | aliguori | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1529 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1530 | 7d85892b | blueswir1 | } |
1531 | 7d85892b | blueswir1 | |
1532 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss1000_machine = {
|
1533 | 66de733b | blueswir1 | .name = "SS-1000",
|
1534 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCserver 1000",
|
1535 | 66de733b | blueswir1 | .init = ss1000_init, |
1536 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1537 | 1bcee014 | blueswir1 | .max_cpus = 8,
|
1538 | 7d85892b | blueswir1 | }; |
1539 | 7d85892b | blueswir1 | |
1540 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss2000_machine = {
|
1541 | 66de733b | blueswir1 | .name = "SS-2000",
|
1542 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCcenter 2000",
|
1543 | 66de733b | blueswir1 | .init = ss2000_init, |
1544 | c9b1ae2c | blueswir1 | .use_scsi = 1,
|
1545 | 1bcee014 | blueswir1 | .max_cpus = 20,
|
1546 | 7d85892b | blueswir1 | }; |
1547 | 8137cde8 | blueswir1 | |
1548 | 8137cde8 | blueswir1 | static const struct sun4c_hwdef sun4c_hwdefs[] = { |
1549 | 8137cde8 | blueswir1 | /* SS-2 */
|
1550 | 8137cde8 | blueswir1 | { |
1551 | 8137cde8 | blueswir1 | .iommu_base = 0xf8000000,
|
1552 | 8137cde8 | blueswir1 | .tcx_base = 0xfe000000,
|
1553 | 8137cde8 | blueswir1 | .slavio_base = 0xf6000000,
|
1554 | 8137cde8 | blueswir1 | .intctl_base = 0xf5000000,
|
1555 | 8137cde8 | blueswir1 | .counter_base = 0xf3000000,
|
1556 | 8137cde8 | blueswir1 | .ms_kb_base = 0xf0000000,
|
1557 | 8137cde8 | blueswir1 | .serial_base = 0xf1000000,
|
1558 | 8137cde8 | blueswir1 | .nvram_base = 0xf2000000,
|
1559 | 8137cde8 | blueswir1 | .fd_base = 0xf7200000,
|
1560 | 8137cde8 | blueswir1 | .dma_base = 0xf8400000,
|
1561 | 8137cde8 | blueswir1 | .esp_base = 0xf8800000,
|
1562 | 8137cde8 | blueswir1 | .le_base = 0xf8c00000,
|
1563 | 8137cde8 | blueswir1 | .aux1_base = 0xf7400003,
|
1564 | 8137cde8 | blueswir1 | .nvram_machine_id = 0x55,
|
1565 | 8137cde8 | blueswir1 | .machine_id = ss2_id, |
1566 | 8137cde8 | blueswir1 | .max_mem = 0x10000000,
|
1567 | 8137cde8 | blueswir1 | .default_cpu_model = "Cypress CY7C601",
|
1568 | 8137cde8 | blueswir1 | }, |
1569 | 8137cde8 | blueswir1 | }; |
1570 | 8137cde8 | blueswir1 | |
1571 | c227f099 | Anthony Liguori | static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
|
1572 | 4b48bf05 | Blue Swirl | qemu_irq *parent_irq) |
1573 | 4b48bf05 | Blue Swirl | { |
1574 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
1575 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
1576 | 4b48bf05 | Blue Swirl | unsigned int i; |
1577 | 4b48bf05 | Blue Swirl | |
1578 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "sun4c_intctl"); |
1579 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1580 | 4b48bf05 | Blue Swirl | |
1581 | 4b48bf05 | Blue Swirl | s = sysbus_from_qdev(dev); |
1582 | 4b48bf05 | Blue Swirl | |
1583 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_PILS; i++) { |
1584 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i, parent_irq[i]); |
1585 | 4b48bf05 | Blue Swirl | } |
1586 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
1587 | 4b48bf05 | Blue Swirl | |
1588 | 4b48bf05 | Blue Swirl | return dev;
|
1589 | 4b48bf05 | Blue Swirl | } |
1590 | 4b48bf05 | Blue Swirl | |
1591 | c227f099 | Anthony Liguori | static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
1592 | 8137cde8 | blueswir1 | const char *boot_device, |
1593 | 3023f332 | aliguori | const char *kernel_filename, |
1594 | 8137cde8 | blueswir1 | const char *kernel_cmdline, |
1595 | 8137cde8 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1596 | 8137cde8 | blueswir1 | { |
1597 | 8137cde8 | blueswir1 | CPUState *env; |
1598 | cfb9de9c | Paul Brook | void *iommu, *espdma, *ledma, *nvram;
|
1599 | e32cba29 | Blue Swirl | qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
|
1600 | 74ff8d90 | Blue Swirl | qemu_irq esp_reset; |
1601 | 2582cfa0 | Blue Swirl | qemu_irq fdc_tc; |
1602 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
1603 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
1604 | 8137cde8 | blueswir1 | void *fw_cfg;
|
1605 | e32cba29 | Blue Swirl | DeviceState *dev; |
1606 | e32cba29 | Blue Swirl | unsigned int i; |
1607 | 8137cde8 | blueswir1 | |
1608 | 8137cde8 | blueswir1 | /* init CPU */
|
1609 | 8137cde8 | blueswir1 | if (!cpu_model)
|
1610 | 8137cde8 | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1611 | 8137cde8 | blueswir1 | |
1612 | 666713c0 | Blue Swirl | env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
|
1613 | 8137cde8 | blueswir1 | |
1614 | 8137cde8 | blueswir1 | /* set up devices */
|
1615 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
1616 | a350db85 | Blue Swirl | |
1617 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
1618 | f48f6569 | Blue Swirl | |
1619 | e32cba29 | Blue Swirl | dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs); |
1620 | e32cba29 | Blue Swirl | |
1621 | e32cba29 | Blue Swirl | for (i = 0; i < 8; i++) { |
1622 | e32cba29 | Blue Swirl | slavio_irq[i] = qdev_get_gpio_in(dev, i); |
1623 | e32cba29 | Blue Swirl | } |
1624 | 8137cde8 | blueswir1 | |
1625 | 8137cde8 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
1626 | c533e0b3 | Blue Swirl | slavio_irq[1]);
|
1627 | 8137cde8 | blueswir1 | |
1628 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
|
1629 | 74ff8d90 | Blue Swirl | iommu, &espdma_irq); |
1630 | 8137cde8 | blueswir1 | |
1631 | 8137cde8 | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
1632 | 74ff8d90 | Blue Swirl | slavio_irq[3], iommu, &ledma_irq);
|
1633 | 8137cde8 | blueswir1 | |
1634 | 8137cde8 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1635 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1636 | 8137cde8 | blueswir1 | exit (1);
|
1637 | 8137cde8 | blueswir1 | } |
1638 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1639 | dc828ca1 | pbrook | graphic_depth); |
1640 | 8137cde8 | blueswir1 | |
1641 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1642 | 8137cde8 | blueswir1 | |
1643 | d95d8f1c | Blue Swirl | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2); |
1644 | 8137cde8 | blueswir1 | |
1645 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
|
1646 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1647 | 8137cde8 | blueswir1 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
1648 | 8137cde8 | blueswir1 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
1649 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, slavio_irq[1],
|
1650 | c533e0b3 | Blue Swirl | slavio_irq[1], serial_hds[0], serial_hds[1], |
1651 | aeeb69c7 | aurel32 | ESCC_CLOCK, 1);
|
1652 | 8137cde8 | blueswir1 | |
1653 | b2b6f6ec | Blue Swirl | slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc); |
1654 | 8137cde8 | blueswir1 | |
1655 | c227f099 | Anthony Liguori | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
1656 | 8137cde8 | blueswir1 | /* there is zero or one floppy drive */
|
1657 | ce802585 | blueswir1 | memset(fd, 0, sizeof(fd)); |
1658 | fd8014e1 | Gerd Hoffmann | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
1659 | c533e0b3 | Blue Swirl | sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
|
1660 | 2582cfa0 | Blue Swirl | &fdc_tc); |
1661 | 8137cde8 | blueswir1 | } |
1662 | 8137cde8 | blueswir1 | |
1663 | 8137cde8 | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1664 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1665 | 8137cde8 | blueswir1 | exit(1);
|
1666 | 8137cde8 | blueswir1 | } |
1667 | 8137cde8 | blueswir1 | |
1668 | 74ff8d90 | Blue Swirl | esp_reset = qdev_get_gpio_in(espdma, 0);
|
1669 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
1670 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
1671 | 74ff8d90 | Blue Swirl | espdma, espdma_irq, &esp_reset); |
1672 | 8137cde8 | blueswir1 | |
1673 | 8137cde8 | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1674 | 8137cde8 | blueswir1 | RAM_size); |
1675 | 8137cde8 | blueswir1 | |
1676 | 8137cde8 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1677 | 8137cde8 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1678 | 8137cde8 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1679 | 8137cde8 | blueswir1 | "Sun4c");
|
1680 | 8137cde8 | blueswir1 | |
1681 | 8137cde8 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1682 | 8137cde8 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1683 | 8137cde8 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1684 | 8137cde8 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1685 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1686 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1687 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1688 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1689 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1690 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
1691 | 513f789f | blueswir1 | } else {
|
1692 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1693 | 513f789f | blueswir1 | } |
1694 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1695 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1696 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1697 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1698 | 8137cde8 | blueswir1 | } |
1699 | 8137cde8 | blueswir1 | |
1700 | 8137cde8 | blueswir1 | /* SPARCstation 2 hardware initialisation */
|
1701 | c227f099 | Anthony Liguori | static void ss2_init(ram_addr_t RAM_size, |
1702 | 3023f332 | aliguori | const char *boot_device, |
1703 | 8137cde8 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
1704 | 8137cde8 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1705 | 8137cde8 | blueswir1 | { |
1706 | 3023f332 | aliguori | sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1707 | 8137cde8 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1708 | 8137cde8 | blueswir1 | } |
1709 | 8137cde8 | blueswir1 | |
1710 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss2_machine = {
|
1711 | 8137cde8 | blueswir1 | .name = "SS-2",
|
1712 | 8137cde8 | blueswir1 | .desc = "Sun4c platform, SPARCstation 2",
|
1713 | 8137cde8 | blueswir1 | .init = ss2_init, |
1714 | 8137cde8 | blueswir1 | .use_scsi = 1,
|
1715 | 8137cde8 | blueswir1 | }; |
1716 | f80f9ec9 | Anthony Liguori | |
1717 | f80f9ec9 | Anthony Liguori | static void ss2_machine_init(void) |
1718 | f80f9ec9 | Anthony Liguori | { |
1719 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss5_machine); |
1720 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss10_machine); |
1721 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss600mp_machine); |
1722 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss20_machine); |
1723 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&voyager_machine); |
1724 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss_lx_machine); |
1725 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss4_machine); |
1726 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&scls_machine); |
1727 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sbook_machine); |
1728 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss1000_machine); |
1729 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss2000_machine); |
1730 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss2_machine); |
1731 | f80f9ec9 | Anthony Liguori | } |
1732 | f80f9ec9 | Anthony Liguori | |
1733 | f80f9ec9 | Anthony Liguori | machine_init(ss2_machine_init); |