root / hw / xilinx_timer.c @ b4b784fe
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1 | 388f60b1 | Edgar E. Iglesias | /*
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2 | 388f60b1 | Edgar E. Iglesias | * QEMU model of the Xilinx timer block.
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3 | 388f60b1 | Edgar E. Iglesias | *
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4 | 388f60b1 | Edgar E. Iglesias | * Copyright (c) 2009 Edgar E. Iglesias.
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5 | 388f60b1 | Edgar E. Iglesias | *
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6 | 388f60b1 | Edgar E. Iglesias | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 388f60b1 | Edgar E. Iglesias | * of this software and associated documentation files (the "Software"), to deal
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8 | 388f60b1 | Edgar E. Iglesias | * in the Software without restriction, including without limitation the rights
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9 | 388f60b1 | Edgar E. Iglesias | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 388f60b1 | Edgar E. Iglesias | * copies of the Software, and to permit persons to whom the Software is
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11 | 388f60b1 | Edgar E. Iglesias | * furnished to do so, subject to the following conditions:
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12 | 388f60b1 | Edgar E. Iglesias | *
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13 | 388f60b1 | Edgar E. Iglesias | * The above copyright notice and this permission notice shall be included in
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14 | 388f60b1 | Edgar E. Iglesias | * all copies or substantial portions of the Software.
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15 | 388f60b1 | Edgar E. Iglesias | *
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16 | 388f60b1 | Edgar E. Iglesias | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 388f60b1 | Edgar E. Iglesias | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 388f60b1 | Edgar E. Iglesias | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 388f60b1 | Edgar E. Iglesias | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 388f60b1 | Edgar E. Iglesias | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 388f60b1 | Edgar E. Iglesias | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 388f60b1 | Edgar E. Iglesias | * THE SOFTWARE.
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23 | 388f60b1 | Edgar E. Iglesias | */
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24 | 388f60b1 | Edgar E. Iglesias | |
25 | 388f60b1 | Edgar E. Iglesias | #include "sysbus.h" |
26 | 388f60b1 | Edgar E. Iglesias | #include "sysemu.h" |
27 | 388f60b1 | Edgar E. Iglesias | #include "qemu-timer.h" |
28 | 388f60b1 | Edgar E. Iglesias | |
29 | 388f60b1 | Edgar E. Iglesias | #define D(x)
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30 | 388f60b1 | Edgar E. Iglesias | |
31 | 388f60b1 | Edgar E. Iglesias | #define R_TCSR 0 |
32 | 388f60b1 | Edgar E. Iglesias | #define R_TLR 1 |
33 | 388f60b1 | Edgar E. Iglesias | #define R_TCR 2 |
34 | 388f60b1 | Edgar E. Iglesias | #define R_MAX 4 |
35 | 388f60b1 | Edgar E. Iglesias | |
36 | 388f60b1 | Edgar E. Iglesias | #define TCSR_MDT (1<<0) |
37 | 388f60b1 | Edgar E. Iglesias | #define TCSR_UDT (1<<1) |
38 | 388f60b1 | Edgar E. Iglesias | #define TCSR_GENT (1<<2) |
39 | 388f60b1 | Edgar E. Iglesias | #define TCSR_CAPT (1<<3) |
40 | 388f60b1 | Edgar E. Iglesias | #define TCSR_ARHT (1<<4) |
41 | 388f60b1 | Edgar E. Iglesias | #define TCSR_LOAD (1<<5) |
42 | 388f60b1 | Edgar E. Iglesias | #define TCSR_ENIT (1<<6) |
43 | 388f60b1 | Edgar E. Iglesias | #define TCSR_ENT (1<<7) |
44 | 388f60b1 | Edgar E. Iglesias | #define TCSR_TINT (1<<8) |
45 | 388f60b1 | Edgar E. Iglesias | #define TCSR_PWMA (1<<9) |
46 | 388f60b1 | Edgar E. Iglesias | #define TCSR_ENALL (1<<10) |
47 | 388f60b1 | Edgar E. Iglesias | |
48 | 388f60b1 | Edgar E. Iglesias | struct xlx_timer
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49 | 388f60b1 | Edgar E. Iglesias | { |
50 | 388f60b1 | Edgar E. Iglesias | QEMUBH *bh; |
51 | 388f60b1 | Edgar E. Iglesias | ptimer_state *ptimer; |
52 | 388f60b1 | Edgar E. Iglesias | void *parent;
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53 | 388f60b1 | Edgar E. Iglesias | int nr; /* for debug. */ |
54 | 388f60b1 | Edgar E. Iglesias | |
55 | 388f60b1 | Edgar E. Iglesias | unsigned long timer_div; |
56 | 388f60b1 | Edgar E. Iglesias | |
57 | 388f60b1 | Edgar E. Iglesias | uint32_t regs[R_MAX]; |
58 | 388f60b1 | Edgar E. Iglesias | }; |
59 | 388f60b1 | Edgar E. Iglesias | |
60 | 388f60b1 | Edgar E. Iglesias | struct timerblock
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61 | 388f60b1 | Edgar E. Iglesias | { |
62 | 388f60b1 | Edgar E. Iglesias | SysBusDevice busdev; |
63 | 388f60b1 | Edgar E. Iglesias | qemu_irq irq; |
64 | ee6847d1 | Gerd Hoffmann | uint32_t nr_timers; |
65 | ee6847d1 | Gerd Hoffmann | uint32_t freq_hz; |
66 | 388f60b1 | Edgar E. Iglesias | struct xlx_timer *timers;
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67 | 388f60b1 | Edgar E. Iglesias | }; |
68 | 388f60b1 | Edgar E. Iglesias | |
69 | c227f099 | Anthony Liguori | static inline unsigned int timer_from_addr(target_phys_addr_t addr) |
70 | 388f60b1 | Edgar E. Iglesias | { |
71 | 388f60b1 | Edgar E. Iglesias | /* Timers get a 4x32bit control reg area each. */
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72 | 388f60b1 | Edgar E. Iglesias | return addr >> 2; |
73 | 388f60b1 | Edgar E. Iglesias | } |
74 | 388f60b1 | Edgar E. Iglesias | |
75 | 388f60b1 | Edgar E. Iglesias | static void timer_update_irq(struct timerblock *t) |
76 | 388f60b1 | Edgar E. Iglesias | { |
77 | 388f60b1 | Edgar E. Iglesias | unsigned int i, irq = 0; |
78 | 388f60b1 | Edgar E. Iglesias | uint32_t csr; |
79 | 388f60b1 | Edgar E. Iglesias | |
80 | 388f60b1 | Edgar E. Iglesias | for (i = 0; i < t->nr_timers; i++) { |
81 | 388f60b1 | Edgar E. Iglesias | csr = t->timers[i].regs[R_TCSR]; |
82 | 388f60b1 | Edgar E. Iglesias | irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT); |
83 | 388f60b1 | Edgar E. Iglesias | } |
84 | 388f60b1 | Edgar E. Iglesias | |
85 | 388f60b1 | Edgar E. Iglesias | /* All timers within the same slave share a single IRQ line. */
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86 | 388f60b1 | Edgar E. Iglesias | qemu_set_irq(t->irq, !!irq); |
87 | 388f60b1 | Edgar E. Iglesias | } |
88 | 388f60b1 | Edgar E. Iglesias | |
89 | c227f099 | Anthony Liguori | static uint32_t timer_readl (void *opaque, target_phys_addr_t addr) |
90 | 388f60b1 | Edgar E. Iglesias | { |
91 | 388f60b1 | Edgar E. Iglesias | struct timerblock *t = opaque;
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92 | 388f60b1 | Edgar E. Iglesias | struct xlx_timer *xt;
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93 | 388f60b1 | Edgar E. Iglesias | uint32_t r = 0;
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94 | 388f60b1 | Edgar E. Iglesias | unsigned int timer; |
95 | 388f60b1 | Edgar E. Iglesias | |
96 | 388f60b1 | Edgar E. Iglesias | addr >>= 2;
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97 | 388f60b1 | Edgar E. Iglesias | timer = timer_from_addr(addr); |
98 | 388f60b1 | Edgar E. Iglesias | xt = &t->timers[timer]; |
99 | 388f60b1 | Edgar E. Iglesias | /* Further decoding to address a specific timers reg. */
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100 | 388f60b1 | Edgar E. Iglesias | addr &= 0x3;
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101 | 388f60b1 | Edgar E. Iglesias | switch (addr)
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102 | 388f60b1 | Edgar E. Iglesias | { |
103 | 388f60b1 | Edgar E. Iglesias | case R_TCR:
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104 | 388f60b1 | Edgar E. Iglesias | r = ptimer_get_count(xt->ptimer); |
105 | 388f60b1 | Edgar E. Iglesias | if (!(xt->regs[R_TCSR] & TCSR_UDT))
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106 | 388f60b1 | Edgar E. Iglesias | r = ~r; |
107 | 388f60b1 | Edgar E. Iglesias | D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
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108 | 388f60b1 | Edgar E. Iglesias | timer, r, xt->regs[R_TCSR] & TCSR_UDT)); |
109 | 388f60b1 | Edgar E. Iglesias | break;
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110 | 388f60b1 | Edgar E. Iglesias | default:
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111 | 388f60b1 | Edgar E. Iglesias | if (addr < ARRAY_SIZE(xt->regs))
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112 | 388f60b1 | Edgar E. Iglesias | r = xt->regs[addr]; |
113 | 388f60b1 | Edgar E. Iglesias | break;
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114 | 388f60b1 | Edgar E. Iglesias | |
115 | 388f60b1 | Edgar E. Iglesias | } |
116 | 388f60b1 | Edgar E. Iglesias | D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r)); |
117 | 388f60b1 | Edgar E. Iglesias | return r;
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118 | 388f60b1 | Edgar E. Iglesias | } |
119 | 388f60b1 | Edgar E. Iglesias | |
120 | 388f60b1 | Edgar E. Iglesias | static void timer_enable(struct xlx_timer *xt) |
121 | 388f60b1 | Edgar E. Iglesias | { |
122 | 388f60b1 | Edgar E. Iglesias | uint64_t count; |
123 | 388f60b1 | Edgar E. Iglesias | |
124 | 388f60b1 | Edgar E. Iglesias | D(printf("%s timer=%d down=%d\n", __func__,
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125 | 388f60b1 | Edgar E. Iglesias | xt->nr, xt->regs[R_TCSR] & TCSR_UDT)); |
126 | 388f60b1 | Edgar E. Iglesias | |
127 | 388f60b1 | Edgar E. Iglesias | ptimer_stop(xt->ptimer); |
128 | 388f60b1 | Edgar E. Iglesias | |
129 | 388f60b1 | Edgar E. Iglesias | if (xt->regs[R_TCSR] & TCSR_UDT)
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130 | 388f60b1 | Edgar E. Iglesias | count = xt->regs[R_TLR]; |
131 | 388f60b1 | Edgar E. Iglesias | else
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132 | 388f60b1 | Edgar E. Iglesias | count = ~0 - xt->regs[R_TLR];
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133 | 388f60b1 | Edgar E. Iglesias | ptimer_set_count(xt->ptimer, count); |
134 | 388f60b1 | Edgar E. Iglesias | ptimer_run(xt->ptimer, 1);
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135 | 388f60b1 | Edgar E. Iglesias | } |
136 | 388f60b1 | Edgar E. Iglesias | |
137 | 388f60b1 | Edgar E. Iglesias | static void |
138 | c227f099 | Anthony Liguori | timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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139 | 388f60b1 | Edgar E. Iglesias | { |
140 | 388f60b1 | Edgar E. Iglesias | struct timerblock *t = opaque;
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141 | 388f60b1 | Edgar E. Iglesias | struct xlx_timer *xt;
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142 | 388f60b1 | Edgar E. Iglesias | unsigned int timer; |
143 | 388f60b1 | Edgar E. Iglesias | |
144 | 388f60b1 | Edgar E. Iglesias | addr >>= 2;
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145 | 388f60b1 | Edgar E. Iglesias | timer = timer_from_addr(addr); |
146 | 388f60b1 | Edgar E. Iglesias | xt = &t->timers[timer]; |
147 | 388f60b1 | Edgar E. Iglesias | D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
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148 | 388f60b1 | Edgar E. Iglesias | __func__, addr * 4, value, timer, addr & 3)); |
149 | 388f60b1 | Edgar E. Iglesias | /* Further decoding to address a specific timers reg. */
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150 | 388f60b1 | Edgar E. Iglesias | addr &= 3;
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151 | 388f60b1 | Edgar E. Iglesias | switch (addr)
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152 | 388f60b1 | Edgar E. Iglesias | { |
153 | 388f60b1 | Edgar E. Iglesias | case R_TCSR:
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154 | 388f60b1 | Edgar E. Iglesias | if (value & TCSR_TINT)
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155 | 388f60b1 | Edgar E. Iglesias | value &= ~TCSR_TINT; |
156 | 388f60b1 | Edgar E. Iglesias | |
157 | 388f60b1 | Edgar E. Iglesias | xt->regs[addr] = value; |
158 | 388f60b1 | Edgar E. Iglesias | if (value & TCSR_ENT)
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159 | 388f60b1 | Edgar E. Iglesias | timer_enable(xt); |
160 | 388f60b1 | Edgar E. Iglesias | break;
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161 | 388f60b1 | Edgar E. Iglesias | |
162 | 388f60b1 | Edgar E. Iglesias | default:
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163 | 388f60b1 | Edgar E. Iglesias | if (addr < ARRAY_SIZE(xt->regs))
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164 | 388f60b1 | Edgar E. Iglesias | xt->regs[addr] = value; |
165 | 388f60b1 | Edgar E. Iglesias | break;
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166 | 388f60b1 | Edgar E. Iglesias | } |
167 | 388f60b1 | Edgar E. Iglesias | timer_update_irq(t); |
168 | 388f60b1 | Edgar E. Iglesias | } |
169 | 388f60b1 | Edgar E. Iglesias | |
170 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const timer_read[] = { |
171 | 388f60b1 | Edgar E. Iglesias | NULL, NULL, |
172 | 388f60b1 | Edgar E. Iglesias | &timer_readl, |
173 | 388f60b1 | Edgar E. Iglesias | }; |
174 | 388f60b1 | Edgar E. Iglesias | |
175 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const timer_write[] = { |
176 | 388f60b1 | Edgar E. Iglesias | NULL, NULL, |
177 | 388f60b1 | Edgar E. Iglesias | &timer_writel, |
178 | 388f60b1 | Edgar E. Iglesias | }; |
179 | 388f60b1 | Edgar E. Iglesias | |
180 | 388f60b1 | Edgar E. Iglesias | static void timer_hit(void *opaque) |
181 | 388f60b1 | Edgar E. Iglesias | { |
182 | 388f60b1 | Edgar E. Iglesias | struct xlx_timer *xt = opaque;
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183 | 388f60b1 | Edgar E. Iglesias | struct timerblock *t = xt->parent;
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184 | 388f60b1 | Edgar E. Iglesias | D(printf("%s %d\n", __func__, timer));
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185 | 388f60b1 | Edgar E. Iglesias | xt->regs[R_TCSR] |= TCSR_TINT; |
186 | 388f60b1 | Edgar E. Iglesias | |
187 | 388f60b1 | Edgar E. Iglesias | if (xt->regs[R_TCSR] & TCSR_ARHT)
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188 | 388f60b1 | Edgar E. Iglesias | timer_enable(xt); |
189 | 388f60b1 | Edgar E. Iglesias | timer_update_irq(t); |
190 | 388f60b1 | Edgar E. Iglesias | } |
191 | 388f60b1 | Edgar E. Iglesias | |
192 | 81a322d4 | Gerd Hoffmann | static int xilinx_timer_init(SysBusDevice *dev) |
193 | 388f60b1 | Edgar E. Iglesias | { |
194 | 388f60b1 | Edgar E. Iglesias | struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
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195 | 388f60b1 | Edgar E. Iglesias | unsigned int i; |
196 | ee6847d1 | Gerd Hoffmann | int timer_regs;
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197 | 388f60b1 | Edgar E. Iglesias | |
198 | 388f60b1 | Edgar E. Iglesias | /* All timers share a single irq line. */
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199 | 388f60b1 | Edgar E. Iglesias | sysbus_init_irq(dev, &t->irq); |
200 | 388f60b1 | Edgar E. Iglesias | |
201 | 388f60b1 | Edgar E. Iglesias | /* Init all the ptimers. */
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202 | 388f60b1 | Edgar E. Iglesias | t->timers = qemu_mallocz(sizeof t->timers[0] * t->nr_timers); |
203 | 388f60b1 | Edgar E. Iglesias | for (i = 0; i < t->nr_timers; i++) { |
204 | 388f60b1 | Edgar E. Iglesias | struct xlx_timer *xt = &t->timers[i];
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205 | 388f60b1 | Edgar E. Iglesias | |
206 | 388f60b1 | Edgar E. Iglesias | xt->parent = t; |
207 | 388f60b1 | Edgar E. Iglesias | xt->nr = i; |
208 | 388f60b1 | Edgar E. Iglesias | xt->bh = qemu_bh_new(timer_hit, xt); |
209 | 388f60b1 | Edgar E. Iglesias | xt->ptimer = ptimer_init(xt->bh); |
210 | ee6847d1 | Gerd Hoffmann | ptimer_set_freq(xt->ptimer, t->freq_hz); |
211 | 388f60b1 | Edgar E. Iglesias | } |
212 | 388f60b1 | Edgar E. Iglesias | |
213 | 1eed09cb | Avi Kivity | timer_regs = cpu_register_io_memory(timer_read, timer_write, t); |
214 | 388f60b1 | Edgar E. Iglesias | sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs);
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215 | 81a322d4 | Gerd Hoffmann | return 0; |
216 | 388f60b1 | Edgar E. Iglesias | } |
217 | 388f60b1 | Edgar E. Iglesias | |
218 | ee6847d1 | Gerd Hoffmann | static SysBusDeviceInfo xilinx_timer_info = {
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219 | ee6847d1 | Gerd Hoffmann | .init = xilinx_timer_init, |
220 | ee6847d1 | Gerd Hoffmann | .qdev.name = "xilinx,timer",
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221 | ee6847d1 | Gerd Hoffmann | .qdev.size = sizeof(struct timerblock), |
222 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
223 | ea2b7271 | Gerd Hoffmann | DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz, 0), |
224 | ea2b7271 | Gerd Hoffmann | DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0), |
225 | ea2b7271 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
226 | ee6847d1 | Gerd Hoffmann | } |
227 | ee6847d1 | Gerd Hoffmann | }; |
228 | ee6847d1 | Gerd Hoffmann | |
229 | 388f60b1 | Edgar E. Iglesias | static void xilinx_timer_register(void) |
230 | 388f60b1 | Edgar E. Iglesias | { |
231 | ee6847d1 | Gerd Hoffmann | sysbus_register_withprop(&xilinx_timer_info); |
232 | 388f60b1 | Edgar E. Iglesias | } |
233 | 388f60b1 | Edgar E. Iglesias | |
234 | 388f60b1 | Edgar E. Iglesias | device_init(xilinx_timer_register) |