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/*
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* Texas Instruments OMAP processors.
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*
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* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef hw_omap_h
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# define hw_omap_h "omap.h" |
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# define OMAP_EMIFS_BASE 0x00000000 |
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# define OMAP_CS0_BASE 0x00000000 |
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# define OMAP_CS1_BASE 0x04000000 |
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# define OMAP_CS2_BASE 0x08000000 |
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# define OMAP_CS3_BASE 0x0c000000 |
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# define OMAP_EMIFF_BASE 0x10000000 |
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# define OMAP_IMIF_BASE 0x20000000 |
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# define OMAP_LOCALBUS_BASE 0x30000000 |
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# define OMAP_MPUI_BASE 0xe1000000 |
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# define OMAP730_SRAM_SIZE 0x00032000 |
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# define OMAP15XX_SRAM_SIZE 0x00030000 |
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# define OMAP16XX_SRAM_SIZE 0x00004000 |
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# define OMAP1611_SRAM_SIZE 0x0003e800 |
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# define OMAP_CS0_SIZE 0x04000000 |
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# define OMAP_CS1_SIZE 0x04000000 |
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# define OMAP_CS2_SIZE 0x04000000 |
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# define OMAP_CS3_SIZE 0x04000000 |
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/* omap1_clk.c */
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struct omap_mpu_state_s;
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typedef struct clk *omap_clk; |
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omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); |
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void omap_clk_init(struct omap_mpu_state_s *mpu); |
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void omap_clk_adduser(struct clk *clk, qemu_irq user); |
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void omap_clk_get(omap_clk clk);
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void omap_clk_put(omap_clk clk);
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void omap_clk_onoff(omap_clk clk, int on); |
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void omap_clk_canidle(omap_clk clk, int can); |
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void omap_clk_setrate(omap_clk clk, int divide, int multiply); |
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int64_t omap_clk_getrate(omap_clk clk); |
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void omap_clk_reparent(omap_clk clk, omap_clk parent);
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/* omap[123].c */
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struct omap_intr_handler_s;
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struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
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unsigned long size, unsigned char nbanks, |
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qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk); |
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struct omap_target_agent_s;
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static inline target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, |
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int region, int iotype) { return 0; } |
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/*
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* Common IRQ numbers for level 1 interrupt handler
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* See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
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*/
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# define OMAP_INT_CAMERA 1 |
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# define OMAP_INT_FIQ 3 |
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# define OMAP_INT_RTDX 6 |
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# define OMAP_INT_DSP_MMU_ABORT 7 |
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# define OMAP_INT_HOST 8 |
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# define OMAP_INT_ABORT 9 |
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# define OMAP_INT_BRIDGE_PRIV 13 |
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# define OMAP_INT_GPIO_BANK1 14 |
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# define OMAP_INT_UART3 15 |
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# define OMAP_INT_TIMER3 16 |
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# define OMAP_INT_DMA_CH0_6 19 |
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# define OMAP_INT_DMA_CH1_7 20 |
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# define OMAP_INT_DMA_CH2_8 21 |
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# define OMAP_INT_DMA_CH3 22 |
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# define OMAP_INT_DMA_CH4 23 |
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# define OMAP_INT_DMA_CH5 24 |
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# define OMAP_INT_DMA_LCD 25 |
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# define OMAP_INT_TIMER1 26 |
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# define OMAP_INT_WD_TIMER 27 |
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# define OMAP_INT_BRIDGE_PUB 28 |
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# define OMAP_INT_TIMER2 30 |
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# define OMAP_INT_LCD_CTRL 31 |
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/*
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* Common OMAP-15xx IRQ numbers for level 1 interrupt handler
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*/
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# define OMAP_INT_15XX_IH2_IRQ 0 |
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# define OMAP_INT_15XX_LB_MMU 17 |
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# define OMAP_INT_15XX_LOCAL_BUS 29 |
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/*
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* OMAP-1510 specific IRQ numbers for level 1 interrupt handler
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*/
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# define OMAP_INT_1510_SPI_TX 4 |
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# define OMAP_INT_1510_SPI_RX 5 |
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# define OMAP_INT_1510_DSP_MAILBOX1 10 |
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# define OMAP_INT_1510_DSP_MAILBOX2 11 |
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/*
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* OMAP-310 specific IRQ numbers for level 1 interrupt handler
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*/
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# define OMAP_INT_310_McBSP2_TX 4 |
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# define OMAP_INT_310_McBSP2_RX 5 |
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# define OMAP_INT_310_HSB_MAILBOX1 12 |
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# define OMAP_INT_310_HSAB_MMU 18 |
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/*
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* OMAP-1610 specific IRQ numbers for level 1 interrupt handler
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*/
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# define OMAP_INT_1610_IH2_IRQ 0 |
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# define OMAP_INT_1610_IH2_FIQ 2 |
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# define OMAP_INT_1610_McBSP2_TX 4 |
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# define OMAP_INT_1610_McBSP2_RX 5 |
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# define OMAP_INT_1610_DSP_MAILBOX1 10 |
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# define OMAP_INT_1610_DSP_MAILBOX2 11 |
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# define OMAP_INT_1610_LCD_LINE 12 |
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# define OMAP_INT_1610_GPTIMER1 17 |
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# define OMAP_INT_1610_GPTIMER2 18 |
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# define OMAP_INT_1610_SSR_FIFO_0 29 |
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/*
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* OMAP-730 specific IRQ numbers for level 1 interrupt handler
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*/
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# define OMAP_INT_730_IH2_FIQ 0 |
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# define OMAP_INT_730_IH2_IRQ 1 |
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# define OMAP_INT_730_USB_NON_ISO 2 |
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# define OMAP_INT_730_USB_ISO 3 |
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# define OMAP_INT_730_ICR 4 |
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# define OMAP_INT_730_EAC 5 |
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# define OMAP_INT_730_GPIO_BANK1 6 |
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# define OMAP_INT_730_GPIO_BANK2 7 |
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# define OMAP_INT_730_GPIO_BANK3 8 |
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# define OMAP_INT_730_McBSP2TX 10 |
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# define OMAP_INT_730_McBSP2RX 11 |
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# define OMAP_INT_730_McBSP2RX_OVF 12 |
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# define OMAP_INT_730_LCD_LINE 14 |
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# define OMAP_INT_730_GSM_PROTECT 15 |
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# define OMAP_INT_730_TIMER3 16 |
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# define OMAP_INT_730_GPIO_BANK5 17 |
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# define OMAP_INT_730_GPIO_BANK6 18 |
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# define OMAP_INT_730_SPGIO_WR 29 |
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/*
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* Common IRQ numbers for level 2 interrupt handler
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*/
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# define OMAP_INT_KEYBOARD 1 |
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# define OMAP_INT_uWireTX 2 |
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# define OMAP_INT_uWireRX 3 |
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# define OMAP_INT_I2C 4 |
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# define OMAP_INT_MPUIO 5 |
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# define OMAP_INT_USB_HHC_1 6 |
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# define OMAP_INT_McBSP3TX 10 |
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# define OMAP_INT_McBSP3RX 11 |
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# define OMAP_INT_McBSP1TX 12 |
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# define OMAP_INT_McBSP1RX 13 |
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# define OMAP_INT_UART1 14 |
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# define OMAP_INT_UART2 15 |
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# define OMAP_INT_USB_W2FC 20 |
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# define OMAP_INT_1WIRE 21 |
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# define OMAP_INT_OS_TIMER 22 |
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# define OMAP_INT_OQN 23 |
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# define OMAP_INT_GAUGE_32K 24 |
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# define OMAP_INT_RTC_TIMER 25 |
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# define OMAP_INT_RTC_ALARM 26 |
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# define OMAP_INT_DSP_MMU 28 |
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/*
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* OMAP-1510 specific IRQ numbers for level 2 interrupt handler
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*/
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# define OMAP_INT_1510_BT_MCSI1TX 16 |
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# define OMAP_INT_1510_BT_MCSI1RX 17 |
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# define OMAP_INT_1510_SoSSI_MATCH 19 |
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# define OMAP_INT_1510_MEM_STICK 27 |
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# define OMAP_INT_1510_COM_SPI_RO 31 |
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/*
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* OMAP-310 specific IRQ numbers for level 2 interrupt handler
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*/
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# define OMAP_INT_310_FAC 0 |
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# define OMAP_INT_310_USB_HHC_2 7 |
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# define OMAP_INT_310_MCSI1_FE 16 |
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# define OMAP_INT_310_MCSI2_FE 17 |
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# define OMAP_INT_310_USB_W2FC_ISO 29 |
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# define OMAP_INT_310_USB_W2FC_NON_ISO 30 |
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# define OMAP_INT_310_McBSP2RX_OF 31 |
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/*
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* OMAP-1610 specific IRQ numbers for level 2 interrupt handler
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*/
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# define OMAP_INT_1610_FAC 0 |
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# define OMAP_INT_1610_USB_HHC_2 7 |
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# define OMAP_INT_1610_USB_OTG 8 |
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# define OMAP_INT_1610_SoSSI 9 |
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# define OMAP_INT_1610_BT_MCSI1TX 16 |
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# define OMAP_INT_1610_BT_MCSI1RX 17 |
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# define OMAP_INT_1610_SoSSI_MATCH 19 |
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# define OMAP_INT_1610_MEM_STICK 27 |
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# define OMAP_INT_1610_McBSP2RX_OF 31 |
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# define OMAP_INT_1610_STI 32 |
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# define OMAP_INT_1610_STI_WAKEUP 33 |
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# define OMAP_INT_1610_GPTIMER3 34 |
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# define OMAP_INT_1610_GPTIMER4 35 |
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# define OMAP_INT_1610_GPTIMER5 36 |
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# define OMAP_INT_1610_GPTIMER6 37 |
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# define OMAP_INT_1610_GPTIMER7 38 |
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# define OMAP_INT_1610_GPTIMER8 39 |
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# define OMAP_INT_1610_GPIO_BANK2 40 |
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# define OMAP_INT_1610_GPIO_BANK3 41 |
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# define OMAP_INT_1610_MMC2 42 |
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# define OMAP_INT_1610_CF 43 |
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# define OMAP_INT_1610_WAKE_UP_REQ 46 |
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# define OMAP_INT_1610_GPIO_BANK4 48 |
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# define OMAP_INT_1610_SPI 49 |
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# define OMAP_INT_1610_DMA_CH6 53 |
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# define OMAP_INT_1610_DMA_CH7 54 |
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# define OMAP_INT_1610_DMA_CH8 55 |
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# define OMAP_INT_1610_DMA_CH9 56 |
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# define OMAP_INT_1610_DMA_CH10 57 |
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# define OMAP_INT_1610_DMA_CH11 58 |
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# define OMAP_INT_1610_DMA_CH12 59 |
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# define OMAP_INT_1610_DMA_CH13 60 |
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# define OMAP_INT_1610_DMA_CH14 61 |
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# define OMAP_INT_1610_DMA_CH15 62 |
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# define OMAP_INT_1610_NAND 63 |
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/*
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* OMAP-730 specific IRQ numbers for level 2 interrupt handler
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*/
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# define OMAP_INT_730_HW_ERRORS 0 |
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# define OMAP_INT_730_NFIQ_PWR_FAIL 1 |
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# define OMAP_INT_730_CFCD 2 |
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# define OMAP_INT_730_CFIREQ 3 |
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# define OMAP_INT_730_I2C 4 |
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# define OMAP_INT_730_PCC 5 |
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# define OMAP_INT_730_MPU_EXT_NIRQ 6 |
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# define OMAP_INT_730_SPI_100K_1 7 |
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# define OMAP_INT_730_SYREN_SPI 8 |
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# define OMAP_INT_730_VLYNQ 9 |
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# define OMAP_INT_730_GPIO_BANK4 10 |
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# define OMAP_INT_730_McBSP1TX 11 |
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# define OMAP_INT_730_McBSP1RX 12 |
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# define OMAP_INT_730_McBSP1RX_OF 13 |
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# define OMAP_INT_730_UART_MODEM_IRDA_2 14 |
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# define OMAP_INT_730_UART_MODEM_1 15 |
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# define OMAP_INT_730_MCSI 16 |
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# define OMAP_INT_730_uWireTX 17 |
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# define OMAP_INT_730_uWireRX 18 |
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# define OMAP_INT_730_SMC_CD 19 |
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# define OMAP_INT_730_SMC_IREQ 20 |
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# define OMAP_INT_730_HDQ_1WIRE 21 |
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# define OMAP_INT_730_TIMER32K 22 |
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# define OMAP_INT_730_MMC_SDIO 23 |
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# define OMAP_INT_730_UPLD 24 |
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# define OMAP_INT_730_USB_HHC_1 27 |
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# define OMAP_INT_730_USB_HHC_2 28 |
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# define OMAP_INT_730_USB_GENI 29 |
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# define OMAP_INT_730_USB_OTG 30 |
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# define OMAP_INT_730_CAMERA_IF 31 |
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# define OMAP_INT_730_RNG 32 |
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# define OMAP_INT_730_DUAL_MODE_TIMER 33 |
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# define OMAP_INT_730_DBB_RF_EN 34 |
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# define OMAP_INT_730_MPUIO_KEYPAD 35 |
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# define OMAP_INT_730_SHA1_MD5 36 |
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# define OMAP_INT_730_SPI_100K_2 37 |
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# define OMAP_INT_730_RNG_IDLE 38 |
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# define OMAP_INT_730_MPUIO 39 |
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# define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 |
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# define OMAP_INT_730_LLPC_OE_FALLING 41 |
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# define OMAP_INT_730_LLPC_OE_RISING 42 |
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# define OMAP_INT_730_LLPC_VSYNC 43 |
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# define OMAP_INT_730_WAKE_UP_REQ 46 |
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# define OMAP_INT_730_DMA_CH6 53 |
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# define OMAP_INT_730_DMA_CH7 54 |
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# define OMAP_INT_730_DMA_CH8 55 |
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# define OMAP_INT_730_DMA_CH9 56 |
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# define OMAP_INT_730_DMA_CH10 57 |
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# define OMAP_INT_730_DMA_CH11 58 |
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# define OMAP_INT_730_DMA_CH12 59 |
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# define OMAP_INT_730_DMA_CH13 60 |
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# define OMAP_INT_730_DMA_CH14 61 |
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# define OMAP_INT_730_DMA_CH15 62 |
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# define OMAP_INT_730_NAND 63 |
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|
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/*
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* OMAP-24xx common IRQ numbers
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*/
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# define OMAP_INT_24XX_SYS_NIRQ 7 |
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# define OMAP_INT_24XX_SDMA_IRQ0 12 |
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# define OMAP_INT_24XX_SDMA_IRQ1 13 |
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# define OMAP_INT_24XX_SDMA_IRQ2 14 |
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# define OMAP_INT_24XX_SDMA_IRQ3 15 |
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# define OMAP_INT_24XX_CAM_IRQ 24 |
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# define OMAP_INT_24XX_DSS_IRQ 25 |
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# define OMAP_INT_24XX_MAIL_U0_MPU 26 |
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# define OMAP_INT_24XX_DSP_UMA 27 |
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# define OMAP_INT_24XX_DSP_MMU 28 |
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# define OMAP_INT_24XX_GPIO_BANK1 29 |
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# define OMAP_INT_24XX_GPIO_BANK2 30 |
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# define OMAP_INT_24XX_GPIO_BANK3 31 |
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# define OMAP_INT_24XX_GPIO_BANK4 32 |
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# define OMAP_INT_24XX_GPIO_BANK5 33 |
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# define OMAP_INT_24XX_MAIL_U3_MPU 34 |
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# define OMAP_INT_24XX_GPTIMER1 37 |
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# define OMAP_INT_24XX_GPTIMER2 38 |
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# define OMAP_INT_24XX_GPTIMER3 39 |
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# define OMAP_INT_24XX_GPTIMER4 40 |
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# define OMAP_INT_24XX_GPTIMER5 41 |
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# define OMAP_INT_24XX_GPTIMER6 42 |
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# define OMAP_INT_24XX_GPTIMER7 43 |
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# define OMAP_INT_24XX_GPTIMER8 44 |
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# define OMAP_INT_24XX_GPTIMER9 45 |
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# define OMAP_INT_24XX_GPTIMER10 46 |
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# define OMAP_INT_24XX_GPTIMER11 47 |
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# define OMAP_INT_24XX_GPTIMER12 48 |
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# define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 |
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# define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 |
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# define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 |
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# define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 |
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# define OMAP_INT_24XX_UART1_IRQ 72 |
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# define OMAP_INT_24XX_UART2_IRQ 73 |
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# define OMAP_INT_24XX_UART3_IRQ 74 |
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# define OMAP_INT_24XX_USB_IRQ_GEN 75 |
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# define OMAP_INT_24XX_USB_IRQ_NISO 76 |
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# define OMAP_INT_24XX_USB_IRQ_ISO 77 |
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# define OMAP_INT_24XX_USB_IRQ_HGEN 78 |
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# define OMAP_INT_24XX_USB_IRQ_HSOF 79 |
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# define OMAP_INT_24XX_USB_IRQ_OTG 80 |
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# define OMAP_INT_24XX_MMC_IRQ 83 |
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# define OMAP_INT_243X_HS_USB_MC 92 |
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# define OMAP_INT_243X_HS_USB_DMA 93 |
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# define OMAP_INT_243X_CARKIT 94 |
342 |
|
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/* omap_dma.c */
|
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enum omap_dma_model {
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omap_dma_3_0, |
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omap_dma_3_1, |
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omap_dma_3_2, |
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omap_dma_4, |
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}; |
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|
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struct omap_dma_s;
|
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struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
|
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qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
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enum omap_dma_model model);
|
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void omap_dma_reset(struct omap_dma_s *s); |
356 |
|
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struct dma_irq_map {
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int ih;
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int intr;
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}; |
361 |
|
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/* Only used in OMAP DMA 3.x gigacells */
|
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enum omap_dma_port {
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emiff = 0,
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emifs, |
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imif, /* omap16xx: ocp_t1 */
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tipb, |
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local, /* omap16xx: ocp_t2 */
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tipb_mpui, |
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omap_dma_port_last, |
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}; |
372 |
|
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typedef enum { |
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constant = 0,
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post_incremented, |
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single_index, |
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double_index, |
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} omap_dma_addressing_t; |
379 |
|
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/* Only used in OMAP DMA 3.x gigacells */
|
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struct omap_dma_lcd_channel_s {
|
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enum omap_dma_port src;
|
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target_phys_addr_t src_f1_top; |
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target_phys_addr_t src_f1_bottom; |
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target_phys_addr_t src_f2_top; |
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target_phys_addr_t src_f2_bottom; |
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|
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/* Used in OMAP DMA 3.2 gigacell */
|
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unsigned char brust_f1; |
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unsigned char pack_f1; |
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unsigned char data_type_f1; |
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unsigned char brust_f2; |
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unsigned char pack_f2; |
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unsigned char data_type_f2; |
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unsigned char end_prog; |
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unsigned char repeat; |
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unsigned char auto_init; |
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unsigned char priority; |
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unsigned char fs; |
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unsigned char running; |
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unsigned char bs; |
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unsigned char omap_3_1_compatible_disable; |
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unsigned char dst; |
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unsigned char lch_type; |
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int16_t element_index_f1; |
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int16_t element_index_f2; |
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int32_t frame_index_f1; |
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int32_t frame_index_f2; |
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uint16_t elements_f1; |
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uint16_t frames_f1; |
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uint16_t elements_f2; |
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uint16_t frames_f2; |
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omap_dma_addressing_t mode_f1; |
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omap_dma_addressing_t mode_f2; |
415 |
|
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/* Destination port is fixed. */
|
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int interrupts;
|
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int condition;
|
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int dual;
|
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|
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int current_frame;
|
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ram_addr_t phys_framebuffer[2];
|
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qemu_irq irq; |
424 |
struct omap_mpu_state_s *mpu;
|
425 |
} *omap_dma_get_lcdch(struct omap_dma_s *s);
|
426 |
|
427 |
/*
|
428 |
* DMA request numbers for OMAP1
|
429 |
* See /usr/include/asm-arm/arch-omap/dma.h in Linux.
|
430 |
*/
|
431 |
# define OMAP_DMA_NO_DEVICE 0 |
432 |
# define OMAP_DMA_MCSI1_TX 1 |
433 |
# define OMAP_DMA_MCSI1_RX 2 |
434 |
# define OMAP_DMA_I2C_RX 3 |
435 |
# define OMAP_DMA_I2C_TX 4 |
436 |
# define OMAP_DMA_EXT_NDMA_REQ0 5 |
437 |
# define OMAP_DMA_EXT_NDMA_REQ1 6 |
438 |
# define OMAP_DMA_UWIRE_TX 7 |
439 |
# define OMAP_DMA_MCBSP1_TX 8 |
440 |
# define OMAP_DMA_MCBSP1_RX 9 |
441 |
# define OMAP_DMA_MCBSP3_TX 10 |
442 |
# define OMAP_DMA_MCBSP3_RX 11 |
443 |
# define OMAP_DMA_UART1_TX 12 |
444 |
# define OMAP_DMA_UART1_RX 13 |
445 |
# define OMAP_DMA_UART2_TX 14 |
446 |
# define OMAP_DMA_UART2_RX 15 |
447 |
# define OMAP_DMA_MCBSP2_TX 16 |
448 |
# define OMAP_DMA_MCBSP2_RX 17 |
449 |
# define OMAP_DMA_UART3_TX 18 |
450 |
# define OMAP_DMA_UART3_RX 19 |
451 |
# define OMAP_DMA_CAMERA_IF_RX 20 |
452 |
# define OMAP_DMA_MMC_TX 21 |
453 |
# define OMAP_DMA_MMC_RX 22 |
454 |
# define OMAP_DMA_NAND 23 /* Not in OMAP310 */ |
455 |
# define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ |
456 |
# define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ |
457 |
# define OMAP_DMA_USB_W2FC_RX0 26 |
458 |
# define OMAP_DMA_USB_W2FC_RX1 27 |
459 |
# define OMAP_DMA_USB_W2FC_RX2 28 |
460 |
# define OMAP_DMA_USB_W2FC_TX0 29 |
461 |
# define OMAP_DMA_USB_W2FC_TX1 30 |
462 |
# define OMAP_DMA_USB_W2FC_TX2 31 |
463 |
|
464 |
/* These are only for 1610 */
|
465 |
# define OMAP_DMA_CRYPTO_DES_IN 32 |
466 |
# define OMAP_DMA_SPI_TX 33 |
467 |
# define OMAP_DMA_SPI_RX 34 |
468 |
# define OMAP_DMA_CRYPTO_HASH 35 |
469 |
# define OMAP_DMA_CCP_ATTN 36 |
470 |
# define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 |
471 |
# define OMAP_DMA_CMT_APE_TX_CHAN_0 38 |
472 |
# define OMAP_DMA_CMT_APE_RV_CHAN_0 39 |
473 |
# define OMAP_DMA_CMT_APE_TX_CHAN_1 40 |
474 |
# define OMAP_DMA_CMT_APE_RV_CHAN_1 41 |
475 |
# define OMAP_DMA_CMT_APE_TX_CHAN_2 42 |
476 |
# define OMAP_DMA_CMT_APE_RV_CHAN_2 43 |
477 |
# define OMAP_DMA_CMT_APE_TX_CHAN_3 44 |
478 |
# define OMAP_DMA_CMT_APE_RV_CHAN_3 45 |
479 |
# define OMAP_DMA_CMT_APE_TX_CHAN_4 46 |
480 |
# define OMAP_DMA_CMT_APE_RV_CHAN_4 47 |
481 |
# define OMAP_DMA_CMT_APE_TX_CHAN_5 48 |
482 |
# define OMAP_DMA_CMT_APE_RV_CHAN_5 49 |
483 |
# define OMAP_DMA_CMT_APE_TX_CHAN_6 50 |
484 |
# define OMAP_DMA_CMT_APE_RV_CHAN_6 51 |
485 |
# define OMAP_DMA_CMT_APE_TX_CHAN_7 52 |
486 |
# define OMAP_DMA_CMT_APE_RV_CHAN_7 53 |
487 |
# define OMAP_DMA_MMC2_TX 54 |
488 |
# define OMAP_DMA_MMC2_RX 55 |
489 |
# define OMAP_DMA_CRYPTO_DES_OUT 56 |
490 |
|
491 |
/* omap[123].c */
|
492 |
struct omap_mpu_timer_s;
|
493 |
struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
|
494 |
qemu_irq irq, omap_clk clk); |
495 |
|
496 |
struct omap_watchdog_timer_s;
|
497 |
struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
|
498 |
qemu_irq irq, omap_clk clk); |
499 |
|
500 |
struct omap_32khz_timer_s;
|
501 |
struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
|
502 |
qemu_irq irq, omap_clk clk); |
503 |
|
504 |
struct omap_tipb_bridge_s;
|
505 |
struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
|
506 |
qemu_irq abort_irq, omap_clk clk); |
507 |
|
508 |
struct omap_uart_s;
|
509 |
struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
|
510 |
qemu_irq irq, omap_clk clk, CharDriverState *chr); |
511 |
|
512 |
struct omap_mpuio_s;
|
513 |
struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
|
514 |
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
515 |
omap_clk clk); |
516 |
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
|
517 |
void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); |
518 |
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); |
519 |
|
520 |
struct omap_gpio_s;
|
521 |
struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
|
522 |
qemu_irq irq, omap_clk clk); |
523 |
qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
|
524 |
void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler); |
525 |
|
526 |
struct uwire_slave_s {
|
527 |
uint16_t (*receive)(void *opaque);
|
528 |
void (*send)(void *opaque, uint16_t data); |
529 |
void *opaque;
|
530 |
}; |
531 |
struct omap_uwire_s;
|
532 |
struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
533 |
qemu_irq *irq, qemu_irq dma, omap_clk clk); |
534 |
void omap_uwire_attach(struct omap_uwire_s *s, |
535 |
struct uwire_slave_s *slave, int chipselect); |
536 |
|
537 |
struct omap_rtc_s;
|
538 |
struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
|
539 |
qemu_irq *irq, omap_clk clk); |
540 |
|
541 |
struct i2s_codec_s {
|
542 |
void *opaque;
|
543 |
|
544 |
/* The CPU can call this if it is generating the clock signal on the
|
545 |
* i2s port. The CODEC can ignore it if it is set up as a clock
|
546 |
* master and generates its own clock. */
|
547 |
void (*set_rate)(void *opaque, int in, int out); |
548 |
|
549 |
void (*tx_swallow)(void *opaque); |
550 |
qemu_irq rx_swallow; |
551 |
qemu_irq tx_start; |
552 |
|
553 |
int tx_rate;
|
554 |
int cts;
|
555 |
int rx_rate;
|
556 |
int rts;
|
557 |
|
558 |
struct i2s_fifo_s {
|
559 |
uint8_t *fifo; |
560 |
int len;
|
561 |
int start;
|
562 |
int size;
|
563 |
} in, out; |
564 |
}; |
565 |
struct omap_mcbsp_s;
|
566 |
struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
|
567 |
qemu_irq *irq, qemu_irq *dma, omap_clk clk); |
568 |
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave); |
569 |
|
570 |
struct omap_lpg_s;
|
571 |
struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
|
572 |
|
573 |
/* omap_lcdc.c */
|
574 |
struct omap_lcd_panel_s;
|
575 |
void omap_lcdc_reset(struct omap_lcd_panel_s *s); |
576 |
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
|
577 |
struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
|
578 |
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk); |
579 |
|
580 |
/* omap_mmc.c */
|
581 |
struct omap_mmc_s;
|
582 |
struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
|
583 |
BlockDriverState *bd, |
584 |
qemu_irq irq, qemu_irq dma[], omap_clk clk); |
585 |
void omap_mmc_reset(struct omap_mmc_s *s); |
586 |
void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); |
587 |
|
588 |
/* omap_i2c.c */
|
589 |
struct omap_i2c_s;
|
590 |
struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
|
591 |
qemu_irq irq, qemu_irq *dma, omap_clk clk); |
592 |
struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, |
593 |
qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk); |
594 |
void omap_i2c_reset(struct omap_i2c_s *s); |
595 |
i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
|
596 |
|
597 |
# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
|
598 |
# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
|
599 |
# define cpu_is_omap15xx(cpu) \
|
600 |
(cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) |
601 |
# define cpu_class_omap1(cpu) 1 |
602 |
|
603 |
struct omap_mpu_state_s {
|
604 |
enum omap1_mpu_model {
|
605 |
omap310, |
606 |
omap1510, |
607 |
} mpu_model; |
608 |
|
609 |
CPUState *env; |
610 |
|
611 |
qemu_irq *irq[2];
|
612 |
qemu_irq *drq; |
613 |
|
614 |
qemu_irq wakeup; |
615 |
|
616 |
struct omap_dma_port_if_s {
|
617 |
uint32_t (*read[3])(struct omap_mpu_state_s *s, |
618 |
target_phys_addr_t offset); |
619 |
void (*write[3])(struct omap_mpu_state_s *s, |
620 |
target_phys_addr_t offset, uint32_t value); |
621 |
int (*addr_valid)(struct omap_mpu_state_s *s, |
622 |
target_phys_addr_t addr); |
623 |
} port[omap_dma_port_last]; |
624 |
|
625 |
unsigned long sdram_size; |
626 |
unsigned long sram_size; |
627 |
|
628 |
/* MPUI-TIPB peripherals */
|
629 |
struct omap_uart_s *uart[3]; |
630 |
|
631 |
struct omap_gpio_s *gpio;
|
632 |
|
633 |
struct omap_mcbsp_s *mcbsp1;
|
634 |
struct omap_mcbsp_s *mcbsp3;
|
635 |
|
636 |
/* MPU public TIPB peripherals */
|
637 |
struct omap_32khz_timer_s *os_timer;
|
638 |
|
639 |
struct omap_mmc_s *mmc;
|
640 |
|
641 |
struct omap_mpuio_s *mpuio;
|
642 |
|
643 |
struct omap_uwire_s *microwire;
|
644 |
|
645 |
struct {
|
646 |
uint8_t output; |
647 |
uint8_t level; |
648 |
uint8_t enable; |
649 |
int clk;
|
650 |
} pwl; |
651 |
|
652 |
struct {
|
653 |
uint8_t frc; |
654 |
uint8_t vrc; |
655 |
uint8_t gcr; |
656 |
omap_clk clk; |
657 |
} pwt; |
658 |
|
659 |
struct omap_i2c_s *i2c;
|
660 |
|
661 |
struct omap_rtc_s *rtc;
|
662 |
|
663 |
struct omap_mcbsp_s *mcbsp2;
|
664 |
|
665 |
struct omap_lpg_s *led[2]; |
666 |
|
667 |
/* MPU private TIPB peripherals */
|
668 |
struct omap_intr_handler_s *ih[2]; |
669 |
|
670 |
struct omap_dma_s *dma;
|
671 |
|
672 |
struct omap_mpu_timer_s *timer[3]; |
673 |
struct omap_watchdog_timer_s *wdt;
|
674 |
|
675 |
struct omap_lcd_panel_s *lcd;
|
676 |
|
677 |
target_phys_addr_t ulpd_pm_base; |
678 |
uint32_t ulpd_pm_regs[21];
|
679 |
int64_t ulpd_gauge_start; |
680 |
|
681 |
target_phys_addr_t pin_cfg_base; |
682 |
uint32_t func_mux_ctrl[14];
|
683 |
uint32_t comp_mode_ctrl[1];
|
684 |
uint32_t pull_dwn_ctrl[4];
|
685 |
uint32_t gate_inh_ctrl[1];
|
686 |
uint32_t voltage_ctrl[1];
|
687 |
uint32_t test_dbg_ctrl[1];
|
688 |
uint32_t mod_conf_ctrl[1];
|
689 |
int compat1509;
|
690 |
|
691 |
uint32_t mpui_ctrl; |
692 |
target_phys_addr_t mpui_base; |
693 |
|
694 |
struct omap_tipb_bridge_s *private_tipb;
|
695 |
struct omap_tipb_bridge_s *public_tipb;
|
696 |
|
697 |
target_phys_addr_t tcmi_base; |
698 |
uint32_t tcmi_regs[17];
|
699 |
|
700 |
struct dpll_ctl_s {
|
701 |
target_phys_addr_t base; |
702 |
uint16_t mode; |
703 |
omap_clk dpll; |
704 |
} dpll[3];
|
705 |
|
706 |
omap_clk clks; |
707 |
struct {
|
708 |
target_phys_addr_t mpu_base; |
709 |
target_phys_addr_t dsp_base; |
710 |
|
711 |
int cold_start;
|
712 |
int clocking_scheme;
|
713 |
uint16_t arm_ckctl; |
714 |
uint16_t arm_idlect1; |
715 |
uint16_t arm_idlect2; |
716 |
uint16_t arm_ewupct; |
717 |
uint16_t arm_rstct1; |
718 |
uint16_t arm_rstct2; |
719 |
uint16_t arm_ckout1; |
720 |
int dpll1_mode;
|
721 |
uint16_t dsp_idlect1; |
722 |
uint16_t dsp_idlect2; |
723 |
uint16_t dsp_rstct2; |
724 |
} clkm; |
725 |
} *omap310_mpu_init(unsigned long sdram_size, |
726 |
DisplayState *ds, const char *core); |
727 |
|
728 |
# if TARGET_PHYS_ADDR_BITS == 32 |
729 |
# define OMAP_FMT_plx "%#08x" |
730 |
# elif TARGET_PHYS_ADDR_BITS == 64 |
731 |
# define OMAP_FMT_plx "%#08" PRIx64 |
732 |
# else
|
733 |
# error TARGET_PHYS_ADDR_BITS undefined
|
734 |
# endif
|
735 |
|
736 |
uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
|
737 |
void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
738 |
uint32_t value); |
739 |
uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
|
740 |
void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
741 |
uint32_t value); |
742 |
uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
|
743 |
void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
744 |
uint32_t value); |
745 |
|
746 |
# define OMAP_BAD_REG(paddr) \
|
747 |
printf("%s: Bad register " OMAP_FMT_plx "\n", __FUNCTION__, paddr) |
748 |
# define OMAP_RO_REG(paddr) \
|
749 |
printf("%s: Read-only register " OMAP_FMT_plx "\n", \ |
750 |
__FUNCTION__, paddr) |
751 |
|
752 |
# define TCMI_VERBOSE 1 |
753 |
//# define MEM_VERBOSE 1
|
754 |
|
755 |
# ifdef TCMI_VERBOSE
|
756 |
# define OMAP_8B_REG(paddr) \
|
757 |
printf("%s: 8-bit register " OMAP_FMT_plx "\n", \ |
758 |
__FUNCTION__, paddr) |
759 |
# define OMAP_16B_REG(paddr) \
|
760 |
printf("%s: 16-bit register " OMAP_FMT_plx "\n", \ |
761 |
__FUNCTION__, paddr) |
762 |
# define OMAP_32B_REG(paddr) \
|
763 |
printf("%s: 32-bit register " OMAP_FMT_plx "\n", \ |
764 |
__FUNCTION__, paddr) |
765 |
# else
|
766 |
# define OMAP_8B_REG(paddr)
|
767 |
# define OMAP_16B_REG(paddr)
|
768 |
# define OMAP_32B_REG(paddr)
|
769 |
# endif
|
770 |
|
771 |
# define OMAP_MPUI_REG_MASK 0x000007ff |
772 |
|
773 |
# ifdef MEM_VERBOSE
|
774 |
struct io_fn {
|
775 |
CPUReadMemoryFunc **mem_read; |
776 |
CPUWriteMemoryFunc **mem_write; |
777 |
void *opaque;
|
778 |
int in;
|
779 |
}; |
780 |
|
781 |
static uint32_t io_readb(void *opaque, target_phys_addr_t addr) |
782 |
{ |
783 |
struct io_fn *s = opaque;
|
784 |
uint32_t ret; |
785 |
|
786 |
s->in ++; |
787 |
ret = s->mem_read[0](s->opaque, addr);
|
788 |
s->in --; |
789 |
if (!s->in)
|
790 |
fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
|
791 |
return ret;
|
792 |
} |
793 |
static uint32_t io_readh(void *opaque, target_phys_addr_t addr) |
794 |
{ |
795 |
struct io_fn *s = opaque;
|
796 |
uint32_t ret; |
797 |
|
798 |
s->in ++; |
799 |
ret = s->mem_read[1](s->opaque, addr);
|
800 |
s->in --; |
801 |
if (!s->in)
|
802 |
fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
|
803 |
return ret;
|
804 |
} |
805 |
static uint32_t io_readw(void *opaque, target_phys_addr_t addr) |
806 |
{ |
807 |
struct io_fn *s = opaque;
|
808 |
uint32_t ret; |
809 |
|
810 |
s->in ++; |
811 |
ret = s->mem_read[2](s->opaque, addr);
|
812 |
s->in --; |
813 |
if (!s->in)
|
814 |
fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
|
815 |
return ret;
|
816 |
} |
817 |
static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) |
818 |
{ |
819 |
struct io_fn *s = opaque;
|
820 |
|
821 |
if (!s->in)
|
822 |
fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
|
823 |
s->in ++; |
824 |
s->mem_write[0](s->opaque, addr, value);
|
825 |
s->in --; |
826 |
} |
827 |
static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) |
828 |
{ |
829 |
struct io_fn *s = opaque;
|
830 |
|
831 |
if (!s->in)
|
832 |
fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
|
833 |
s->in ++; |
834 |
s->mem_write[1](s->opaque, addr, value);
|
835 |
s->in --; |
836 |
} |
837 |
static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value) |
838 |
{ |
839 |
struct io_fn *s = opaque;
|
840 |
|
841 |
if (!s->in)
|
842 |
fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
|
843 |
s->in ++; |
844 |
s->mem_write[2](s->opaque, addr, value);
|
845 |
s->in --; |
846 |
} |
847 |
|
848 |
static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
|
849 |
static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
|
850 |
|
851 |
inline static int debug_register_io_memory(int io_index, |
852 |
CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write, |
853 |
void *opaque)
|
854 |
{ |
855 |
struct io_fn *s = qemu_malloc(sizeof(struct io_fn)); |
856 |
|
857 |
s->mem_read = mem_read; |
858 |
s->mem_write = mem_write; |
859 |
s->opaque = opaque; |
860 |
s->in = 0;
|
861 |
return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
|
862 |
} |
863 |
# define cpu_register_io_memory debug_register_io_memory
|
864 |
# endif
|
865 |
|
866 |
/* Not really omap specific, but is the only thing that uses the
|
867 |
uwire interface. */
|
868 |
/* tsc210x.c */
|
869 |
struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
|
870 |
struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip); |
871 |
|
872 |
#endif /* hw_omap_h */ |