|
1 |
/*
|
|
2 |
* QEMU model of the Milkymist SD Card Controller.
|
|
3 |
*
|
|
4 |
* Copyright (c) 2010 Michael Walle <michael@walle.cc>
|
|
5 |
*
|
|
6 |
* This library is free software; you can redistribute it and/or
|
|
7 |
* modify it under the terms of the GNU Lesser General Public
|
|
8 |
* License as published by the Free Software Foundation; either
|
|
9 |
* version 2 of the License, or (at your option) any later version.
|
|
10 |
*
|
|
11 |
* This library is distributed in the hope that it will be useful,
|
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
14 |
* Lesser General Public License for more details.
|
|
15 |
*
|
|
16 |
* You should have received a copy of the GNU Lesser General Public
|
|
17 |
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
|
18 |
*
|
|
19 |
*
|
|
20 |
* Specification available at:
|
|
21 |
* http://www.milkymist.org/socdoc/memcard.pdf
|
|
22 |
*/
|
|
23 |
|
|
24 |
#include "hw.h"
|
|
25 |
#include "sysbus.h"
|
|
26 |
#include "sysemu.h"
|
|
27 |
#include "trace.h"
|
|
28 |
#include "qemu-error.h"
|
|
29 |
#include "blockdev.h"
|
|
30 |
#include "sd.h"
|
|
31 |
|
|
32 |
enum {
|
|
33 |
ENABLE_CMD_TX = (1<<0),
|
|
34 |
ENABLE_CMD_RX = (1<<1),
|
|
35 |
ENABLE_DAT_TX = (1<<2),
|
|
36 |
ENABLE_DAT_RX = (1<<3),
|
|
37 |
};
|
|
38 |
|
|
39 |
enum {
|
|
40 |
PENDING_CMD_TX = (1<<0),
|
|
41 |
PENDING_CMD_RX = (1<<1),
|
|
42 |
PENDING_DAT_TX = (1<<2),
|
|
43 |
PENDING_DAT_RX = (1<<3),
|
|
44 |
};
|
|
45 |
|
|
46 |
enum {
|
|
47 |
START_CMD_TX = (1<<0),
|
|
48 |
START_DAT_RX = (1<<1),
|
|
49 |
};
|
|
50 |
|
|
51 |
enum {
|
|
52 |
R_CLK2XDIV = 0,
|
|
53 |
R_ENABLE,
|
|
54 |
R_PENDING,
|
|
55 |
R_START,
|
|
56 |
R_CMD,
|
|
57 |
R_DAT,
|
|
58 |
R_MAX
|
|
59 |
};
|
|
60 |
|
|
61 |
struct MilkymistMemcardState {
|
|
62 |
SysBusDevice busdev;
|
|
63 |
SDState *card;
|
|
64 |
|
|
65 |
int command_write_ptr;
|
|
66 |
int response_read_ptr;
|
|
67 |
int response_len;
|
|
68 |
int ignore_next_cmd;
|
|
69 |
int enabled;
|
|
70 |
uint8_t command[6];
|
|
71 |
uint8_t response[17];
|
|
72 |
uint32_t regs[R_MAX];
|
|
73 |
};
|
|
74 |
typedef struct MilkymistMemcardState MilkymistMemcardState;
|
|
75 |
|
|
76 |
static void update_pending_bits(MilkymistMemcardState *s)
|
|
77 |
{
|
|
78 |
/* transmits are instantaneous, thus tx pending bits are never set */
|
|
79 |
s->regs[R_PENDING] = 0;
|
|
80 |
/* if rx is enabled the corresponding pending bits are always set */
|
|
81 |
if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
|
|
82 |
s->regs[R_PENDING] |= PENDING_CMD_RX;
|
|
83 |
}
|
|
84 |
if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
|
|
85 |
s->regs[R_PENDING] |= PENDING_DAT_RX;
|
|
86 |
}
|
|
87 |
}
|
|
88 |
|
|
89 |
static void memcard_sd_command(MilkymistMemcardState *s)
|
|
90 |
{
|
|
91 |
SDRequest req;
|
|
92 |
|
|
93 |
req.cmd = s->command[0] & 0x3f;
|
|
94 |
req.arg = (s->command[1] << 24) | (s->command[2] << 16)
|
|
95 |
| (s->command[3] << 8) | s->command[4];
|
|
96 |
req.crc = s->command[5];
|
|
97 |
|
|
98 |
s->response[0] = req.cmd;
|
|
99 |
s->response_len = sd_do_command(s->card, &req, s->response+1);
|
|
100 |
s->response_read_ptr = 0;
|
|
101 |
|
|
102 |
if (s->response_len == 16) {
|
|
103 |
/* R2 response */
|
|
104 |
s->response[0] = 0x3f;
|
|
105 |
s->response_len += 1;
|
|
106 |
} else if (s->response_len == 4) {
|
|
107 |
/* no crc calculation, insert dummy byte */
|
|
108 |
s->response[5] = 0;
|
|
109 |
s->response_len += 2;
|
|
110 |
}
|
|
111 |
|
|
112 |
if (req.cmd == 0) {
|
|
113 |
/* next write is a dummy byte to clock the initialization of the sd
|
|
114 |
* card */
|
|
115 |
s->ignore_next_cmd = 1;
|
|
116 |
}
|
|
117 |
}
|
|
118 |
|
|
119 |
static uint32_t memcard_read(void *opaque, target_phys_addr_t addr)
|
|
120 |
{
|
|
121 |
MilkymistMemcardState *s = opaque;
|
|
122 |
uint32_t r = 0;
|
|
123 |
|
|
124 |
addr >>= 2;
|
|
125 |
switch (addr) {
|
|
126 |
case R_CMD:
|
|
127 |
if (!s->enabled) {
|
|
128 |
r = 0xff;
|
|
129 |
} else {
|
|
130 |
r = s->response[s->response_read_ptr++];
|
|
131 |
if (s->response_read_ptr > s->response_len) {
|
|
132 |
error_report("milkymist_memcard: "
|
|
133 |
"read more cmd bytes than available. Clipping.");
|
|
134 |
s->response_read_ptr = 0;
|
|
135 |
}
|
|
136 |
}
|
|
137 |
break;
|
|
138 |
case R_DAT:
|
|
139 |
if (!s->enabled) {
|
|
140 |
r = 0xffffffff;
|
|
141 |
} else {
|
|
142 |
r = 0;
|
|
143 |
r |= sd_read_data(s->card) << 24;
|
|
144 |
r |= sd_read_data(s->card) << 16;
|
|
145 |
r |= sd_read_data(s->card) << 8;
|
|
146 |
r |= sd_read_data(s->card);
|
|
147 |
}
|
|
148 |
break;
|
|
149 |
case R_CLK2XDIV:
|
|
150 |
case R_ENABLE:
|
|
151 |
case R_PENDING:
|
|
152 |
case R_START:
|
|
153 |
r = s->regs[addr];
|
|
154 |
break;
|
|
155 |
|
|
156 |
default:
|
|
157 |
error_report("milkymist_memcard: read access to unkown register 0x"
|
|
158 |
TARGET_FMT_plx, addr << 2);
|
|
159 |
break;
|
|
160 |
}
|
|
161 |
|
|
162 |
trace_milkymist_memcard_memory_read(addr << 2, r);
|
|
163 |
|
|
164 |
return r;
|
|
165 |
}
|
|
166 |
|
|
167 |
static void memcard_write(void *opaque, target_phys_addr_t addr, uint32_t value)
|
|
168 |
{
|
|
169 |
MilkymistMemcardState *s = opaque;
|
|
170 |
|
|
171 |
trace_milkymist_memcard_memory_write(addr, value);
|
|
172 |
|
|
173 |
addr >>= 2;
|
|
174 |
switch (addr) {
|
|
175 |
case R_PENDING:
|
|
176 |
/* clear rx pending bits */
|
|
177 |
s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
|
|
178 |
update_pending_bits(s);
|
|
179 |
break;
|
|
180 |
case R_CMD:
|
|
181 |
if (!s->enabled) {
|
|
182 |
break;
|
|
183 |
}
|
|
184 |
if (s->ignore_next_cmd) {
|
|
185 |
s->ignore_next_cmd = 0;
|
|
186 |
break;
|
|
187 |
}
|
|
188 |
s->command[s->command_write_ptr] = value & 0xff;
|
|
189 |
s->command_write_ptr = (s->command_write_ptr + 1) % 6;
|
|
190 |
if (s->command_write_ptr == 0) {
|
|
191 |
memcard_sd_command(s);
|
|
192 |
}
|
|
193 |
break;
|
|
194 |
case R_DAT:
|
|
195 |
if (!s->enabled) {
|
|
196 |
break;
|
|
197 |
}
|
|
198 |
sd_write_data(s->card, (value >> 24) & 0xff);
|
|
199 |
sd_write_data(s->card, (value >> 16) & 0xff);
|
|
200 |
sd_write_data(s->card, (value >> 8) & 0xff);
|
|
201 |
sd_write_data(s->card, value & 0xff);
|
|
202 |
break;
|
|
203 |
case R_ENABLE:
|
|
204 |
s->regs[addr] = value;
|
|
205 |
update_pending_bits(s);
|
|
206 |
break;
|
|
207 |
case R_CLK2XDIV:
|
|
208 |
case R_START:
|
|
209 |
s->regs[addr] = value;
|
|
210 |
break;
|
|
211 |
|
|
212 |
default:
|
|
213 |
error_report("milkymist_memcard: write access to unkown register 0x"
|
|
214 |
TARGET_FMT_plx, addr << 2);
|
|
215 |
break;
|
|
216 |
}
|
|
217 |
}
|
|
218 |
|
|
219 |
static CPUReadMemoryFunc * const memcard_read_fn[] = {
|
|
220 |
NULL,
|
|
221 |
NULL,
|
|
222 |
&memcard_read,
|
|
223 |
};
|
|
224 |
|
|
225 |
static CPUWriteMemoryFunc * const memcard_write_fn[] = {
|
|
226 |
NULL,
|
|
227 |
NULL,
|
|
228 |
&memcard_write,
|
|
229 |
};
|
|
230 |
|
|
231 |
static void milkymist_memcard_reset(DeviceState *d)
|
|
232 |
{
|
|
233 |
MilkymistMemcardState *s =
|
|
234 |
container_of(d, MilkymistMemcardState, busdev.qdev);
|
|
235 |
int i;
|
|
236 |
|
|
237 |
s->command_write_ptr = 0;
|
|
238 |
s->response_read_ptr = 0;
|
|
239 |
s->response_len = 0;
|
|
240 |
|
|
241 |
for (i = 0; i < R_MAX; i++) {
|
|
242 |
s->regs[i] = 0;
|
|
243 |
}
|
|
244 |
}
|
|
245 |
|
|
246 |
static int milkymist_memcard_init(SysBusDevice *dev)
|
|
247 |
{
|
|
248 |
MilkymistMemcardState *s = FROM_SYSBUS(typeof(*s), dev);
|
|
249 |
DriveInfo *dinfo;
|
|
250 |
int memcard_regs;
|
|
251 |
|
|
252 |
dinfo = drive_get_next(IF_SD);
|
|
253 |
s->card = sd_init(dinfo ? dinfo->bdrv : NULL, 0);
|
|
254 |
s->enabled = dinfo ? bdrv_is_inserted(dinfo->bdrv) : 0;
|
|
255 |
|
|
256 |
memcard_regs = cpu_register_io_memory(memcard_read_fn, memcard_write_fn, s,
|
|
257 |
DEVICE_NATIVE_ENDIAN);
|
|
258 |
sysbus_init_mmio(dev, R_MAX * 4, memcard_regs);
|
|
259 |
|
|
260 |
return 0;
|
|
261 |
}
|
|
262 |
|
|
263 |
static const VMStateDescription vmstate_milkymist_memcard = {
|
|
264 |
.name = "milkymist-memcard",
|
|
265 |
.version_id = 1,
|
|
266 |
.minimum_version_id = 1,
|
|
267 |
.minimum_version_id_old = 1,
|
|
268 |
.fields = (VMStateField[]) {
|
|
269 |
VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
|
|
270 |
VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
|
|
271 |
VMSTATE_INT32(response_len, MilkymistMemcardState),
|
|
272 |
VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
|
|
273 |
VMSTATE_INT32(enabled, MilkymistMemcardState),
|
|
274 |
VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
|
|
275 |
VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
|
|
276 |
VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
|
|
277 |
VMSTATE_END_OF_LIST()
|
|
278 |
}
|
|
279 |
};
|
|
280 |
|
|
281 |
static SysBusDeviceInfo milkymist_memcard_info = {
|
|
282 |
.init = milkymist_memcard_init,
|
|
283 |
.qdev.name = "milkymist-memcard",
|
|
284 |
.qdev.size = sizeof(MilkymistMemcardState),
|
|
285 |
.qdev.vmsd = &vmstate_milkymist_memcard,
|
|
286 |
.qdev.reset = milkymist_memcard_reset,
|
|
287 |
};
|
|
288 |
|
|
289 |
static void milkymist_memcard_register(void)
|
|
290 |
{
|
|
291 |
sysbus_register_withprop(&milkymist_memcard_info);
|
|
292 |
}
|
|
293 |
|
|
294 |
device_init(milkymist_memcard_register)
|