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1 | e8af50a3 | bellard | /*
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2 | e8af50a3 | bellard | * sparc helpers
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3 | 5fafdf24 | ths | *
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4 | 83469015 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | e8af50a3 | bellard | *
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6 | e8af50a3 | bellard | * This library is free software; you can redistribute it and/or
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7 | e8af50a3 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | e8af50a3 | bellard | * License as published by the Free Software Foundation; either
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9 | e8af50a3 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | e8af50a3 | bellard | *
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11 | e8af50a3 | bellard | * This library is distributed in the hope that it will be useful,
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12 | e8af50a3 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | e8af50a3 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | e8af50a3 | bellard | * Lesser General Public License for more details.
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15 | e8af50a3 | bellard | *
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16 | e8af50a3 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | e8af50a3 | bellard | */
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19 | ee5bbe38 | bellard | #include <stdarg.h> |
20 | ee5bbe38 | bellard | #include <stdlib.h> |
21 | ee5bbe38 | bellard | #include <stdio.h> |
22 | ee5bbe38 | bellard | #include <string.h> |
23 | ee5bbe38 | bellard | #include <inttypes.h> |
24 | ee5bbe38 | bellard | #include <signal.h> |
25 | ee5bbe38 | bellard | |
26 | ee5bbe38 | bellard | #include "cpu.h" |
27 | ee5bbe38 | bellard | #include "exec-all.h" |
28 | ca10f867 | aurel32 | #include "qemu-common.h" |
29 | e8af50a3 | bellard | |
30 | e80cfcfc | bellard | //#define DEBUG_MMU
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31 | 64a88d5d | blueswir1 | //#define DEBUG_FEATURES
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32 | e8af50a3 | bellard | |
33 | 22548760 | blueswir1 | static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); |
34 | c48fcb47 | blueswir1 | |
35 | e8af50a3 | bellard | /* Sparc MMU emulation */
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36 | e8af50a3 | bellard | |
37 | e8af50a3 | bellard | /* thread support */
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38 | e8af50a3 | bellard | |
39 | c227f099 | Anthony Liguori | static spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
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40 | e8af50a3 | bellard | |
41 | e8af50a3 | bellard | void cpu_lock(void) |
42 | e8af50a3 | bellard | { |
43 | e8af50a3 | bellard | spin_lock(&global_cpu_lock); |
44 | e8af50a3 | bellard | } |
45 | e8af50a3 | bellard | |
46 | e8af50a3 | bellard | void cpu_unlock(void) |
47 | e8af50a3 | bellard | { |
48 | e8af50a3 | bellard | spin_unlock(&global_cpu_lock); |
49 | e8af50a3 | bellard | } |
50 | e8af50a3 | bellard | |
51 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
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52 | 9d893301 | bellard | |
53 | 22548760 | blueswir1 | int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw, |
54 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
55 | 9d893301 | bellard | { |
56 | 878d3096 | bellard | if (rw & 2) |
57 | 22548760 | blueswir1 | env1->exception_index = TT_TFAULT; |
58 | 878d3096 | bellard | else
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59 | 22548760 | blueswir1 | env1->exception_index = TT_DFAULT; |
60 | 9d893301 | bellard | return 1; |
61 | 9d893301 | bellard | } |
62 | 9d893301 | bellard | |
63 | 9d893301 | bellard | #else
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64 | e8af50a3 | bellard | |
65 | 3475187d | bellard | #ifndef TARGET_SPARC64
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66 | 83469015 | bellard | /*
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67 | 83469015 | bellard | * Sparc V8 Reference MMU (SRMMU)
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68 | 83469015 | bellard | */
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69 | e8af50a3 | bellard | static const int access_table[8][8] = { |
70 | a764a566 | blueswir1 | { 0, 0, 0, 0, 8, 0, 12, 12 }, |
71 | a764a566 | blueswir1 | { 0, 0, 0, 0, 8, 0, 0, 0 }, |
72 | a764a566 | blueswir1 | { 8, 8, 0, 0, 0, 8, 12, 12 }, |
73 | a764a566 | blueswir1 | { 8, 8, 0, 0, 0, 8, 0, 0 }, |
74 | a764a566 | blueswir1 | { 8, 0, 8, 0, 8, 8, 12, 12 }, |
75 | a764a566 | blueswir1 | { 8, 0, 8, 0, 8, 0, 8, 0 }, |
76 | a764a566 | blueswir1 | { 8, 8, 8, 0, 8, 8, 12, 12 }, |
77 | a764a566 | blueswir1 | { 8, 8, 8, 0, 8, 8, 8, 0 } |
78 | e8af50a3 | bellard | }; |
79 | e8af50a3 | bellard | |
80 | 227671c9 | bellard | static const int perm_table[2][8] = { |
81 | 227671c9 | bellard | { |
82 | 227671c9 | bellard | PAGE_READ, |
83 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE, |
84 | 227671c9 | bellard | PAGE_READ | PAGE_EXEC, |
85 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
86 | 227671c9 | bellard | PAGE_EXEC, |
87 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE, |
88 | 227671c9 | bellard | PAGE_READ | PAGE_EXEC, |
89 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE | PAGE_EXEC |
90 | 227671c9 | bellard | }, |
91 | 227671c9 | bellard | { |
92 | 227671c9 | bellard | PAGE_READ, |
93 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE, |
94 | 227671c9 | bellard | PAGE_READ | PAGE_EXEC, |
95 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
96 | 227671c9 | bellard | PAGE_EXEC, |
97 | 227671c9 | bellard | PAGE_READ, |
98 | 227671c9 | bellard | 0,
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99 | 227671c9 | bellard | 0,
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100 | 227671c9 | bellard | } |
101 | e8af50a3 | bellard | }; |
102 | e8af50a3 | bellard | |
103 | c227f099 | Anthony Liguori | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
104 | c48fcb47 | blueswir1 | int *prot, int *access_index, |
105 | c48fcb47 | blueswir1 | target_ulong address, int rw, int mmu_idx) |
106 | e8af50a3 | bellard | { |
107 | e80cfcfc | bellard | int access_perms = 0; |
108 | c227f099 | Anthony Liguori | target_phys_addr_t pde_ptr; |
109 | af7bf89b | bellard | uint32_t pde; |
110 | af7bf89b | bellard | target_ulong virt_addr; |
111 | 6ebbf390 | j_mayer | int error_code = 0, is_dirty, is_user; |
112 | e80cfcfc | bellard | unsigned long page_offset; |
113 | e8af50a3 | bellard | |
114 | 6ebbf390 | j_mayer | is_user = mmu_idx == MMU_USER_IDX; |
115 | e8af50a3 | bellard | virt_addr = address & TARGET_PAGE_MASK; |
116 | 40ce0a9a | blueswir1 | |
117 | e8af50a3 | bellard | if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
118 | 40ce0a9a | blueswir1 | // Boot mode: instruction fetches are taken from PROM
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119 | 5578ceab | blueswir1 | if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) { |
120 | 58a770f3 | blueswir1 | *physical = env->prom_addr | (address & 0x7ffffULL);
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121 | 40ce0a9a | blueswir1 | *prot = PAGE_READ | PAGE_EXEC; |
122 | 40ce0a9a | blueswir1 | return 0; |
123 | 40ce0a9a | blueswir1 | } |
124 | 0f8a249a | blueswir1 | *physical = address; |
125 | 227671c9 | bellard | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
126 | e80cfcfc | bellard | return 0; |
127 | e8af50a3 | bellard | } |
128 | e8af50a3 | bellard | |
129 | 7483750d | bellard | *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
130 | 5dcb6b91 | blueswir1 | *physical = 0xffffffffffff0000ULL;
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131 | 7483750d | bellard | |
132 | e8af50a3 | bellard | /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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133 | e8af50a3 | bellard | /* Context base + context number */
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134 | 3deaeab7 | blueswir1 | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
135 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
136 | e8af50a3 | bellard | |
137 | e8af50a3 | bellard | /* Ctx pde */
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138 | e8af50a3 | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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139 | e80cfcfc | bellard | default:
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140 | e8af50a3 | bellard | case 0: /* Invalid */ |
141 | 0f8a249a | blueswir1 | return 1 << 2; |
142 | e80cfcfc | bellard | case 2: /* L0 PTE, maybe should not happen? */ |
143 | e8af50a3 | bellard | case 3: /* Reserved */ |
144 | 7483750d | bellard | return 4 << 2; |
145 | e80cfcfc | bellard | case 1: /* L0 PDE */ |
146 | 0f8a249a | blueswir1 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
147 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
148 | e8af50a3 | bellard | |
149 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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150 | 0f8a249a | blueswir1 | default:
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151 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
152 | 0f8a249a | blueswir1 | return (1 << 8) | (1 << 2); |
153 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
154 | 0f8a249a | blueswir1 | return (1 << 8) | (4 << 2); |
155 | 0f8a249a | blueswir1 | case 1: /* L1 PDE */ |
156 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
157 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
158 | e8af50a3 | bellard | |
159 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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160 | 0f8a249a | blueswir1 | default:
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161 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
162 | 0f8a249a | blueswir1 | return (2 << 8) | (1 << 2); |
163 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
164 | 0f8a249a | blueswir1 | return (2 << 8) | (4 << 2); |
165 | 0f8a249a | blueswir1 | case 1: /* L2 PDE */ |
166 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
167 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
168 | e8af50a3 | bellard | |
169 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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170 | 0f8a249a | blueswir1 | default:
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171 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
172 | 0f8a249a | blueswir1 | return (3 << 8) | (1 << 2); |
173 | 0f8a249a | blueswir1 | case 1: /* PDE, should not happen */ |
174 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
175 | 0f8a249a | blueswir1 | return (3 << 8) | (4 << 2); |
176 | 0f8a249a | blueswir1 | case 2: /* L3 PTE */ |
177 | 0f8a249a | blueswir1 | virt_addr = address & TARGET_PAGE_MASK; |
178 | 77f193da | blueswir1 | page_offset = (address & TARGET_PAGE_MASK) & |
179 | 77f193da | blueswir1 | (TARGET_PAGE_SIZE - 1);
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180 | 0f8a249a | blueswir1 | } |
181 | 0f8a249a | blueswir1 | break;
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182 | 0f8a249a | blueswir1 | case 2: /* L2 PTE */ |
183 | 0f8a249a | blueswir1 | virt_addr = address & ~0x3ffff;
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184 | 0f8a249a | blueswir1 | page_offset = address & 0x3ffff;
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185 | 0f8a249a | blueswir1 | } |
186 | 0f8a249a | blueswir1 | break;
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187 | 0f8a249a | blueswir1 | case 2: /* L1 PTE */ |
188 | 0f8a249a | blueswir1 | virt_addr = address & ~0xffffff;
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189 | 0f8a249a | blueswir1 | page_offset = address & 0xffffff;
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190 | 0f8a249a | blueswir1 | } |
191 | e8af50a3 | bellard | } |
192 | e8af50a3 | bellard | |
193 | e8af50a3 | bellard | /* update page modified and dirty bits */
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194 | b769d8fe | bellard | is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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195 | e8af50a3 | bellard | if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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196 | 0f8a249a | blueswir1 | pde |= PG_ACCESSED_MASK; |
197 | 0f8a249a | blueswir1 | if (is_dirty)
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198 | 0f8a249a | blueswir1 | pde |= PG_MODIFIED_MASK; |
199 | 49be8030 | bellard | stl_phys_notdirty(pde_ptr, pde); |
200 | e8af50a3 | bellard | } |
201 | e8af50a3 | bellard | /* check access */
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202 | e8af50a3 | bellard | access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
203 | e80cfcfc | bellard | error_code = access_table[*access_index][access_perms]; |
204 | d8e3326c | bellard | if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) |
205 | 0f8a249a | blueswir1 | return error_code;
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206 | e8af50a3 | bellard | |
207 | e8af50a3 | bellard | /* the page can be put in the TLB */
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208 | 227671c9 | bellard | *prot = perm_table[is_user][access_perms]; |
209 | 227671c9 | bellard | if (!(pde & PG_MODIFIED_MASK)) {
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210 | e8af50a3 | bellard | /* only set write access if already dirty... otherwise wait
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211 | e8af50a3 | bellard | for dirty access */
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212 | 227671c9 | bellard | *prot &= ~PAGE_WRITE; |
213 | e8af50a3 | bellard | } |
214 | e8af50a3 | bellard | |
215 | e8af50a3 | bellard | /* Even if large ptes, we map only one 4KB page in the cache to
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216 | e8af50a3 | bellard | avoid filling it too fast */
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217 | c227f099 | Anthony Liguori | *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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218 | 6f7e9aec | bellard | return error_code;
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219 | e80cfcfc | bellard | } |
220 | e80cfcfc | bellard | |
221 | e80cfcfc | bellard | /* Perform address translation */
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222 | af7bf89b | bellard | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
223 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
224 | e80cfcfc | bellard | { |
225 | c227f099 | Anthony Liguori | target_phys_addr_t paddr; |
226 | 5dcb6b91 | blueswir1 | target_ulong vaddr; |
227 | e80cfcfc | bellard | int error_code = 0, prot, ret = 0, access_index; |
228 | e8af50a3 | bellard | |
229 | 77f193da | blueswir1 | error_code = get_physical_address(env, &paddr, &prot, &access_index, |
230 | 77f193da | blueswir1 | address, rw, mmu_idx); |
231 | e80cfcfc | bellard | if (error_code == 0) { |
232 | 0f8a249a | blueswir1 | vaddr = address & TARGET_PAGE_MASK; |
233 | 0f8a249a | blueswir1 | paddr &= TARGET_PAGE_MASK; |
234 | 9e61bde5 | bellard | #ifdef DEBUG_MMU
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235 | 0f8a249a | blueswir1 | printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
236 | 5dcb6b91 | blueswir1 | TARGET_FMT_lx "\n", address, paddr, vaddr);
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237 | 9e61bde5 | bellard | #endif
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238 | 6ebbf390 | j_mayer | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
239 | 0f8a249a | blueswir1 | return ret;
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240 | e80cfcfc | bellard | } |
241 | e8af50a3 | bellard | |
242 | e8af50a3 | bellard | if (env->mmuregs[3]) /* Fault status register */ |
243 | 0f8a249a | blueswir1 | env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
244 | 7483750d | bellard | env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
245 | e8af50a3 | bellard | env->mmuregs[4] = address; /* Fault address register */ |
246 | e8af50a3 | bellard | |
247 | 878d3096 | bellard | if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
248 | 6f7e9aec | bellard | // No fault mode: if a mapping is available, just override
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249 | 6f7e9aec | bellard | // permissions. If no mapping is available, redirect accesses to
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250 | 6f7e9aec | bellard | // neverland. Fake/overridden mappings will be flushed when
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251 | 6f7e9aec | bellard | // switching to normal mode.
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252 | 0f8a249a | blueswir1 | vaddr = address & TARGET_PAGE_MASK; |
253 | 227671c9 | bellard | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
254 | 6ebbf390 | j_mayer | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
255 | 0f8a249a | blueswir1 | return ret;
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256 | 7483750d | bellard | } else {
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257 | 7483750d | bellard | if (rw & 2) |
258 | 7483750d | bellard | env->exception_index = TT_TFAULT; |
259 | 7483750d | bellard | else
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260 | 7483750d | bellard | env->exception_index = TT_DFAULT; |
261 | 7483750d | bellard | return 1; |
262 | 878d3096 | bellard | } |
263 | e8af50a3 | bellard | } |
264 | 24741ef3 | bellard | |
265 | 24741ef3 | bellard | target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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266 | 24741ef3 | bellard | { |
267 | c227f099 | Anthony Liguori | target_phys_addr_t pde_ptr; |
268 | 24741ef3 | bellard | uint32_t pde; |
269 | 24741ef3 | bellard | |
270 | 24741ef3 | bellard | /* Context base + context number */
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271 | c227f099 | Anthony Liguori | pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
272 | 5dcb6b91 | blueswir1 | (env->mmuregs[2] << 2); |
273 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
274 | 24741ef3 | bellard | |
275 | 24741ef3 | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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276 | 24741ef3 | bellard | default:
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277 | 24741ef3 | bellard | case 0: /* Invalid */ |
278 | 24741ef3 | bellard | case 2: /* PTE, maybe should not happen? */ |
279 | 24741ef3 | bellard | case 3: /* Reserved */ |
280 | 0f8a249a | blueswir1 | return 0; |
281 | 24741ef3 | bellard | case 1: /* L1 PDE */ |
282 | 0f8a249a | blueswir1 | if (mmulev == 3) |
283 | 0f8a249a | blueswir1 | return pde;
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284 | 0f8a249a | blueswir1 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
285 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
286 | 24741ef3 | bellard | |
287 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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288 | 0f8a249a | blueswir1 | default:
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289 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
290 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
291 | 0f8a249a | blueswir1 | return 0; |
292 | 0f8a249a | blueswir1 | case 2: /* L1 PTE */ |
293 | 0f8a249a | blueswir1 | return pde;
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294 | 0f8a249a | blueswir1 | case 1: /* L2 PDE */ |
295 | 0f8a249a | blueswir1 | if (mmulev == 2) |
296 | 0f8a249a | blueswir1 | return pde;
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297 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
298 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
299 | 24741ef3 | bellard | |
300 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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301 | 0f8a249a | blueswir1 | default:
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302 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
303 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
304 | 0f8a249a | blueswir1 | return 0; |
305 | 0f8a249a | blueswir1 | case 2: /* L2 PTE */ |
306 | 0f8a249a | blueswir1 | return pde;
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307 | 0f8a249a | blueswir1 | case 1: /* L3 PDE */ |
308 | 0f8a249a | blueswir1 | if (mmulev == 1) |
309 | 0f8a249a | blueswir1 | return pde;
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310 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
311 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
312 | 24741ef3 | bellard | |
313 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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314 | 0f8a249a | blueswir1 | default:
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315 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
316 | 0f8a249a | blueswir1 | case 1: /* PDE, should not happen */ |
317 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
318 | 0f8a249a | blueswir1 | return 0; |
319 | 0f8a249a | blueswir1 | case 2: /* L3 PTE */ |
320 | 0f8a249a | blueswir1 | return pde;
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321 | 0f8a249a | blueswir1 | } |
322 | 0f8a249a | blueswir1 | } |
323 | 0f8a249a | blueswir1 | } |
324 | 24741ef3 | bellard | } |
325 | 24741ef3 | bellard | return 0; |
326 | 24741ef3 | bellard | } |
327 | 24741ef3 | bellard | |
328 | 24741ef3 | bellard | #ifdef DEBUG_MMU
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329 | 24741ef3 | bellard | void dump_mmu(CPUState *env)
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330 | 24741ef3 | bellard | { |
331 | 5dcb6b91 | blueswir1 | target_ulong va, va1, va2; |
332 | 5dcb6b91 | blueswir1 | unsigned int n, m, o; |
333 | c227f099 | Anthony Liguori | target_phys_addr_t pde_ptr, pa; |
334 | 24741ef3 | bellard | uint32_t pde; |
335 | 24741ef3 | bellard | |
336 | 24741ef3 | bellard | printf("MMU dump:\n");
|
337 | 24741ef3 | bellard | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
338 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
339 | 5dcb6b91 | blueswir1 | printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
340 | c227f099 | Anthony Liguori | (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); |
341 | 24741ef3 | bellard | for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
342 | 0f8a249a | blueswir1 | pde = mmu_probe(env, va, 2);
|
343 | 0f8a249a | blueswir1 | if (pde) {
|
344 | 0f8a249a | blueswir1 | pa = cpu_get_phys_page_debug(env, va); |
345 | 0f8a249a | blueswir1 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
346 | 5dcb6b91 | blueswir1 | " PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
347 | 0f8a249a | blueswir1 | for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
348 | 0f8a249a | blueswir1 | pde = mmu_probe(env, va1, 1);
|
349 | 0f8a249a | blueswir1 | if (pde) {
|
350 | 0f8a249a | blueswir1 | pa = cpu_get_phys_page_debug(env, va1); |
351 | 0f8a249a | blueswir1 | printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
352 | 5dcb6b91 | blueswir1 | " PDE: " TARGET_FMT_lx "\n", va1, pa, pde); |
353 | 0f8a249a | blueswir1 | for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
354 | 0f8a249a | blueswir1 | pde = mmu_probe(env, va2, 0);
|
355 | 0f8a249a | blueswir1 | if (pde) {
|
356 | 0f8a249a | blueswir1 | pa = cpu_get_phys_page_debug(env, va2); |
357 | 0f8a249a | blueswir1 | printf(" VA: " TARGET_FMT_lx ", PA: " |
358 | 5dcb6b91 | blueswir1 | TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", |
359 | 5dcb6b91 | blueswir1 | va2, pa, pde); |
360 | 0f8a249a | blueswir1 | } |
361 | 0f8a249a | blueswir1 | } |
362 | 0f8a249a | blueswir1 | } |
363 | 0f8a249a | blueswir1 | } |
364 | 0f8a249a | blueswir1 | } |
365 | 24741ef3 | bellard | } |
366 | 24741ef3 | bellard | printf("MMU dump ends\n");
|
367 | 24741ef3 | bellard | } |
368 | 24741ef3 | bellard | #endif /* DEBUG_MMU */ |
369 | 24741ef3 | bellard | |
370 | 24741ef3 | bellard | #else /* !TARGET_SPARC64 */ |
371 | e8807b14 | Igor Kovalenko | |
372 | e8807b14 | Igor Kovalenko | // 41 bit physical address space
|
373 | c227f099 | Anthony Liguori | static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x) |
374 | e8807b14 | Igor Kovalenko | { |
375 | e8807b14 | Igor Kovalenko | return x & 0x1ffffffffffULL; |
376 | e8807b14 | Igor Kovalenko | } |
377 | e8807b14 | Igor Kovalenko | |
378 | 83469015 | bellard | /*
|
379 | 83469015 | bellard | * UltraSparc IIi I/DMMUs
|
380 | 83469015 | bellard | */
|
381 | 536ba015 | Igor Kovalenko | |
382 | 536ba015 | Igor Kovalenko | static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) |
383 | 536ba015 | Igor Kovalenko | { |
384 | 536ba015 | Igor Kovalenko | return (x & mask) == (y & mask);
|
385 | 536ba015 | Igor Kovalenko | } |
386 | 536ba015 | Igor Kovalenko | |
387 | 536ba015 | Igor Kovalenko | // Returns true if TTE tag is valid and matches virtual address value in context
|
388 | 536ba015 | Igor Kovalenko | // requires virtual address mask value calculated from TTE entry size
|
389 | 6e8e7d4c | Igor Kovalenko | static inline int ultrasparc_tag_match(SparcTLBEntry *tlb, |
390 | 536ba015 | Igor Kovalenko | uint64_t address, uint64_t context, |
391 | c227f099 | Anthony Liguori | target_phys_addr_t *physical) |
392 | 536ba015 | Igor Kovalenko | { |
393 | 536ba015 | Igor Kovalenko | uint64_t mask; |
394 | 536ba015 | Igor Kovalenko | |
395 | 6e8e7d4c | Igor Kovalenko | switch ((tlb->tte >> 61) & 3) { |
396 | 536ba015 | Igor Kovalenko | default:
|
397 | 536ba015 | Igor Kovalenko | case 0x0: // 8k |
398 | 536ba015 | Igor Kovalenko | mask = 0xffffffffffffe000ULL;
|
399 | 536ba015 | Igor Kovalenko | break;
|
400 | 536ba015 | Igor Kovalenko | case 0x1: // 64k |
401 | 536ba015 | Igor Kovalenko | mask = 0xffffffffffff0000ULL;
|
402 | 536ba015 | Igor Kovalenko | break;
|
403 | 536ba015 | Igor Kovalenko | case 0x2: // 512k |
404 | 536ba015 | Igor Kovalenko | mask = 0xfffffffffff80000ULL;
|
405 | 536ba015 | Igor Kovalenko | break;
|
406 | 536ba015 | Igor Kovalenko | case 0x3: // 4M |
407 | 536ba015 | Igor Kovalenko | mask = 0xffffffffffc00000ULL;
|
408 | 536ba015 | Igor Kovalenko | break;
|
409 | 536ba015 | Igor Kovalenko | } |
410 | 536ba015 | Igor Kovalenko | |
411 | 536ba015 | Igor Kovalenko | // valid, context match, virtual address match?
|
412 | f707726e | Igor Kovalenko | if (TTE_IS_VALID(tlb->tte) &&
|
413 | 6e8e7d4c | Igor Kovalenko | compare_masked(context, tlb->tag, 0x1fff) &&
|
414 | 6e8e7d4c | Igor Kovalenko | compare_masked(address, tlb->tag, mask)) |
415 | 536ba015 | Igor Kovalenko | { |
416 | 536ba015 | Igor Kovalenko | // decode physical address
|
417 | 6e8e7d4c | Igor Kovalenko | *physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL;
|
418 | 536ba015 | Igor Kovalenko | return 1; |
419 | 536ba015 | Igor Kovalenko | } |
420 | 536ba015 | Igor Kovalenko | |
421 | 536ba015 | Igor Kovalenko | return 0; |
422 | 536ba015 | Igor Kovalenko | } |
423 | 536ba015 | Igor Kovalenko | |
424 | 77f193da | blueswir1 | static int get_physical_address_data(CPUState *env, |
425 | c227f099 | Anthony Liguori | target_phys_addr_t *physical, int *prot,
|
426 | 22548760 | blueswir1 | target_ulong address, int rw, int is_user) |
427 | 3475187d | bellard | { |
428 | 3475187d | bellard | unsigned int i; |
429 | 536ba015 | Igor Kovalenko | uint64_t context; |
430 | 3475187d | bellard | |
431 | 3475187d | bellard | if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ |
432 | e8807b14 | Igor Kovalenko | *physical = ultrasparc_truncate_physical(address); |
433 | 0f8a249a | blueswir1 | *prot = PAGE_READ | PAGE_WRITE; |
434 | 3475187d | bellard | return 0; |
435 | 3475187d | bellard | } |
436 | 3475187d | bellard | |
437 | 6e8e7d4c | Igor Kovalenko | context = env->dmmu.mmu_primary_context & 0x1fff;
|
438 | 536ba015 | Igor Kovalenko | |
439 | 3475187d | bellard | for (i = 0; i < 64; i++) { |
440 | afdf8109 | blueswir1 | // ctx match, vaddr match, valid?
|
441 | 6e8e7d4c | Igor Kovalenko | if (ultrasparc_tag_match(&env->dtlb[i],
|
442 | 536ba015 | Igor Kovalenko | address, context, physical) |
443 | 536ba015 | Igor Kovalenko | ) { |
444 | afdf8109 | blueswir1 | // access ok?
|
445 | 6e8e7d4c | Igor Kovalenko | if (((env->dtlb[i].tte & 0x4) && is_user) || |
446 | 6e8e7d4c | Igor Kovalenko | (!(env->dtlb[i].tte & 0x2) && (rw == 1))) { |
447 | 6e8e7d4c | Igor Kovalenko | uint8_t fault_type = 0;
|
448 | 6e8e7d4c | Igor Kovalenko | |
449 | 6e8e7d4c | Igor Kovalenko | if ((env->dtlb[i].tte & 0x4) && is_user) { |
450 | 6e8e7d4c | Igor Kovalenko | fault_type |= 1; /* privilege violation */ |
451 | 6e8e7d4c | Igor Kovalenko | } |
452 | 6e8e7d4c | Igor Kovalenko | |
453 | 6e8e7d4c | Igor Kovalenko | if (env->dmmu.sfsr & 1) /* Fault status register */ |
454 | 6e8e7d4c | Igor Kovalenko | env->dmmu.sfsr = 2; /* overflow (not read before |
455 | 77f193da | blueswir1 | another fault) */
|
456 | 6e8e7d4c | Igor Kovalenko | |
457 | 6e8e7d4c | Igor Kovalenko | env->dmmu.sfsr |= (is_user << 3) | ((rw == 1) << 2) | 1; |
458 | 6e8e7d4c | Igor Kovalenko | |
459 | 6e8e7d4c | Igor Kovalenko | env->dmmu.sfsr |= (fault_type << 7);
|
460 | 6e8e7d4c | Igor Kovalenko | |
461 | 6e8e7d4c | Igor Kovalenko | env->dmmu.sfar = address; /* Fault address register */
|
462 | 0f8a249a | blueswir1 | env->exception_index = TT_DFAULT; |
463 | 83469015 | bellard | #ifdef DEBUG_MMU
|
464 | 0f8a249a | blueswir1 | printf("DFAULT at 0x%" PRIx64 "\n", address); |
465 | 83469015 | bellard | #endif
|
466 | 0f8a249a | blueswir1 | return 1; |
467 | 0f8a249a | blueswir1 | } |
468 | 0f8a249a | blueswir1 | *prot = PAGE_READ; |
469 | 6e8e7d4c | Igor Kovalenko | if (env->dtlb[i].tte & 0x2) |
470 | 0f8a249a | blueswir1 | *prot |= PAGE_WRITE; |
471 | f707726e | Igor Kovalenko | TTE_SET_USED(env->dtlb[i].tte); |
472 | 0f8a249a | blueswir1 | return 0; |
473 | 0f8a249a | blueswir1 | } |
474 | 3475187d | bellard | } |
475 | 83469015 | bellard | #ifdef DEBUG_MMU
|
476 | 26a76461 | bellard | printf("DMISS at 0x%" PRIx64 "\n", address); |
477 | 83469015 | bellard | #endif
|
478 | 6e8e7d4c | Igor Kovalenko | env->dmmu.tag_access = (address & ~0x1fffULL) | context;
|
479 | 83469015 | bellard | env->exception_index = TT_DMISS; |
480 | 3475187d | bellard | return 1; |
481 | 3475187d | bellard | } |
482 | 3475187d | bellard | |
483 | 77f193da | blueswir1 | static int get_physical_address_code(CPUState *env, |
484 | c227f099 | Anthony Liguori | target_phys_addr_t *physical, int *prot,
|
485 | 22548760 | blueswir1 | target_ulong address, int is_user)
|
486 | 3475187d | bellard | { |
487 | 3475187d | bellard | unsigned int i; |
488 | 536ba015 | Igor Kovalenko | uint64_t context; |
489 | 3475187d | bellard | |
490 | e8807b14 | Igor Kovalenko | if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) { |
491 | e8807b14 | Igor Kovalenko | /* IMMU disabled */
|
492 | e8807b14 | Igor Kovalenko | *physical = ultrasparc_truncate_physical(address); |
493 | 0f8a249a | blueswir1 | *prot = PAGE_EXEC; |
494 | 3475187d | bellard | return 0; |
495 | 3475187d | bellard | } |
496 | 83469015 | bellard | |
497 | 6e8e7d4c | Igor Kovalenko | context = env->dmmu.mmu_primary_context & 0x1fff;
|
498 | 536ba015 | Igor Kovalenko | |
499 | 3475187d | bellard | for (i = 0; i < 64; i++) { |
500 | afdf8109 | blueswir1 | // ctx match, vaddr match, valid?
|
501 | 6e8e7d4c | Igor Kovalenko | if (ultrasparc_tag_match(&env->itlb[i],
|
502 | 536ba015 | Igor Kovalenko | address, context, physical) |
503 | 536ba015 | Igor Kovalenko | ) { |
504 | afdf8109 | blueswir1 | // access ok?
|
505 | 6e8e7d4c | Igor Kovalenko | if ((env->itlb[i].tte & 0x4) && is_user) { |
506 | 6e8e7d4c | Igor Kovalenko | if (env->immu.sfsr) /* Fault status register */ |
507 | 6e8e7d4c | Igor Kovalenko | env->immu.sfsr = 2; /* overflow (not read before |
508 | 77f193da | blueswir1 | another fault) */
|
509 | 6e8e7d4c | Igor Kovalenko | env->immu.sfsr |= (is_user << 3) | 1; |
510 | 0f8a249a | blueswir1 | env->exception_index = TT_TFAULT; |
511 | 83469015 | bellard | #ifdef DEBUG_MMU
|
512 | 0f8a249a | blueswir1 | printf("TFAULT at 0x%" PRIx64 "\n", address); |
513 | 83469015 | bellard | #endif
|
514 | 0f8a249a | blueswir1 | return 1; |
515 | 0f8a249a | blueswir1 | } |
516 | 0f8a249a | blueswir1 | *prot = PAGE_EXEC; |
517 | f707726e | Igor Kovalenko | TTE_SET_USED(env->itlb[i].tte); |
518 | 0f8a249a | blueswir1 | return 0; |
519 | 0f8a249a | blueswir1 | } |
520 | 3475187d | bellard | } |
521 | 83469015 | bellard | #ifdef DEBUG_MMU
|
522 | 26a76461 | bellard | printf("TMISS at 0x%" PRIx64 "\n", address); |
523 | 83469015 | bellard | #endif
|
524 | 7ab463cb | Blue Swirl | /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
|
525 | 6e8e7d4c | Igor Kovalenko | env->immu.tag_access = (address & ~0x1fffULL) | context;
|
526 | 83469015 | bellard | env->exception_index = TT_TMISS; |
527 | 3475187d | bellard | return 1; |
528 | 3475187d | bellard | } |
529 | 3475187d | bellard | |
530 | c227f099 | Anthony Liguori | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
531 | c48fcb47 | blueswir1 | int *prot, int *access_index, |
532 | c48fcb47 | blueswir1 | target_ulong address, int rw, int mmu_idx) |
533 | 3475187d | bellard | { |
534 | 6ebbf390 | j_mayer | int is_user = mmu_idx == MMU_USER_IDX;
|
535 | 6ebbf390 | j_mayer | |
536 | 3475187d | bellard | if (rw == 2) |
537 | 22548760 | blueswir1 | return get_physical_address_code(env, physical, prot, address,
|
538 | 22548760 | blueswir1 | is_user); |
539 | 3475187d | bellard | else
|
540 | 22548760 | blueswir1 | return get_physical_address_data(env, physical, prot, address, rw,
|
541 | 22548760 | blueswir1 | is_user); |
542 | 3475187d | bellard | } |
543 | 3475187d | bellard | |
544 | 3475187d | bellard | /* Perform address translation */
|
545 | 3475187d | bellard | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
546 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
547 | 3475187d | bellard | { |
548 | 83469015 | bellard | target_ulong virt_addr, vaddr; |
549 | c227f099 | Anthony Liguori | target_phys_addr_t paddr; |
550 | 3475187d | bellard | int error_code = 0, prot, ret = 0, access_index; |
551 | 3475187d | bellard | |
552 | 77f193da | blueswir1 | error_code = get_physical_address(env, &paddr, &prot, &access_index, |
553 | 77f193da | blueswir1 | address, rw, mmu_idx); |
554 | 3475187d | bellard | if (error_code == 0) { |
555 | 0f8a249a | blueswir1 | virt_addr = address & TARGET_PAGE_MASK; |
556 | 77f193da | blueswir1 | vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & |
557 | 77f193da | blueswir1 | (TARGET_PAGE_SIZE - 1));
|
558 | 83469015 | bellard | #ifdef DEBUG_MMU
|
559 | 77f193da | blueswir1 | printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 |
560 | 77f193da | blueswir1 | "\n", address, paddr, vaddr);
|
561 | 83469015 | bellard | #endif
|
562 | 6ebbf390 | j_mayer | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
563 | 0f8a249a | blueswir1 | return ret;
|
564 | 3475187d | bellard | } |
565 | 3475187d | bellard | // XXX
|
566 | 3475187d | bellard | return 1; |
567 | 3475187d | bellard | } |
568 | 3475187d | bellard | |
569 | 83469015 | bellard | #ifdef DEBUG_MMU
|
570 | 83469015 | bellard | void dump_mmu(CPUState *env)
|
571 | 83469015 | bellard | { |
572 | 83469015 | bellard | unsigned int i; |
573 | 83469015 | bellard | const char *mask; |
574 | 83469015 | bellard | |
575 | 77f193da | blueswir1 | printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", |
576 | 6e8e7d4c | Igor Kovalenko | env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); |
577 | 83469015 | bellard | if ((env->lsu & DMMU_E) == 0) { |
578 | 0f8a249a | blueswir1 | printf("DMMU disabled\n");
|
579 | 83469015 | bellard | } else {
|
580 | 0f8a249a | blueswir1 | printf("DMMU dump:\n");
|
581 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
582 | 0f8a249a | blueswir1 | switch ((env->dtlb_tte[i] >> 61) & 3) { |
583 | 0f8a249a | blueswir1 | default:
|
584 | 0f8a249a | blueswir1 | case 0x0: |
585 | 0f8a249a | blueswir1 | mask = " 8k";
|
586 | 0f8a249a | blueswir1 | break;
|
587 | 0f8a249a | blueswir1 | case 0x1: |
588 | 0f8a249a | blueswir1 | mask = " 64k";
|
589 | 0f8a249a | blueswir1 | break;
|
590 | 0f8a249a | blueswir1 | case 0x2: |
591 | 0f8a249a | blueswir1 | mask = "512k";
|
592 | 0f8a249a | blueswir1 | break;
|
593 | 0f8a249a | blueswir1 | case 0x3: |
594 | 0f8a249a | blueswir1 | mask = " 4M";
|
595 | 0f8a249a | blueswir1 | break;
|
596 | 0f8a249a | blueswir1 | } |
597 | 0f8a249a | blueswir1 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { |
598 | 6e8e7d4c | Igor Kovalenko | printf("[%02u] VA: " PRIx64 ", PA: " PRIx64 |
599 | 77f193da | blueswir1 | ", %s, %s, %s, %s, ctx %" PRId64 "\n", |
600 | 6e8e7d4c | Igor Kovalenko | i, |
601 | 0bf9e31a | Blue Swirl | env->dtlb_tag[i] & (uint64_t)~0x1fffULL,
|
602 | 0bf9e31a | Blue Swirl | env->dtlb_tte[i] & (uint64_t)0x1ffffffe000ULL,
|
603 | 0f8a249a | blueswir1 | mask, |
604 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x4? "priv": "user", |
605 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x2? "RW": "RO", |
606 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x40? "locked": "unlocked", |
607 | 0bf9e31a | Blue Swirl | env->dtlb_tag[i] & (uint64_t)0x1fffULL);
|
608 | 0f8a249a | blueswir1 | } |
609 | 0f8a249a | blueswir1 | } |
610 | 83469015 | bellard | } |
611 | 83469015 | bellard | if ((env->lsu & IMMU_E) == 0) { |
612 | 0f8a249a | blueswir1 | printf("IMMU disabled\n");
|
613 | 83469015 | bellard | } else {
|
614 | 0f8a249a | blueswir1 | printf("IMMU dump:\n");
|
615 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
616 | 0f8a249a | blueswir1 | switch ((env->itlb_tte[i] >> 61) & 3) { |
617 | 0f8a249a | blueswir1 | default:
|
618 | 0f8a249a | blueswir1 | case 0x0: |
619 | 0f8a249a | blueswir1 | mask = " 8k";
|
620 | 0f8a249a | blueswir1 | break;
|
621 | 0f8a249a | blueswir1 | case 0x1: |
622 | 0f8a249a | blueswir1 | mask = " 64k";
|
623 | 0f8a249a | blueswir1 | break;
|
624 | 0f8a249a | blueswir1 | case 0x2: |
625 | 0f8a249a | blueswir1 | mask = "512k";
|
626 | 0f8a249a | blueswir1 | break;
|
627 | 0f8a249a | blueswir1 | case 0x3: |
628 | 0f8a249a | blueswir1 | mask = " 4M";
|
629 | 0f8a249a | blueswir1 | break;
|
630 | 0f8a249a | blueswir1 | } |
631 | 0f8a249a | blueswir1 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { |
632 | 6e8e7d4c | Igor Kovalenko | printf("[%02u] VA: " PRIx64 ", PA: " PRIx64 |
633 | 77f193da | blueswir1 | ", %s, %s, %s, ctx %" PRId64 "\n", |
634 | 6e8e7d4c | Igor Kovalenko | i, |
635 | 6e8e7d4c | Igor Kovalenko | env->itlb[i].tag & (uint64_t)~0x1fffULL,
|
636 | 0bf9e31a | Blue Swirl | env->itlb_tte[i] & (uint64_t)0x1ffffffe000ULL,
|
637 | 0f8a249a | blueswir1 | mask, |
638 | 0f8a249a | blueswir1 | env->itlb_tte[i] & 0x4? "priv": "user", |
639 | 0f8a249a | blueswir1 | env->itlb_tte[i] & 0x40? "locked": "unlocked", |
640 | 6e8e7d4c | Igor Kovalenko | env->itlb[i].tag & (uint64_t)0x1fffULL);
|
641 | 0f8a249a | blueswir1 | } |
642 | 0f8a249a | blueswir1 | } |
643 | 83469015 | bellard | } |
644 | 83469015 | bellard | } |
645 | 24741ef3 | bellard | #endif /* DEBUG_MMU */ |
646 | 24741ef3 | bellard | |
647 | 24741ef3 | bellard | #endif /* TARGET_SPARC64 */ |
648 | 24741ef3 | bellard | #endif /* !CONFIG_USER_ONLY */ |
649 | 24741ef3 | bellard | |
650 | c48fcb47 | blueswir1 | |
651 | c48fcb47 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
652 | c227f099 | Anthony Liguori | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
653 | c48fcb47 | blueswir1 | { |
654 | c48fcb47 | blueswir1 | return addr;
|
655 | c48fcb47 | blueswir1 | } |
656 | c48fcb47 | blueswir1 | |
657 | c48fcb47 | blueswir1 | #else
|
658 | c227f099 | Anthony Liguori | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
659 | c48fcb47 | blueswir1 | { |
660 | c227f099 | Anthony Liguori | target_phys_addr_t phys_addr; |
661 | c48fcb47 | blueswir1 | int prot, access_index;
|
662 | c48fcb47 | blueswir1 | |
663 | c48fcb47 | blueswir1 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, |
664 | c48fcb47 | blueswir1 | MMU_KERNEL_IDX) != 0)
|
665 | c48fcb47 | blueswir1 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
|
666 | c48fcb47 | blueswir1 | 0, MMU_KERNEL_IDX) != 0) |
667 | c48fcb47 | blueswir1 | return -1; |
668 | c48fcb47 | blueswir1 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
|
669 | c48fcb47 | blueswir1 | return -1; |
670 | c48fcb47 | blueswir1 | return phys_addr;
|
671 | c48fcb47 | blueswir1 | } |
672 | c48fcb47 | blueswir1 | #endif
|
673 | c48fcb47 | blueswir1 | |
674 | c48fcb47 | blueswir1 | void cpu_reset(CPUSPARCState *env)
|
675 | c48fcb47 | blueswir1 | { |
676 | eca1bdf4 | aliguori | if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
677 | eca1bdf4 | aliguori | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
678 | eca1bdf4 | aliguori | log_cpu_state(env, 0);
|
679 | eca1bdf4 | aliguori | } |
680 | eca1bdf4 | aliguori | |
681 | c48fcb47 | blueswir1 | tlb_flush(env, 1);
|
682 | c48fcb47 | blueswir1 | env->cwp = 0;
|
683 | 5210977a | Igor Kovalenko | #ifndef TARGET_SPARC64
|
684 | c48fcb47 | blueswir1 | env->wim = 1;
|
685 | 5210977a | Igor Kovalenko | #endif
|
686 | c48fcb47 | blueswir1 | env->regwptr = env->regbase + (env->cwp * 16);
|
687 | 6b743278 | Blue Swirl | CC_OP = CC_OP_FLAGS; |
688 | c48fcb47 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
689 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
690 | 1a14026e | blueswir1 | env->cleanwin = env->nwindows - 2;
|
691 | 1a14026e | blueswir1 | env->cansave = env->nwindows - 2;
|
692 | c48fcb47 | blueswir1 | env->pstate = PS_RMO | PS_PEF | PS_IE; |
693 | c48fcb47 | blueswir1 | env->asi = 0x82; // Primary no-fault |
694 | c48fcb47 | blueswir1 | #endif
|
695 | c48fcb47 | blueswir1 | #else
|
696 | 5210977a | Igor Kovalenko | #if !defined(TARGET_SPARC64)
|
697 | c48fcb47 | blueswir1 | env->psret = 0;
|
698 | 5210977a | Igor Kovalenko | #endif
|
699 | c48fcb47 | blueswir1 | env->psrs = 1;
|
700 | c48fcb47 | blueswir1 | env->psrps = 1;
|
701 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
702 | 8194f35a | Igor Kovalenko | env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG; |
703 | c48fcb47 | blueswir1 | env->hpstate = HS_PRIV; |
704 | 8194f35a | Igor Kovalenko | env->tl = env->maxtl; |
705 | 8194f35a | Igor Kovalenko | cpu_tsptr(env)->tt = TT_POWER_ON_RESET; |
706 | 415fc906 | blueswir1 | env->lsu = 0;
|
707 | c48fcb47 | blueswir1 | #else
|
708 | c48fcb47 | blueswir1 | env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
709 | 5578ceab | blueswir1 | env->mmuregs[0] |= env->def->mmu_bm;
|
710 | c48fcb47 | blueswir1 | #endif
|
711 | e87231d4 | blueswir1 | env->pc = 0;
|
712 | c48fcb47 | blueswir1 | env->npc = env->pc + 4;
|
713 | c48fcb47 | blueswir1 | #endif
|
714 | c48fcb47 | blueswir1 | } |
715 | c48fcb47 | blueswir1 | |
716 | 64a88d5d | blueswir1 | static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) |
717 | c48fcb47 | blueswir1 | { |
718 | 64a88d5d | blueswir1 | sparc_def_t def1, *def = &def1; |
719 | c48fcb47 | blueswir1 | |
720 | 64a88d5d | blueswir1 | if (cpu_sparc_find_by_name(def, cpu_model) < 0) |
721 | 64a88d5d | blueswir1 | return -1; |
722 | c48fcb47 | blueswir1 | |
723 | 5578ceab | blueswir1 | env->def = qemu_mallocz(sizeof(*def));
|
724 | 5578ceab | blueswir1 | memcpy(env->def, def, sizeof(*def));
|
725 | 5578ceab | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
726 | 5578ceab | blueswir1 | if ((env->def->features & CPU_FEATURE_FLOAT))
|
727 | 5578ceab | blueswir1 | env->def->features |= CPU_FEATURE_FLOAT128; |
728 | 5578ceab | blueswir1 | #endif
|
729 | c48fcb47 | blueswir1 | env->cpu_model_str = cpu_model; |
730 | c48fcb47 | blueswir1 | env->version = def->iu_version; |
731 | c48fcb47 | blueswir1 | env->fsr = def->fpu_version; |
732 | 1a14026e | blueswir1 | env->nwindows = def->nwindows; |
733 | c48fcb47 | blueswir1 | #if !defined(TARGET_SPARC64)
|
734 | c48fcb47 | blueswir1 | env->mmuregs[0] |= def->mmu_version;
|
735 | c48fcb47 | blueswir1 | cpu_sparc_set_id(env, 0);
|
736 | 963262de | blueswir1 | env->mxccregs[7] |= def->mxcc_version;
|
737 | 1a14026e | blueswir1 | #else
|
738 | fb79ceb9 | blueswir1 | env->mmu_version = def->mmu_version; |
739 | c19148bd | blueswir1 | env->maxtl = def->maxtl; |
740 | c19148bd | blueswir1 | env->version |= def->maxtl << 8;
|
741 | 1a14026e | blueswir1 | env->version |= def->nwindows - 1;
|
742 | c48fcb47 | blueswir1 | #endif
|
743 | 64a88d5d | blueswir1 | return 0; |
744 | 64a88d5d | blueswir1 | } |
745 | 64a88d5d | blueswir1 | |
746 | 64a88d5d | blueswir1 | static void cpu_sparc_close(CPUSPARCState *env) |
747 | 64a88d5d | blueswir1 | { |
748 | 5578ceab | blueswir1 | free(env->def); |
749 | 64a88d5d | blueswir1 | free(env); |
750 | 64a88d5d | blueswir1 | } |
751 | 64a88d5d | blueswir1 | |
752 | 64a88d5d | blueswir1 | CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
753 | 64a88d5d | blueswir1 | { |
754 | 64a88d5d | blueswir1 | CPUSPARCState *env; |
755 | 64a88d5d | blueswir1 | |
756 | 64a88d5d | blueswir1 | env = qemu_mallocz(sizeof(CPUSPARCState));
|
757 | 64a88d5d | blueswir1 | cpu_exec_init(env); |
758 | c48fcb47 | blueswir1 | |
759 | c48fcb47 | blueswir1 | gen_intermediate_code_init(env); |
760 | c48fcb47 | blueswir1 | |
761 | 64a88d5d | blueswir1 | if (cpu_sparc_register(env, cpu_model) < 0) { |
762 | 64a88d5d | blueswir1 | cpu_sparc_close(env); |
763 | 64a88d5d | blueswir1 | return NULL; |
764 | 64a88d5d | blueswir1 | } |
765 | c48fcb47 | blueswir1 | cpu_reset(env); |
766 | 0bf46a40 | aliguori | qemu_init_vcpu(env); |
767 | c48fcb47 | blueswir1 | |
768 | c48fcb47 | blueswir1 | return env;
|
769 | c48fcb47 | blueswir1 | } |
770 | c48fcb47 | blueswir1 | |
771 | c48fcb47 | blueswir1 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
772 | c48fcb47 | blueswir1 | { |
773 | c48fcb47 | blueswir1 | #if !defined(TARGET_SPARC64)
|
774 | c48fcb47 | blueswir1 | env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
775 | c48fcb47 | blueswir1 | #endif
|
776 | c48fcb47 | blueswir1 | } |
777 | c48fcb47 | blueswir1 | |
778 | c48fcb47 | blueswir1 | static const sparc_def_t sparc_defs[] = { |
779 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
780 | c48fcb47 | blueswir1 | { |
781 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64",
|
782 | c19148bd | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), |
783 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
784 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
785 | 1a14026e | blueswir1 | .nwindows = 4,
|
786 | c19148bd | blueswir1 | .maxtl = 4,
|
787 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
788 | c48fcb47 | blueswir1 | }, |
789 | c48fcb47 | blueswir1 | { |
790 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64 III",
|
791 | c19148bd | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), |
792 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
793 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
794 | 1a14026e | blueswir1 | .nwindows = 5,
|
795 | c19148bd | blueswir1 | .maxtl = 4,
|
796 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
797 | c48fcb47 | blueswir1 | }, |
798 | c48fcb47 | blueswir1 | { |
799 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64 IV",
|
800 | c19148bd | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), |
801 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
802 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
803 | 1a14026e | blueswir1 | .nwindows = 8,
|
804 | c19148bd | blueswir1 | .maxtl = 5,
|
805 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
806 | c48fcb47 | blueswir1 | }, |
807 | c48fcb47 | blueswir1 | { |
808 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64 V",
|
809 | c19148bd | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), |
810 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
811 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
812 | 1a14026e | blueswir1 | .nwindows = 8,
|
813 | c19148bd | blueswir1 | .maxtl = 5,
|
814 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
815 | c48fcb47 | blueswir1 | }, |
816 | c48fcb47 | blueswir1 | { |
817 | c48fcb47 | blueswir1 | .name = "TI UltraSparc I",
|
818 | c19148bd | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
819 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
820 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
821 | 1a14026e | blueswir1 | .nwindows = 8,
|
822 | c19148bd | blueswir1 | .maxtl = 5,
|
823 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
824 | c48fcb47 | blueswir1 | }, |
825 | c48fcb47 | blueswir1 | { |
826 | c48fcb47 | blueswir1 | .name = "TI UltraSparc II",
|
827 | c19148bd | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), |
828 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
829 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
830 | 1a14026e | blueswir1 | .nwindows = 8,
|
831 | c19148bd | blueswir1 | .maxtl = 5,
|
832 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
833 | c48fcb47 | blueswir1 | }, |
834 | c48fcb47 | blueswir1 | { |
835 | c48fcb47 | blueswir1 | .name = "TI UltraSparc IIi",
|
836 | c19148bd | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), |
837 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
838 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
839 | 1a14026e | blueswir1 | .nwindows = 8,
|
840 | c19148bd | blueswir1 | .maxtl = 5,
|
841 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
842 | c48fcb47 | blueswir1 | }, |
843 | c48fcb47 | blueswir1 | { |
844 | c48fcb47 | blueswir1 | .name = "TI UltraSparc IIe",
|
845 | c19148bd | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), |
846 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
847 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
848 | 1a14026e | blueswir1 | .nwindows = 8,
|
849 | c19148bd | blueswir1 | .maxtl = 5,
|
850 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
851 | c48fcb47 | blueswir1 | }, |
852 | c48fcb47 | blueswir1 | { |
853 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc III",
|
854 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), |
855 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
856 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
857 | 1a14026e | blueswir1 | .nwindows = 8,
|
858 | c19148bd | blueswir1 | .maxtl = 5,
|
859 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
860 | c48fcb47 | blueswir1 | }, |
861 | c48fcb47 | blueswir1 | { |
862 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc III Cu",
|
863 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), |
864 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
865 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_3, |
866 | 1a14026e | blueswir1 | .nwindows = 8,
|
867 | c19148bd | blueswir1 | .maxtl = 5,
|
868 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
869 | c48fcb47 | blueswir1 | }, |
870 | c48fcb47 | blueswir1 | { |
871 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IIIi",
|
872 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), |
873 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
874 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
875 | 1a14026e | blueswir1 | .nwindows = 8,
|
876 | c19148bd | blueswir1 | .maxtl = 5,
|
877 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
878 | c48fcb47 | blueswir1 | }, |
879 | c48fcb47 | blueswir1 | { |
880 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IV",
|
881 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), |
882 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
883 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_4, |
884 | 1a14026e | blueswir1 | .nwindows = 8,
|
885 | c19148bd | blueswir1 | .maxtl = 5,
|
886 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
887 | c48fcb47 | blueswir1 | }, |
888 | c48fcb47 | blueswir1 | { |
889 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IV+",
|
890 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), |
891 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
892 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
893 | 1a14026e | blueswir1 | .nwindows = 8,
|
894 | c19148bd | blueswir1 | .maxtl = 5,
|
895 | fb79ceb9 | blueswir1 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, |
896 | c48fcb47 | blueswir1 | }, |
897 | c48fcb47 | blueswir1 | { |
898 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IIIi+",
|
899 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), |
900 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
901 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_3, |
902 | 1a14026e | blueswir1 | .nwindows = 8,
|
903 | c19148bd | blueswir1 | .maxtl = 5,
|
904 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
905 | c48fcb47 | blueswir1 | }, |
906 | c48fcb47 | blueswir1 | { |
907 | c7ba218d | blueswir1 | .name = "Sun UltraSparc T1",
|
908 | c7ba218d | blueswir1 | // defined in sparc_ifu_fdp.v and ctu.h
|
909 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), |
910 | c7ba218d | blueswir1 | .fpu_version = 0x00000000,
|
911 | c7ba218d | blueswir1 | .mmu_version = mmu_sun4v, |
912 | c7ba218d | blueswir1 | .nwindows = 8,
|
913 | c19148bd | blueswir1 | .maxtl = 6,
|
914 | c7ba218d | blueswir1 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
915 | c7ba218d | blueswir1 | | CPU_FEATURE_GL, |
916 | c7ba218d | blueswir1 | }, |
917 | c7ba218d | blueswir1 | { |
918 | c7ba218d | blueswir1 | .name = "Sun UltraSparc T2",
|
919 | c7ba218d | blueswir1 | // defined in tlu_asi_ctl.v and n2_revid_cust.v
|
920 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), |
921 | c7ba218d | blueswir1 | .fpu_version = 0x00000000,
|
922 | c7ba218d | blueswir1 | .mmu_version = mmu_sun4v, |
923 | c7ba218d | blueswir1 | .nwindows = 8,
|
924 | c19148bd | blueswir1 | .maxtl = 6,
|
925 | c7ba218d | blueswir1 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
926 | c7ba218d | blueswir1 | | CPU_FEATURE_GL, |
927 | c7ba218d | blueswir1 | }, |
928 | c7ba218d | blueswir1 | { |
929 | c48fcb47 | blueswir1 | .name = "NEC UltraSparc I",
|
930 | c19148bd | blueswir1 | .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
931 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
932 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
933 | 1a14026e | blueswir1 | .nwindows = 8,
|
934 | c19148bd | blueswir1 | .maxtl = 5,
|
935 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
936 | c48fcb47 | blueswir1 | }, |
937 | c48fcb47 | blueswir1 | #else
|
938 | c48fcb47 | blueswir1 | { |
939 | c48fcb47 | blueswir1 | .name = "Fujitsu MB86900",
|
940 | c48fcb47 | blueswir1 | .iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
941 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
942 | c48fcb47 | blueswir1 | .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
943 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
944 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
945 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
946 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
947 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
948 | 1a14026e | blueswir1 | .nwindows = 7,
|
949 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD, |
950 | c48fcb47 | blueswir1 | }, |
951 | c48fcb47 | blueswir1 | { |
952 | c48fcb47 | blueswir1 | .name = "Fujitsu MB86904",
|
953 | c48fcb47 | blueswir1 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
954 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
955 | c48fcb47 | blueswir1 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
956 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
957 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
958 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
959 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
960 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
961 | 1a14026e | blueswir1 | .nwindows = 8,
|
962 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
963 | c48fcb47 | blueswir1 | }, |
964 | c48fcb47 | blueswir1 | { |
965 | c48fcb47 | blueswir1 | .name = "Fujitsu MB86907",
|
966 | c48fcb47 | blueswir1 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
967 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
968 | c48fcb47 | blueswir1 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
969 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
970 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
971 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
972 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
973 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
974 | 1a14026e | blueswir1 | .nwindows = 8,
|
975 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
976 | c48fcb47 | blueswir1 | }, |
977 | c48fcb47 | blueswir1 | { |
978 | c48fcb47 | blueswir1 | .name = "LSI L64811",
|
979 | c48fcb47 | blueswir1 | .iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
980 | c48fcb47 | blueswir1 | .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
981 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
982 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
983 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
984 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
985 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
986 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
987 | 1a14026e | blueswir1 | .nwindows = 8,
|
988 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
989 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
990 | c48fcb47 | blueswir1 | }, |
991 | c48fcb47 | blueswir1 | { |
992 | c48fcb47 | blueswir1 | .name = "Cypress CY7C601",
|
993 | c48fcb47 | blueswir1 | .iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
994 | c48fcb47 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
995 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
996 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
997 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
998 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
999 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1000 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1001 | 1a14026e | blueswir1 | .nwindows = 8,
|
1002 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1003 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
1004 | c48fcb47 | blueswir1 | }, |
1005 | c48fcb47 | blueswir1 | { |
1006 | c48fcb47 | blueswir1 | .name = "Cypress CY7C611",
|
1007 | c48fcb47 | blueswir1 | .iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
1008 | c48fcb47 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
1009 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
1010 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1011 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1012 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1013 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1014 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1015 | 1a14026e | blueswir1 | .nwindows = 8,
|
1016 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1017 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
1018 | c48fcb47 | blueswir1 | }, |
1019 | c48fcb47 | blueswir1 | { |
1020 | c48fcb47 | blueswir1 | .name = "TI MicroSparc I",
|
1021 | c48fcb47 | blueswir1 | .iu_version = 0x41000000,
|
1022 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, |
1023 | c48fcb47 | blueswir1 | .mmu_version = 0x41000000,
|
1024 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1025 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1026 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1027 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
1028 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x0000003f,
|
1029 | 1a14026e | blueswir1 | .nwindows = 7,
|
1030 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | |
1031 | e30b4678 | blueswir1 | CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | |
1032 | e30b4678 | blueswir1 | CPU_FEATURE_FMUL, |
1033 | c48fcb47 | blueswir1 | }, |
1034 | c48fcb47 | blueswir1 | { |
1035 | c48fcb47 | blueswir1 | .name = "TI MicroSparc II",
|
1036 | c48fcb47 | blueswir1 | .iu_version = 0x42000000,
|
1037 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, |
1038 | c48fcb47 | blueswir1 | .mmu_version = 0x02000000,
|
1039 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1040 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
1041 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
1042 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
1043 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
1044 | 1a14026e | blueswir1 | .nwindows = 8,
|
1045 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1046 | c48fcb47 | blueswir1 | }, |
1047 | c48fcb47 | blueswir1 | { |
1048 | c48fcb47 | blueswir1 | .name = "TI MicroSparc IIep",
|
1049 | c48fcb47 | blueswir1 | .iu_version = 0x42000000,
|
1050 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, |
1051 | c48fcb47 | blueswir1 | .mmu_version = 0x04000000,
|
1052 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1053 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
1054 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
1055 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016bff,
|
1056 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
1057 | 1a14026e | blueswir1 | .nwindows = 8,
|
1058 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1059 | c48fcb47 | blueswir1 | }, |
1060 | c48fcb47 | blueswir1 | { |
1061 | b5154bde | blueswir1 | .name = "TI SuperSparc 40", // STP1020NPGA |
1062 | 963262de | blueswir1 | .iu_version = 0x41000000, // SuperSPARC 2.x |
1063 | b5154bde | blueswir1 | .fpu_version = 0 << 17, |
1064 | 963262de | blueswir1 | .mmu_version = 0x00000800, // SuperSPARC 2.x, no MXCC |
1065 | b5154bde | blueswir1 | .mmu_bm = 0x00002000,
|
1066 | b5154bde | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1067 | b5154bde | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1068 | b5154bde | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1069 | b5154bde | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1070 | 1a14026e | blueswir1 | .nwindows = 8,
|
1071 | b5154bde | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1072 | b5154bde | blueswir1 | }, |
1073 | b5154bde | blueswir1 | { |
1074 | b5154bde | blueswir1 | .name = "TI SuperSparc 50", // STP1020PGA |
1075 | 963262de | blueswir1 | .iu_version = 0x40000000, // SuperSPARC 3.x |
1076 | b5154bde | blueswir1 | .fpu_version = 0 << 17, |
1077 | 963262de | blueswir1 | .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC |
1078 | b5154bde | blueswir1 | .mmu_bm = 0x00002000,
|
1079 | b5154bde | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1080 | b5154bde | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1081 | b5154bde | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1082 | b5154bde | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1083 | 1a14026e | blueswir1 | .nwindows = 8,
|
1084 | b5154bde | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1085 | b5154bde | blueswir1 | }, |
1086 | b5154bde | blueswir1 | { |
1087 | c48fcb47 | blueswir1 | .name = "TI SuperSparc 51",
|
1088 | 963262de | blueswir1 | .iu_version = 0x40000000, // SuperSPARC 3.x |
1089 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
1090 | 963262de | blueswir1 | .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC |
1091 | c48fcb47 | blueswir1 | .mmu_bm = 0x00002000,
|
1092 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1093 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1094 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1095 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1096 | 963262de | blueswir1 | .mxcc_version = 0x00000104,
|
1097 | 1a14026e | blueswir1 | .nwindows = 8,
|
1098 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1099 | c48fcb47 | blueswir1 | }, |
1100 | c48fcb47 | blueswir1 | { |
1101 | b5154bde | blueswir1 | .name = "TI SuperSparc 60", // STP1020APGA |
1102 | 963262de | blueswir1 | .iu_version = 0x40000000, // SuperSPARC 3.x |
1103 | b5154bde | blueswir1 | .fpu_version = 0 << 17, |
1104 | 963262de | blueswir1 | .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC |
1105 | b5154bde | blueswir1 | .mmu_bm = 0x00002000,
|
1106 | b5154bde | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1107 | b5154bde | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1108 | b5154bde | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1109 | b5154bde | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1110 | 1a14026e | blueswir1 | .nwindows = 8,
|
1111 | b5154bde | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1112 | b5154bde | blueswir1 | }, |
1113 | b5154bde | blueswir1 | { |
1114 | c48fcb47 | blueswir1 | .name = "TI SuperSparc 61",
|
1115 | 963262de | blueswir1 | .iu_version = 0x44000000, // SuperSPARC 3.x |
1116 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
1117 | 963262de | blueswir1 | .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC |
1118 | 963262de | blueswir1 | .mmu_bm = 0x00002000,
|
1119 | 963262de | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1120 | 963262de | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1121 | 963262de | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1122 | 963262de | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1123 | 963262de | blueswir1 | .mxcc_version = 0x00000104,
|
1124 | 963262de | blueswir1 | .nwindows = 8,
|
1125 | 963262de | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1126 | 963262de | blueswir1 | }, |
1127 | 963262de | blueswir1 | { |
1128 | 963262de | blueswir1 | .name = "TI SuperSparc II",
|
1129 | 963262de | blueswir1 | .iu_version = 0x40000000, // SuperSPARC II 1.x |
1130 | 963262de | blueswir1 | .fpu_version = 0 << 17, |
1131 | 963262de | blueswir1 | .mmu_version = 0x08000000, // SuperSPARC II 1.x, MXCC |
1132 | c48fcb47 | blueswir1 | .mmu_bm = 0x00002000,
|
1133 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1134 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1135 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1136 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1137 | 963262de | blueswir1 | .mxcc_version = 0x00000104,
|
1138 | 1a14026e | blueswir1 | .nwindows = 8,
|
1139 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1140 | c48fcb47 | blueswir1 | }, |
1141 | c48fcb47 | blueswir1 | { |
1142 | c48fcb47 | blueswir1 | .name = "Ross RT625",
|
1143 | c48fcb47 | blueswir1 | .iu_version = 0x1e000000,
|
1144 | c48fcb47 | blueswir1 | .fpu_version = 1 << 17, |
1145 | c48fcb47 | blueswir1 | .mmu_version = 0x1e000000,
|
1146 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1147 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1148 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1149 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1150 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1151 | 1a14026e | blueswir1 | .nwindows = 8,
|
1152 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1153 | c48fcb47 | blueswir1 | }, |
1154 | c48fcb47 | blueswir1 | { |
1155 | c48fcb47 | blueswir1 | .name = "Ross RT620",
|
1156 | c48fcb47 | blueswir1 | .iu_version = 0x1f000000,
|
1157 | c48fcb47 | blueswir1 | .fpu_version = 1 << 17, |
1158 | c48fcb47 | blueswir1 | .mmu_version = 0x1f000000,
|
1159 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1160 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1161 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1162 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1163 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1164 | 1a14026e | blueswir1 | .nwindows = 8,
|
1165 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1166 | c48fcb47 | blueswir1 | }, |
1167 | c48fcb47 | blueswir1 | { |
1168 | c48fcb47 | blueswir1 | .name = "BIT B5010",
|
1169 | c48fcb47 | blueswir1 | .iu_version = 0x20000000,
|
1170 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
1171 | c48fcb47 | blueswir1 | .mmu_version = 0x20000000,
|
1172 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1173 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1174 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1175 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1176 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1177 | 1a14026e | blueswir1 | .nwindows = 8,
|
1178 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1179 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
1180 | c48fcb47 | blueswir1 | }, |
1181 | c48fcb47 | blueswir1 | { |
1182 | c48fcb47 | blueswir1 | .name = "Matsushita MN10501",
|
1183 | c48fcb47 | blueswir1 | .iu_version = 0x50000000,
|
1184 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
1185 | c48fcb47 | blueswir1 | .mmu_version = 0x50000000,
|
1186 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1187 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1188 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1189 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1190 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1191 | 1a14026e | blueswir1 | .nwindows = 8,
|
1192 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT | |
1193 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
1194 | c48fcb47 | blueswir1 | }, |
1195 | c48fcb47 | blueswir1 | { |
1196 | c48fcb47 | blueswir1 | .name = "Weitek W8601",
|
1197 | c48fcb47 | blueswir1 | .iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
1198 | c48fcb47 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
1199 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
1200 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1201 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1202 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1203 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1204 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1205 | 1a14026e | blueswir1 | .nwindows = 8,
|
1206 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1207 | c48fcb47 | blueswir1 | }, |
1208 | c48fcb47 | blueswir1 | { |
1209 | c48fcb47 | blueswir1 | .name = "LEON2",
|
1210 | c48fcb47 | blueswir1 | .iu_version = 0xf2000000,
|
1211 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1212 | c48fcb47 | blueswir1 | .mmu_version = 0xf2000000,
|
1213 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1214 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1215 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1216 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1217 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1218 | 1a14026e | blueswir1 | .nwindows = 8,
|
1219 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1220 | c48fcb47 | blueswir1 | }, |
1221 | c48fcb47 | blueswir1 | { |
1222 | c48fcb47 | blueswir1 | .name = "LEON3",
|
1223 | c48fcb47 | blueswir1 | .iu_version = 0xf3000000,
|
1224 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1225 | c48fcb47 | blueswir1 | .mmu_version = 0xf3000000,
|
1226 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1227 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1228 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1229 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1230 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1231 | 1a14026e | blueswir1 | .nwindows = 8,
|
1232 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1233 | c48fcb47 | blueswir1 | }, |
1234 | c48fcb47 | blueswir1 | #endif
|
1235 | c48fcb47 | blueswir1 | }; |
1236 | c48fcb47 | blueswir1 | |
1237 | 64a88d5d | blueswir1 | static const char * const feature_name[] = { |
1238 | 64a88d5d | blueswir1 | "float",
|
1239 | 64a88d5d | blueswir1 | "float128",
|
1240 | 64a88d5d | blueswir1 | "swap",
|
1241 | 64a88d5d | blueswir1 | "mul",
|
1242 | 64a88d5d | blueswir1 | "div",
|
1243 | 64a88d5d | blueswir1 | "flush",
|
1244 | 64a88d5d | blueswir1 | "fsqrt",
|
1245 | 64a88d5d | blueswir1 | "fmul",
|
1246 | 64a88d5d | blueswir1 | "vis1",
|
1247 | 64a88d5d | blueswir1 | "vis2",
|
1248 | e30b4678 | blueswir1 | "fsmuld",
|
1249 | fb79ceb9 | blueswir1 | "hypv",
|
1250 | fb79ceb9 | blueswir1 | "cmt",
|
1251 | fb79ceb9 | blueswir1 | "gl",
|
1252 | 64a88d5d | blueswir1 | }; |
1253 | 64a88d5d | blueswir1 | |
1254 | 64a88d5d | blueswir1 | static void print_features(FILE *f, |
1255 | 64a88d5d | blueswir1 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
1256 | 64a88d5d | blueswir1 | uint32_t features, const char *prefix) |
1257 | c48fcb47 | blueswir1 | { |
1258 | c48fcb47 | blueswir1 | unsigned int i; |
1259 | c48fcb47 | blueswir1 | |
1260 | 64a88d5d | blueswir1 | for (i = 0; i < ARRAY_SIZE(feature_name); i++) |
1261 | 64a88d5d | blueswir1 | if (feature_name[i] && (features & (1 << i))) { |
1262 | 64a88d5d | blueswir1 | if (prefix)
|
1263 | 64a88d5d | blueswir1 | (*cpu_fprintf)(f, "%s", prefix);
|
1264 | 64a88d5d | blueswir1 | (*cpu_fprintf)(f, "%s ", feature_name[i]);
|
1265 | 64a88d5d | blueswir1 | } |
1266 | 64a88d5d | blueswir1 | } |
1267 | 64a88d5d | blueswir1 | |
1268 | 64a88d5d | blueswir1 | static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features) |
1269 | 64a88d5d | blueswir1 | { |
1270 | 64a88d5d | blueswir1 | unsigned int i; |
1271 | 64a88d5d | blueswir1 | |
1272 | 64a88d5d | blueswir1 | for (i = 0; i < ARRAY_SIZE(feature_name); i++) |
1273 | 64a88d5d | blueswir1 | if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
|
1274 | 64a88d5d | blueswir1 | *features |= 1 << i;
|
1275 | 64a88d5d | blueswir1 | return;
|
1276 | 64a88d5d | blueswir1 | } |
1277 | 64a88d5d | blueswir1 | fprintf(stderr, "CPU feature %s not found\n", flagname);
|
1278 | 64a88d5d | blueswir1 | } |
1279 | 64a88d5d | blueswir1 | |
1280 | 22548760 | blueswir1 | static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) |
1281 | 64a88d5d | blueswir1 | { |
1282 | 64a88d5d | blueswir1 | unsigned int i; |
1283 | 64a88d5d | blueswir1 | const sparc_def_t *def = NULL; |
1284 | 64a88d5d | blueswir1 | char *s = strdup(cpu_model);
|
1285 | 64a88d5d | blueswir1 | char *featurestr, *name = strtok(s, ","); |
1286 | 64a88d5d | blueswir1 | uint32_t plus_features = 0;
|
1287 | 64a88d5d | blueswir1 | uint32_t minus_features = 0;
|
1288 | 64a88d5d | blueswir1 | long long iu_version; |
1289 | 1a14026e | blueswir1 | uint32_t fpu_version, mmu_version, nwindows; |
1290 | 64a88d5d | blueswir1 | |
1291 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
1292 | c48fcb47 | blueswir1 | if (strcasecmp(name, sparc_defs[i].name) == 0) { |
1293 | 64a88d5d | blueswir1 | def = &sparc_defs[i]; |
1294 | c48fcb47 | blueswir1 | } |
1295 | c48fcb47 | blueswir1 | } |
1296 | 64a88d5d | blueswir1 | if (!def)
|
1297 | 64a88d5d | blueswir1 | goto error;
|
1298 | 64a88d5d | blueswir1 | memcpy(cpu_def, def, sizeof(*def));
|
1299 | 64a88d5d | blueswir1 | |
1300 | 64a88d5d | blueswir1 | featurestr = strtok(NULL, ","); |
1301 | 64a88d5d | blueswir1 | while (featurestr) {
|
1302 | 64a88d5d | blueswir1 | char *val;
|
1303 | 64a88d5d | blueswir1 | |
1304 | 64a88d5d | blueswir1 | if (featurestr[0] == '+') { |
1305 | 64a88d5d | blueswir1 | add_flagname_to_bitmaps(featurestr + 1, &plus_features);
|
1306 | 64a88d5d | blueswir1 | } else if (featurestr[0] == '-') { |
1307 | 64a88d5d | blueswir1 | add_flagname_to_bitmaps(featurestr + 1, &minus_features);
|
1308 | 64a88d5d | blueswir1 | } else if ((val = strchr(featurestr, '='))) { |
1309 | 64a88d5d | blueswir1 | *val = 0; val++;
|
1310 | 64a88d5d | blueswir1 | if (!strcmp(featurestr, "iu_version")) { |
1311 | 64a88d5d | blueswir1 | char *err;
|
1312 | 64a88d5d | blueswir1 | |
1313 | 64a88d5d | blueswir1 | iu_version = strtoll(val, &err, 0);
|
1314 | 64a88d5d | blueswir1 | if (!*val || *err) {
|
1315 | 64a88d5d | blueswir1 | fprintf(stderr, "bad numerical value %s\n", val);
|
1316 | 64a88d5d | blueswir1 | goto error;
|
1317 | 64a88d5d | blueswir1 | } |
1318 | 64a88d5d | blueswir1 | cpu_def->iu_version = iu_version; |
1319 | 64a88d5d | blueswir1 | #ifdef DEBUG_FEATURES
|
1320 | 64a88d5d | blueswir1 | fprintf(stderr, "iu_version %llx\n", iu_version);
|
1321 | 64a88d5d | blueswir1 | #endif
|
1322 | 64a88d5d | blueswir1 | } else if (!strcmp(featurestr, "fpu_version")) { |
1323 | 64a88d5d | blueswir1 | char *err;
|
1324 | 64a88d5d | blueswir1 | |
1325 | 64a88d5d | blueswir1 | fpu_version = strtol(val, &err, 0);
|
1326 | 64a88d5d | blueswir1 | if (!*val || *err) {
|
1327 | 64a88d5d | blueswir1 | fprintf(stderr, "bad numerical value %s\n", val);
|
1328 | 64a88d5d | blueswir1 | goto error;
|
1329 | 64a88d5d | blueswir1 | } |
1330 | 64a88d5d | blueswir1 | cpu_def->fpu_version = fpu_version; |
1331 | 64a88d5d | blueswir1 | #ifdef DEBUG_FEATURES
|
1332 | 0bf9e31a | Blue Swirl | fprintf(stderr, "fpu_version %x\n", fpu_version);
|
1333 | 64a88d5d | blueswir1 | #endif
|
1334 | 64a88d5d | blueswir1 | } else if (!strcmp(featurestr, "mmu_version")) { |
1335 | 64a88d5d | blueswir1 | char *err;
|
1336 | 64a88d5d | blueswir1 | |
1337 | 64a88d5d | blueswir1 | mmu_version = strtol(val, &err, 0);
|
1338 | 64a88d5d | blueswir1 | if (!*val || *err) {
|
1339 | 64a88d5d | blueswir1 | fprintf(stderr, "bad numerical value %s\n", val);
|
1340 | 64a88d5d | blueswir1 | goto error;
|
1341 | 64a88d5d | blueswir1 | } |
1342 | 64a88d5d | blueswir1 | cpu_def->mmu_version = mmu_version; |
1343 | 64a88d5d | blueswir1 | #ifdef DEBUG_FEATURES
|
1344 | 0bf9e31a | Blue Swirl | fprintf(stderr, "mmu_version %x\n", mmu_version);
|
1345 | 64a88d5d | blueswir1 | #endif
|
1346 | 1a14026e | blueswir1 | } else if (!strcmp(featurestr, "nwindows")) { |
1347 | 1a14026e | blueswir1 | char *err;
|
1348 | 1a14026e | blueswir1 | |
1349 | 1a14026e | blueswir1 | nwindows = strtol(val, &err, 0);
|
1350 | 1a14026e | blueswir1 | if (!*val || *err || nwindows > MAX_NWINDOWS ||
|
1351 | 1a14026e | blueswir1 | nwindows < MIN_NWINDOWS) { |
1352 | 1a14026e | blueswir1 | fprintf(stderr, "bad numerical value %s\n", val);
|
1353 | 1a14026e | blueswir1 | goto error;
|
1354 | 1a14026e | blueswir1 | } |
1355 | 1a14026e | blueswir1 | cpu_def->nwindows = nwindows; |
1356 | 1a14026e | blueswir1 | #ifdef DEBUG_FEATURES
|
1357 | 1a14026e | blueswir1 | fprintf(stderr, "nwindows %d\n", nwindows);
|
1358 | 1a14026e | blueswir1 | #endif
|
1359 | 64a88d5d | blueswir1 | } else {
|
1360 | 64a88d5d | blueswir1 | fprintf(stderr, "unrecognized feature %s\n", featurestr);
|
1361 | 64a88d5d | blueswir1 | goto error;
|
1362 | 64a88d5d | blueswir1 | } |
1363 | 64a88d5d | blueswir1 | } else {
|
1364 | 77f193da | blueswir1 | fprintf(stderr, "feature string `%s' not in format "
|
1365 | 77f193da | blueswir1 | "(+feature|-feature|feature=xyz)\n", featurestr);
|
1366 | 64a88d5d | blueswir1 | goto error;
|
1367 | 64a88d5d | blueswir1 | } |
1368 | 64a88d5d | blueswir1 | featurestr = strtok(NULL, ","); |
1369 | 64a88d5d | blueswir1 | } |
1370 | 64a88d5d | blueswir1 | cpu_def->features |= plus_features; |
1371 | 64a88d5d | blueswir1 | cpu_def->features &= ~minus_features; |
1372 | 64a88d5d | blueswir1 | #ifdef DEBUG_FEATURES
|
1373 | 64a88d5d | blueswir1 | print_features(stderr, fprintf, cpu_def->features, NULL);
|
1374 | 64a88d5d | blueswir1 | #endif
|
1375 | 64a88d5d | blueswir1 | free(s); |
1376 | 64a88d5d | blueswir1 | return 0; |
1377 | 64a88d5d | blueswir1 | |
1378 | 64a88d5d | blueswir1 | error:
|
1379 | 64a88d5d | blueswir1 | free(s); |
1380 | 64a88d5d | blueswir1 | return -1; |
1381 | c48fcb47 | blueswir1 | } |
1382 | c48fcb47 | blueswir1 | |
1383 | 77f193da | blueswir1 | void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
1384 | c48fcb47 | blueswir1 | { |
1385 | c48fcb47 | blueswir1 | unsigned int i; |
1386 | c48fcb47 | blueswir1 | |
1387 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
1388 | 1a14026e | blueswir1 | (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ", |
1389 | c48fcb47 | blueswir1 | sparc_defs[i].name, |
1390 | c48fcb47 | blueswir1 | sparc_defs[i].iu_version, |
1391 | c48fcb47 | blueswir1 | sparc_defs[i].fpu_version, |
1392 | 1a14026e | blueswir1 | sparc_defs[i].mmu_version, |
1393 | 1a14026e | blueswir1 | sparc_defs[i].nwindows); |
1394 | 77f193da | blueswir1 | print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & |
1395 | 77f193da | blueswir1 | ~sparc_defs[i].features, "-");
|
1396 | 77f193da | blueswir1 | print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & |
1397 | 77f193da | blueswir1 | sparc_defs[i].features, "+");
|
1398 | 64a88d5d | blueswir1 | (*cpu_fprintf)(f, "\n");
|
1399 | c48fcb47 | blueswir1 | } |
1400 | f76981b1 | blueswir1 | (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
|
1401 | f76981b1 | blueswir1 | print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
|
1402 | 64a88d5d | blueswir1 | (*cpu_fprintf)(f, "\n");
|
1403 | f76981b1 | blueswir1 | (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
|
1404 | f76981b1 | blueswir1 | print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
|
1405 | f76981b1 | blueswir1 | (*cpu_fprintf)(f, "\n");
|
1406 | f76981b1 | blueswir1 | (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
|
1407 | f76981b1 | blueswir1 | "fpu_version mmu_version nwindows\n");
|
1408 | c48fcb47 | blueswir1 | } |
1409 | c48fcb47 | blueswir1 | |
1410 | c48fcb47 | blueswir1 | void cpu_dump_state(CPUState *env, FILE *f,
|
1411 | c48fcb47 | blueswir1 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
1412 | c48fcb47 | blueswir1 | int flags)
|
1413 | c48fcb47 | blueswir1 | { |
1414 | c48fcb47 | blueswir1 | int i, x;
|
1415 | c48fcb47 | blueswir1 | |
1416 | 77f193da | blueswir1 | cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, |
1417 | 77f193da | blueswir1 | env->npc); |
1418 | c48fcb47 | blueswir1 | cpu_fprintf(f, "General Registers:\n");
|
1419 | c48fcb47 | blueswir1 | for (i = 0; i < 4; i++) |
1420 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
1421 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1422 | c48fcb47 | blueswir1 | for (; i < 8; i++) |
1423 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
1424 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\nCurrent Register Window:\n");
|
1425 | c48fcb47 | blueswir1 | for (x = 0; x < 3; x++) { |
1426 | c48fcb47 | blueswir1 | for (i = 0; i < 4; i++) |
1427 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
1428 | c48fcb47 | blueswir1 | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
1429 | c48fcb47 | blueswir1 | env->regwptr[i + x * 8]);
|
1430 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1431 | c48fcb47 | blueswir1 | for (; i < 8; i++) |
1432 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
1433 | c48fcb47 | blueswir1 | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
1434 | c48fcb47 | blueswir1 | env->regwptr[i + x * 8]);
|
1435 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1436 | c48fcb47 | blueswir1 | } |
1437 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\nFloating Point Registers:\n");
|
1438 | c48fcb47 | blueswir1 | for (i = 0; i < 32; i++) { |
1439 | c48fcb47 | blueswir1 | if ((i & 3) == 0) |
1440 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%f%02d:", i);
|
1441 | a37ee56c | blueswir1 | cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]); |
1442 | c48fcb47 | blueswir1 | if ((i & 3) == 3) |
1443 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1444 | c48fcb47 | blueswir1 | } |
1445 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
1446 | c48fcb47 | blueswir1 | cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
|
1447 | c48fcb47 | blueswir1 | env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
1448 | 77f193da | blueswir1 | cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
|
1449 | 77f193da | blueswir1 | "cleanwin %d cwp %d\n",
|
1450 | c48fcb47 | blueswir1 | env->cansave, env->canrestore, env->otherwin, env->wstate, |
1451 | 1a14026e | blueswir1 | env->cleanwin, env->nwindows - 1 - env->cwp);
|
1452 | c48fcb47 | blueswir1 | #else
|
1453 | d78f3995 | blueswir1 | |
1454 | d78f3995 | blueswir1 | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
1455 | d78f3995 | blueswir1 | |
1456 | 77f193da | blueswir1 | cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
|
1457 | 77f193da | blueswir1 | GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
1458 | 77f193da | blueswir1 | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
1459 | 77f193da | blueswir1 | env->psrs?'S':'-', env->psrps?'P':'-', |
1460 | 77f193da | blueswir1 | env->psret?'E':'-', env->wim); |
1461 | c48fcb47 | blueswir1 | #endif
|
1462 | 3a3b925d | blueswir1 | cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr);
|
1463 | c48fcb47 | blueswir1 | } |