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/*
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 *  i386 micro operations
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 * 
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "exec-i386.h"
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/* NOTE: data are not static to force relocation generation by GCC */
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uint8_t parity_table[256] = {
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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};
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/* modulo 17 table */
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const uint8_t rclw_table[32] = {
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    0, 1, 2, 3, 4, 5, 6, 7, 
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    8, 9,10,11,12,13,14,15,
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   16, 0, 1, 2, 3, 4, 5, 6,
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    7, 8, 9,10,11,12,13,14,
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};
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/* modulo 9 table */
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const uint8_t rclb_table[32] = {
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    0, 1, 2, 3, 4, 5, 6, 7, 
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    8, 0, 1, 2, 3, 4, 5, 6,
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    7, 8, 0, 1, 2, 3, 4, 5, 
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    6, 7, 8, 0, 1, 2, 3, 4,
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};
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#ifdef USE_X86LDOUBLE
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/* an array of Intel 80-bit FP constants, to be loaded via integer ops */
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typedef unsigned short f15ld[5];
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const f15ld f15rk[] =
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{
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/*0*/        {0x0000,0x0000,0x0000,0x0000,0x0000},
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/*1*/        {0x0000,0x0000,0x0000,0x8000,0x3fff},
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/*pi*/        {0xc235,0x2168,0xdaa2,0xc90f,0x4000},
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/*lg2*/        {0xf799,0xfbcf,0x9a84,0x9a20,0x3ffd},
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/*ln2*/        {0x79ac,0xd1cf,0x17f7,0xb172,0x3ffe},
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/*l2e*/        {0xf0bc,0x5c17,0x3b29,0xb8aa,0x3fff},
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/*l2t*/        {0x8afe,0xcd1b,0x784b,0xd49a,0x4000}
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};
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#else
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/* the same, 64-bit version */
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typedef unsigned short f15ld[4];
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const f15ld f15rk[] =
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{
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#ifndef WORDS_BIGENDIAN
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/*0*/        {0x0000,0x0000,0x0000,0x0000},
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/*1*/        {0x0000,0x0000,0x0000,0x3ff0},
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/*pi*/        {0x2d18,0x5444,0x21fb,0x4009},
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/*lg2*/        {0x79ff,0x509f,0x4413,0x3fd3},
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/*ln2*/        {0x39ef,0xfefa,0x2e42,0x3fe6},
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/*l2e*/        {0x82fe,0x652b,0x1547,0x3ff7},
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/*l2t*/        {0xa371,0x0979,0x934f,0x400a}
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#else
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/*0*/   {0x0000,0x0000,0x0000,0x0000},
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/*1*/   {0x3ff0,0x0000,0x0000,0x0000},
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/*pi*/  {0x4009,0x21fb,0x5444,0x2d18},
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/*lg2*/        {0x3fd3,0x4413,0x509f,0x79ff},
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/*ln2*/        {0x3fe6,0x2e42,0xfefa,0x39ef},
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/*l2e*/        {0x3ff7,0x1547,0x652b,0x82fe},
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/*l2t*/        {0x400a,0x934f,0x0979,0xa371}
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#endif
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};
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#endif
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/* n must be a constant to be efficient */
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static inline int lshift(int x, int n)
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{
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    if (n >= 0)
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        return x << n;
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    else
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        return x >> (-n);
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}
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/* we define the various pieces of code used by the JIT */
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#define REG EAX
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#define REGNAME _EAX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG ECX
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#define REGNAME _ECX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EDX
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#define REGNAME _EDX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EBX
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#define REGNAME _EBX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG ESP
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#define REGNAME _ESP
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EBP
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#define REGNAME _EBP
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG ESI
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#define REGNAME _ESI
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EDI
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#define REGNAME _EDI
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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/* operations with flags */
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void OPPROTO op_addl_T0_T1_cc(void)
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{
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    CC_SRC = T0;
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    T0 += T1;
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    CC_DST = T0;
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}
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void OPPROTO op_orl_T0_T1_cc(void)
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{
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    T0 |= T1;
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    CC_DST = T0;
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}
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void OPPROTO op_andl_T0_T1_cc(void)
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{
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    T0 &= T1;
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    CC_DST = T0;
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}
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void OPPROTO op_subl_T0_T1_cc(void)
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{
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    CC_SRC = T0;
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    T0 -= T1;
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    CC_DST = T0;
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}
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void OPPROTO op_xorl_T0_T1_cc(void)
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{
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    T0 ^= T1;
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    CC_DST = T0;
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}
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void OPPROTO op_cmpl_T0_T1_cc(void)
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{
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    CC_SRC = T0;
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    CC_DST = T0 - T1;
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}
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void OPPROTO op_negl_T0_cc(void)
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{
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    CC_SRC = 0;
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    T0 = -T0;
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    CC_DST = T0;
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}
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void OPPROTO op_incl_T0_cc(void)
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{
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    CC_SRC = cc_table[CC_OP].compute_c();
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    T0++;
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    CC_DST = T0;
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}
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void OPPROTO op_decl_T0_cc(void)
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{
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    CC_SRC = cc_table[CC_OP].compute_c();
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    T0--;
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    CC_DST = T0;
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}
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void OPPROTO op_testl_T0_T1_cc(void)
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{
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    CC_DST = T0 & T1;
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}
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/* operations without flags */
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void OPPROTO op_addl_T0_T1(void)
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{
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    T0 += T1;
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}
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void OPPROTO op_orl_T0_T1(void)
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{
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    T0 |= T1;
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}
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void OPPROTO op_andl_T0_T1(void)
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{
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    T0 &= T1;
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}
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void OPPROTO op_subl_T0_T1(void)
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{
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    T0 -= T1;
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}
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void OPPROTO op_xorl_T0_T1(void)
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{
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    T0 ^= T1;
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}
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void OPPROTO op_negl_T0(void)
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{
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    T0 = -T0;
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}
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void OPPROTO op_incl_T0(void)
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{
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    T0++;
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}
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void OPPROTO op_decl_T0(void)
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{
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    T0--;
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}
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void OPPROTO op_notl_T0(void)
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{
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    T0 = ~T0;
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}
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void OPPROTO op_bswapl_T0(void)
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{
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    T0 = bswap32(T0);
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}
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/* multiply/divide */
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void OPPROTO op_mulb_AL_T0(void)
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{
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    unsigned int res;
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    res = (uint8_t)EAX * (uint8_t)T0;
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    EAX = (EAX & 0xffff0000) | res;
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    CC_SRC = (res & 0xff00);
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}
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void OPPROTO op_imulb_AL_T0(void)
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{
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    int res;
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    res = (int8_t)EAX * (int8_t)T0;
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    EAX = (EAX & 0xffff0000) | (res & 0xffff);
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    CC_SRC = (res != (int8_t)res);
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}
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void OPPROTO op_mulw_AX_T0(void)
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{
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    unsigned int res;
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    res = (uint16_t)EAX * (uint16_t)T0;
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    EAX = (EAX & 0xffff0000) | (res & 0xffff);
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    EDX = (EDX & 0xffff0000) | ((res >> 16) & 0xffff);
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    CC_SRC = res >> 16;
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}
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void OPPROTO op_imulw_AX_T0(void)
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{
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    int res;
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    res = (int16_t)EAX * (int16_t)T0;
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    EAX = (EAX & 0xffff0000) | (res & 0xffff);
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    EDX = (EDX & 0xffff0000) | ((res >> 16) & 0xffff);
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    CC_SRC = (res != (int16_t)res);
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}
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void OPPROTO op_mull_EAX_T0(void)
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{
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    uint64_t res;
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    res = (uint64_t)((uint32_t)EAX) * (uint64_t)((uint32_t)T0);
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    EAX = res;
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    EDX = res >> 32;
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    CC_SRC = res >> 32;
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}
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void OPPROTO op_imull_EAX_T0(void)
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{
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    int64_t res;
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    res = (int64_t)((int32_t)EAX) * (int64_t)((int32_t)T0);
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    EAX = res;
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    EDX = res >> 32;
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    CC_SRC = (res != (int32_t)res);
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}
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void OPPROTO op_imulw_T0_T1(void)
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{
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    int res;
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    res = (int16_t)T0 * (int16_t)T1;
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    T0 = res;
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    CC_SRC = (res != (int16_t)res);
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}
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void OPPROTO op_imull_T0_T1(void)
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{
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    int64_t res;
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    res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1);
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    T0 = res;
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    CC_SRC = (res != (int32_t)res);
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}
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/* division, flags are undefined */
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/* XXX: add exceptions for overflow */
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void OPPROTO op_divb_AL_T0(void)
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{
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    unsigned int num, den, q, r;
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    num = (EAX & 0xffff);
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    den = (T0 & 0xff);
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    if (den == 0)
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        raise_exception(EXCP00_DIVZ);
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    q = (num / den) & 0xff;
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    r = (num % den) & 0xff;
371 7bfdb6d1 bellard
    EAX = (EAX & 0xffff0000) | (r << 8) | q;
372 7bfdb6d1 bellard
}
373 7bfdb6d1 bellard
374 7bfdb6d1 bellard
void OPPROTO op_idivb_AL_T0(void)
375 7bfdb6d1 bellard
{
376 7bfdb6d1 bellard
    int num, den, q, r;
377 7bfdb6d1 bellard
378 7bfdb6d1 bellard
    num = (int16_t)EAX;
379 7bfdb6d1 bellard
    den = (int8_t)T0;
380 9de5e440 bellard
    if (den == 0)
381 9de5e440 bellard
        raise_exception(EXCP00_DIVZ);
382 7bfdb6d1 bellard
    q = (num / den) & 0xff;
383 7bfdb6d1 bellard
    r = (num % den) & 0xff;
384 7bfdb6d1 bellard
    EAX = (EAX & 0xffff0000) | (r << 8) | q;
385 7bfdb6d1 bellard
}
386 7bfdb6d1 bellard
387 7bfdb6d1 bellard
void OPPROTO op_divw_AX_T0(void)
388 7bfdb6d1 bellard
{
389 7bfdb6d1 bellard
    unsigned int num, den, q, r;
390 7bfdb6d1 bellard
391 7bfdb6d1 bellard
    num = (EAX & 0xffff) | ((EDX & 0xffff) << 16);
392 7bfdb6d1 bellard
    den = (T0 & 0xffff);
393 9de5e440 bellard
    if (den == 0)
394 9de5e440 bellard
        raise_exception(EXCP00_DIVZ);
395 7bfdb6d1 bellard
    q = (num / den) & 0xffff;
396 7bfdb6d1 bellard
    r = (num % den) & 0xffff;
397 7bfdb6d1 bellard
    EAX = (EAX & 0xffff0000) | q;
398 7bfdb6d1 bellard
    EDX = (EDX & 0xffff0000) | r;
399 7bfdb6d1 bellard
}
400 7bfdb6d1 bellard
401 7bfdb6d1 bellard
void OPPROTO op_idivw_AX_T0(void)
402 7bfdb6d1 bellard
{
403 7bfdb6d1 bellard
    int num, den, q, r;
404 7bfdb6d1 bellard
405 7bfdb6d1 bellard
    num = (EAX & 0xffff) | ((EDX & 0xffff) << 16);
406 7bfdb6d1 bellard
    den = (int16_t)T0;
407 9de5e440 bellard
    if (den == 0)
408 9de5e440 bellard
        raise_exception(EXCP00_DIVZ);
409 7bfdb6d1 bellard
    q = (num / den) & 0xffff;
410 7bfdb6d1 bellard
    r = (num % den) & 0xffff;
411 7bfdb6d1 bellard
    EAX = (EAX & 0xffff0000) | q;
412 7bfdb6d1 bellard
    EDX = (EDX & 0xffff0000) | r;
413 7bfdb6d1 bellard
}
414 7bfdb6d1 bellard
415 51fe6890 bellard
#ifdef BUGGY_GCC_DIV64
416 51fe6890 bellard
/* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
417 51fe6890 bellard
   call it from another function */
418 51fe6890 bellard
uint32_t div64(uint32_t *q_ptr, uint64_t num, uint32_t den)
419 51fe6890 bellard
{
420 51fe6890 bellard
    *q_ptr = num / den;
421 51fe6890 bellard
    return num % den;
422 51fe6890 bellard
}
423 51fe6890 bellard
424 51fe6890 bellard
int32_t idiv64(int32_t *q_ptr, int64_t num, int32_t den)
425 51fe6890 bellard
{
426 51fe6890 bellard
    *q_ptr = num / den;
427 51fe6890 bellard
    return num % den;
428 51fe6890 bellard
}
429 51fe6890 bellard
#endif
430 51fe6890 bellard
431 7bfdb6d1 bellard
void OPPROTO op_divl_EAX_T0(void)
432 7bfdb6d1 bellard
{
433 7bfdb6d1 bellard
    unsigned int den, q, r;
434 7bfdb6d1 bellard
    uint64_t num;
435 7bfdb6d1 bellard
    
436 7bfdb6d1 bellard
    num = EAX | ((uint64_t)EDX << 32);
437 7bfdb6d1 bellard
    den = T0;
438 9de5e440 bellard
    if (den == 0)
439 9de5e440 bellard
        raise_exception(EXCP00_DIVZ);
440 51fe6890 bellard
#ifdef BUGGY_GCC_DIV64
441 51fe6890 bellard
    r = div64(&q, num, den);
442 51fe6890 bellard
#else
443 7bfdb6d1 bellard
    q = (num / den);
444 7bfdb6d1 bellard
    r = (num % den);
445 51fe6890 bellard
#endif
446 7bfdb6d1 bellard
    EAX = q;
447 7bfdb6d1 bellard
    EDX = r;
448 7bfdb6d1 bellard
}
449 7bfdb6d1 bellard
450 7bfdb6d1 bellard
void OPPROTO op_idivl_EAX_T0(void)
451 7bfdb6d1 bellard
{
452 7bfdb6d1 bellard
    int den, q, r;
453 4b74fe1f bellard
    int64_t num;
454 7bfdb6d1 bellard
    
455 7bfdb6d1 bellard
    num = EAX | ((uint64_t)EDX << 32);
456 4b74fe1f bellard
    den = T0;
457 9de5e440 bellard
    if (den == 0)
458 9de5e440 bellard
        raise_exception(EXCP00_DIVZ);
459 51fe6890 bellard
#ifdef BUGGY_GCC_DIV64
460 51fe6890 bellard
    r = idiv64(&q, num, den);
461 51fe6890 bellard
#else
462 7bfdb6d1 bellard
    q = (num / den);
463 7bfdb6d1 bellard
    r = (num % den);
464 51fe6890 bellard
#endif
465 7bfdb6d1 bellard
    EAX = q;
466 7bfdb6d1 bellard
    EDX = r;
467 7bfdb6d1 bellard
}
468 7bfdb6d1 bellard
469 dab2ed99 bellard
/* constant load & misc op */
470 7bfdb6d1 bellard
471 ba1c6e37 bellard
void OPPROTO op_movl_T0_im(void)
472 7bfdb6d1 bellard
{
473 7bfdb6d1 bellard
    T0 = PARAM1;
474 7bfdb6d1 bellard
}
475 7bfdb6d1 bellard
476 dab2ed99 bellard
void OPPROTO op_addl_T0_im(void)
477 dab2ed99 bellard
{
478 dab2ed99 bellard
    T0 += PARAM1;
479 dab2ed99 bellard
}
480 dab2ed99 bellard
481 dab2ed99 bellard
void OPPROTO op_andl_T0_ffff(void)
482 dab2ed99 bellard
{
483 dab2ed99 bellard
    T0 = T0 & 0xffff;
484 dab2ed99 bellard
}
485 dab2ed99 bellard
486 dab2ed99 bellard
void OPPROTO op_movl_T0_T1(void)
487 dab2ed99 bellard
{
488 dab2ed99 bellard
    T0 = T1;
489 dab2ed99 bellard
}
490 dab2ed99 bellard
491 ba1c6e37 bellard
void OPPROTO op_movl_T1_im(void)
492 7bfdb6d1 bellard
{
493 7bfdb6d1 bellard
    T1 = PARAM1;
494 7bfdb6d1 bellard
}
495 7bfdb6d1 bellard
496 dab2ed99 bellard
void OPPROTO op_addl_T1_im(void)
497 dab2ed99 bellard
{
498 dab2ed99 bellard
    T1 += PARAM1;
499 dab2ed99 bellard
}
500 dab2ed99 bellard
501 dab2ed99 bellard
void OPPROTO op_movl_T1_A0(void)
502 dab2ed99 bellard
{
503 dab2ed99 bellard
    T1 = A0;
504 dab2ed99 bellard
}
505 dab2ed99 bellard
506 ba1c6e37 bellard
void OPPROTO op_movl_A0_im(void)
507 7bfdb6d1 bellard
{
508 7bfdb6d1 bellard
    A0 = PARAM1;
509 7bfdb6d1 bellard
}
510 7bfdb6d1 bellard
511 4b74fe1f bellard
void OPPROTO op_addl_A0_im(void)
512 4b74fe1f bellard
{
513 4b74fe1f bellard
    A0 += PARAM1;
514 4b74fe1f bellard
}
515 4b74fe1f bellard
516 31bb950b bellard
void OPPROTO op_addl_A0_AL(void)
517 31bb950b bellard
{
518 31bb950b bellard
    A0 += (EAX & 0xff);
519 31bb950b bellard
}
520 31bb950b bellard
521 4b74fe1f bellard
void OPPROTO op_andl_A0_ffff(void)
522 4b74fe1f bellard
{
523 4b74fe1f bellard
    A0 = A0 & 0xffff;
524 4b74fe1f bellard
}
525 4b74fe1f bellard
526 7bfdb6d1 bellard
/* memory access */
527 7bfdb6d1 bellard
528 7bfdb6d1 bellard
void OPPROTO op_ldub_T0_A0(void)
529 7bfdb6d1 bellard
{
530 7bfdb6d1 bellard
    T0 = ldub((uint8_t *)A0);
531 7bfdb6d1 bellard
}
532 7bfdb6d1 bellard
533 7bfdb6d1 bellard
void OPPROTO op_ldsb_T0_A0(void)
534 7bfdb6d1 bellard
{
535 7bfdb6d1 bellard
    T0 = ldsb((int8_t *)A0);
536 7bfdb6d1 bellard
}
537 7bfdb6d1 bellard
538 7bfdb6d1 bellard
void OPPROTO op_lduw_T0_A0(void)
539 7bfdb6d1 bellard
{
540 7bfdb6d1 bellard
    T0 = lduw((uint8_t *)A0);
541 7bfdb6d1 bellard
}
542 7bfdb6d1 bellard
543 7bfdb6d1 bellard
void OPPROTO op_ldsw_T0_A0(void)
544 7bfdb6d1 bellard
{
545 7bfdb6d1 bellard
    T0 = ldsw((int8_t *)A0);
546 7bfdb6d1 bellard
}
547 7bfdb6d1 bellard
548 7bfdb6d1 bellard
void OPPROTO op_ldl_T0_A0(void)
549 7bfdb6d1 bellard
{
550 7bfdb6d1 bellard
    T0 = ldl((uint8_t *)A0);
551 7bfdb6d1 bellard
}
552 7bfdb6d1 bellard
553 7bfdb6d1 bellard
void OPPROTO op_ldub_T1_A0(void)
554 7bfdb6d1 bellard
{
555 7bfdb6d1 bellard
    T1 = ldub((uint8_t *)A0);
556 7bfdb6d1 bellard
}
557 7bfdb6d1 bellard
558 7bfdb6d1 bellard
void OPPROTO op_ldsb_T1_A0(void)
559 7bfdb6d1 bellard
{
560 7bfdb6d1 bellard
    T1 = ldsb((int8_t *)A0);
561 7bfdb6d1 bellard
}
562 7bfdb6d1 bellard
563 7bfdb6d1 bellard
void OPPROTO op_lduw_T1_A0(void)
564 7bfdb6d1 bellard
{
565 7bfdb6d1 bellard
    T1 = lduw((uint8_t *)A0);
566 7bfdb6d1 bellard
}
567 7bfdb6d1 bellard
568 7bfdb6d1 bellard
void OPPROTO op_ldsw_T1_A0(void)
569 7bfdb6d1 bellard
{
570 7bfdb6d1 bellard
    T1 = ldsw((int8_t *)A0);
571 7bfdb6d1 bellard
}
572 7bfdb6d1 bellard
573 7bfdb6d1 bellard
void OPPROTO op_ldl_T1_A0(void)
574 7bfdb6d1 bellard
{
575 7bfdb6d1 bellard
    T1 = ldl((uint8_t *)A0);
576 7bfdb6d1 bellard
}
577 7bfdb6d1 bellard
578 7bfdb6d1 bellard
void OPPROTO op_stb_T0_A0(void)
579 7bfdb6d1 bellard
{
580 7bfdb6d1 bellard
    stb((uint8_t *)A0, T0);
581 7bfdb6d1 bellard
}
582 7bfdb6d1 bellard
583 7bfdb6d1 bellard
void OPPROTO op_stw_T0_A0(void)
584 7bfdb6d1 bellard
{
585 7bfdb6d1 bellard
    stw((uint8_t *)A0, T0);
586 7bfdb6d1 bellard
}
587 7bfdb6d1 bellard
588 7bfdb6d1 bellard
void OPPROTO op_stl_T0_A0(void)
589 7bfdb6d1 bellard
{
590 7bfdb6d1 bellard
    stl((uint8_t *)A0, T0);
591 7bfdb6d1 bellard
}
592 7bfdb6d1 bellard
593 4b74fe1f bellard
/* used for bit operations */
594 4b74fe1f bellard
595 4b74fe1f bellard
void OPPROTO op_add_bitw_A0_T1(void)
596 4b74fe1f bellard
{
597 4b74fe1f bellard
    A0 += ((int32_t)T1 >> 4) << 1;
598 4b74fe1f bellard
}
599 4b74fe1f bellard
600 4b74fe1f bellard
void OPPROTO op_add_bitl_A0_T1(void)
601 4b74fe1f bellard
{
602 4b74fe1f bellard
    A0 += ((int32_t)T1 >> 5) << 2;
603 4b74fe1f bellard
}
604 7bfdb6d1 bellard
605 7bfdb6d1 bellard
/* indirect jump */
606 0ecfa993 bellard
607 7bfdb6d1 bellard
void OPPROTO op_jmp_T0(void)
608 7bfdb6d1 bellard
{
609 dab2ed99 bellard
    EIP = T0;
610 7bfdb6d1 bellard
}
611 7bfdb6d1 bellard
612 7bfdb6d1 bellard
void OPPROTO op_jmp_im(void)
613 7bfdb6d1 bellard
{
614 dab2ed99 bellard
    EIP = PARAM1;
615 7bfdb6d1 bellard
}
616 7bfdb6d1 bellard
617 0ecfa993 bellard
void OPPROTO op_int_im(void)
618 0ecfa993 bellard
{
619 dab2ed99 bellard
    EIP = PARAM1;
620 0ecfa993 bellard
    raise_exception(EXCP0D_GPF);
621 0ecfa993 bellard
}
622 0ecfa993 bellard
623 0ecfa993 bellard
void OPPROTO op_int3(void)
624 0ecfa993 bellard
{
625 dab2ed99 bellard
    EIP = PARAM1;
626 0ecfa993 bellard
    raise_exception(EXCP03_INT3);
627 0ecfa993 bellard
}
628 0ecfa993 bellard
629 0ecfa993 bellard
void OPPROTO op_into(void)
630 0ecfa993 bellard
{
631 0ecfa993 bellard
    int eflags;
632 0ecfa993 bellard
    eflags = cc_table[CC_OP].compute_all();
633 0ecfa993 bellard
    if (eflags & CC_O) {
634 0ecfa993 bellard
        raise_exception(EXCP04_INTO);
635 a4a0ffdb bellard
    }
636 a4a0ffdb bellard
}
637 a4a0ffdb bellard
638 f631ef9b bellard
/* XXX: add IOPL/CPL tests */
639 f631ef9b bellard
void OPPROTO op_cli(void)
640 f631ef9b bellard
{
641 f631ef9b bellard
    raise_exception(EXCP0D_GPF);
642 f631ef9b bellard
}
643 f631ef9b bellard
644 f631ef9b bellard
/* XXX: add IOPL/CPL tests */
645 f631ef9b bellard
void OPPROTO op_sti(void)
646 f631ef9b bellard
{
647 f631ef9b bellard
    raise_exception(EXCP0D_GPF);
648 f631ef9b bellard
}
649 f631ef9b bellard
650 f631ef9b bellard
/* vm86plus instructions */
651 f631ef9b bellard
652 f631ef9b bellard
void OPPROTO op_cli_vm(void)
653 f631ef9b bellard
{
654 f631ef9b bellard
    env->eflags &= ~VIF_MASK;
655 f631ef9b bellard
}
656 f631ef9b bellard
657 f631ef9b bellard
void OPPROTO op_sti_vm(void)
658 f631ef9b bellard
{
659 f631ef9b bellard
    env->eflags |= VIF_MASK;
660 f631ef9b bellard
    if (env->eflags & VIP_MASK) {
661 f631ef9b bellard
        EIP = PARAM1;
662 f631ef9b bellard
        raise_exception(EXCP0D_GPF);
663 f631ef9b bellard
    }
664 f631ef9b bellard
    FORCE_RET();
665 f631ef9b bellard
}
666 f631ef9b bellard
667 a4a0ffdb bellard
void OPPROTO op_boundw(void)
668 a4a0ffdb bellard
{
669 a4a0ffdb bellard
    int low, high, v;
670 a4a0ffdb bellard
    low = ldsw((uint8_t *)A0);
671 a4a0ffdb bellard
    high = ldsw((uint8_t *)A0 + 2);
672 a4a0ffdb bellard
    v = (int16_t)T0;
673 a4a0ffdb bellard
    if (v < low || v > high)
674 a4a0ffdb bellard
        raise_exception(EXCP05_BOUND);
675 a4a0ffdb bellard
    FORCE_RET();
676 a4a0ffdb bellard
}
677 a4a0ffdb bellard
678 a4a0ffdb bellard
void OPPROTO op_boundl(void)
679 a4a0ffdb bellard
{
680 a4a0ffdb bellard
    int low, high, v;
681 a4a0ffdb bellard
    low = ldl((uint8_t *)A0);
682 a4a0ffdb bellard
    high = ldl((uint8_t *)A0 + 4);
683 a4a0ffdb bellard
    v = T0;
684 a4a0ffdb bellard
    if (v < low || v > high)
685 a4a0ffdb bellard
        raise_exception(EXCP05_BOUND);
686 a4a0ffdb bellard
    FORCE_RET();
687 a4a0ffdb bellard
}
688 a4a0ffdb bellard
689 a4a0ffdb bellard
void OPPROTO op_cmpxchg8b(void)
690 a4a0ffdb bellard
{
691 a4a0ffdb bellard
    uint64_t d;
692 a4a0ffdb bellard
    int eflags;
693 a4a0ffdb bellard
694 a4a0ffdb bellard
    eflags = cc_table[CC_OP].compute_all();
695 a4a0ffdb bellard
    d = ldq((uint8_t *)A0);
696 a4a0ffdb bellard
    if (d == (((uint64_t)EDX << 32) | EAX)) {
697 a4a0ffdb bellard
        stq((uint8_t *)A0, ((uint64_t)ECX << 32) | EBX);
698 a4a0ffdb bellard
        eflags |= CC_Z;
699 0ecfa993 bellard
    } else {
700 a4a0ffdb bellard
        EDX = d >> 32;
701 a4a0ffdb bellard
        EAX = d;
702 a4a0ffdb bellard
        eflags &= ~CC_Z;
703 0ecfa993 bellard
    }
704 a4a0ffdb bellard
    CC_SRC = eflags;
705 a4a0ffdb bellard
    FORCE_RET();
706 0ecfa993 bellard
}
707 0ecfa993 bellard
708 7bfdb6d1 bellard
/* string ops */
709 7bfdb6d1 bellard
710 7bfdb6d1 bellard
#define ldul ldl
711 7bfdb6d1 bellard
712 7bfdb6d1 bellard
#define SHIFT 0
713 367e86e8 bellard
#include "ops_template.h"
714 7bfdb6d1 bellard
#undef SHIFT
715 7bfdb6d1 bellard
716 7bfdb6d1 bellard
#define SHIFT 1
717 367e86e8 bellard
#include "ops_template.h"
718 7bfdb6d1 bellard
#undef SHIFT
719 7bfdb6d1 bellard
720 7bfdb6d1 bellard
#define SHIFT 2
721 367e86e8 bellard
#include "ops_template.h"
722 7bfdb6d1 bellard
#undef SHIFT
723 7bfdb6d1 bellard
724 7bfdb6d1 bellard
/* sign extend */
725 7bfdb6d1 bellard
726 7bfdb6d1 bellard
void OPPROTO op_movsbl_T0_T0(void)
727 7bfdb6d1 bellard
{
728 7bfdb6d1 bellard
    T0 = (int8_t)T0;
729 7bfdb6d1 bellard
}
730 7bfdb6d1 bellard
731 7bfdb6d1 bellard
void OPPROTO op_movzbl_T0_T0(void)
732 7bfdb6d1 bellard
{
733 7bfdb6d1 bellard
    T0 = (uint8_t)T0;
734 7bfdb6d1 bellard
}
735 7bfdb6d1 bellard
736 7bfdb6d1 bellard
void OPPROTO op_movswl_T0_T0(void)
737 7bfdb6d1 bellard
{
738 7bfdb6d1 bellard
    T0 = (int16_t)T0;
739 7bfdb6d1 bellard
}
740 7bfdb6d1 bellard
741 7bfdb6d1 bellard
void OPPROTO op_movzwl_T0_T0(void)
742 7bfdb6d1 bellard
{
743 7bfdb6d1 bellard
    T0 = (uint16_t)T0;
744 7bfdb6d1 bellard
}
745 7bfdb6d1 bellard
746 7bfdb6d1 bellard
void OPPROTO op_movswl_EAX_AX(void)
747 7bfdb6d1 bellard
{
748 7bfdb6d1 bellard
    EAX = (int16_t)EAX;
749 7bfdb6d1 bellard
}
750 7bfdb6d1 bellard
751 7bfdb6d1 bellard
void OPPROTO op_movsbw_AX_AL(void)
752 7bfdb6d1 bellard
{
753 7bfdb6d1 bellard
    EAX = (EAX & 0xffff0000) | ((int8_t)EAX & 0xffff);
754 7bfdb6d1 bellard
}
755 7bfdb6d1 bellard
756 7bfdb6d1 bellard
void OPPROTO op_movslq_EDX_EAX(void)
757 7bfdb6d1 bellard
{
758 7bfdb6d1 bellard
    EDX = (int32_t)EAX >> 31;
759 7bfdb6d1 bellard
}
760 7bfdb6d1 bellard
761 7bfdb6d1 bellard
void OPPROTO op_movswl_DX_AX(void)
762 7bfdb6d1 bellard
{
763 7bfdb6d1 bellard
    EDX = (EDX & 0xffff0000) | (((int16_t)EAX >> 15) & 0xffff);
764 7bfdb6d1 bellard
}
765 7bfdb6d1 bellard
766 7bfdb6d1 bellard
/* push/pop */
767 7bfdb6d1 bellard
768 7bfdb6d1 bellard
void op_pushl_T0(void)
769 7bfdb6d1 bellard
{
770 7bfdb6d1 bellard
    uint32_t offset;
771 7bfdb6d1 bellard
    offset = ESP - 4;
772 7bfdb6d1 bellard
    stl((void *)offset, T0);
773 7bfdb6d1 bellard
    /* modify ESP after to handle exceptions correctly */
774 7bfdb6d1 bellard
    ESP = offset;
775 7bfdb6d1 bellard
}
776 7bfdb6d1 bellard
777 dab2ed99 bellard
void op_pushw_T0(void)
778 dab2ed99 bellard
{
779 dab2ed99 bellard
    uint32_t offset;
780 dab2ed99 bellard
    offset = ESP - 2;
781 dab2ed99 bellard
    stw((void *)offset, T0);
782 dab2ed99 bellard
    /* modify ESP after to handle exceptions correctly */
783 dab2ed99 bellard
    ESP = offset;
784 dab2ed99 bellard
}
785 dab2ed99 bellard
786 dab2ed99 bellard
void op_pushl_ss32_T0(void)
787 7bfdb6d1 bellard
{
788 7bfdb6d1 bellard
    uint32_t offset;
789 7bfdb6d1 bellard
    offset = ESP - 4;
790 dab2ed99 bellard
    stl(env->seg_cache[R_SS].base + offset, T0);
791 dab2ed99 bellard
    /* modify ESP after to handle exceptions correctly */
792 dab2ed99 bellard
    ESP = offset;
793 dab2ed99 bellard
}
794 dab2ed99 bellard
795 dab2ed99 bellard
void op_pushw_ss32_T0(void)
796 dab2ed99 bellard
{
797 dab2ed99 bellard
    uint32_t offset;
798 dab2ed99 bellard
    offset = ESP - 2;
799 dab2ed99 bellard
    stw(env->seg_cache[R_SS].base + offset, T0);
800 7bfdb6d1 bellard
    /* modify ESP after to handle exceptions correctly */
801 7bfdb6d1 bellard
    ESP = offset;
802 7bfdb6d1 bellard
}
803 7bfdb6d1 bellard
804 dab2ed99 bellard
void op_pushl_ss16_T0(void)
805 dab2ed99 bellard
{
806 dab2ed99 bellard
    uint32_t offset;
807 dab2ed99 bellard
    offset = (ESP - 4) & 0xffff;
808 dab2ed99 bellard
    stl(env->seg_cache[R_SS].base + offset, T0);
809 dab2ed99 bellard
    /* modify ESP after to handle exceptions correctly */
810 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | offset;
811 dab2ed99 bellard
}
812 dab2ed99 bellard
813 dab2ed99 bellard
void op_pushw_ss16_T0(void)
814 dab2ed99 bellard
{
815 dab2ed99 bellard
    uint32_t offset;
816 dab2ed99 bellard
    offset = (ESP - 2) & 0xffff;
817 dab2ed99 bellard
    stw(env->seg_cache[R_SS].base + offset, T0);
818 dab2ed99 bellard
    /* modify ESP after to handle exceptions correctly */
819 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | offset;
820 dab2ed99 bellard
}
821 dab2ed99 bellard
822 dab2ed99 bellard
/* NOTE: ESP update is done after */
823 7bfdb6d1 bellard
void op_popl_T0(void)
824 7bfdb6d1 bellard
{
825 7bfdb6d1 bellard
    T0 = ldl((void *)ESP);
826 dab2ed99 bellard
}
827 dab2ed99 bellard
828 dab2ed99 bellard
void op_popw_T0(void)
829 dab2ed99 bellard
{
830 dab2ed99 bellard
    T0 = lduw((void *)ESP);
831 dab2ed99 bellard
}
832 dab2ed99 bellard
833 dab2ed99 bellard
void op_popl_ss32_T0(void)
834 dab2ed99 bellard
{
835 dab2ed99 bellard
    T0 = ldl(env->seg_cache[R_SS].base + ESP);
836 dab2ed99 bellard
}
837 dab2ed99 bellard
838 dab2ed99 bellard
void op_popw_ss32_T0(void)
839 dab2ed99 bellard
{
840 dab2ed99 bellard
    T0 = lduw(env->seg_cache[R_SS].base + ESP);
841 dab2ed99 bellard
}
842 dab2ed99 bellard
843 dab2ed99 bellard
void op_popl_ss16_T0(void)
844 dab2ed99 bellard
{
845 dab2ed99 bellard
    T0 = ldl(env->seg_cache[R_SS].base + (ESP & 0xffff));
846 dab2ed99 bellard
}
847 dab2ed99 bellard
848 dab2ed99 bellard
void op_popw_ss16_T0(void)
849 dab2ed99 bellard
{
850 dab2ed99 bellard
    T0 = lduw(env->seg_cache[R_SS].base + (ESP & 0xffff));
851 dab2ed99 bellard
}
852 dab2ed99 bellard
853 dab2ed99 bellard
void op_addl_ESP_4(void)
854 dab2ed99 bellard
{
855 7bfdb6d1 bellard
    ESP += 4;
856 7bfdb6d1 bellard
}
857 7bfdb6d1 bellard
858 dab2ed99 bellard
void op_addl_ESP_2(void)
859 dab2ed99 bellard
{
860 dab2ed99 bellard
    ESP += 2;
861 dab2ed99 bellard
}
862 dab2ed99 bellard
863 dab2ed99 bellard
void op_addw_ESP_4(void)
864 dab2ed99 bellard
{
865 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | ((ESP + 4) & 0xffff);
866 dab2ed99 bellard
}
867 dab2ed99 bellard
868 dab2ed99 bellard
void op_addw_ESP_2(void)
869 dab2ed99 bellard
{
870 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | ((ESP + 2) & 0xffff);
871 dab2ed99 bellard
}
872 dab2ed99 bellard
873 7bfdb6d1 bellard
void op_addl_ESP_im(void)
874 7bfdb6d1 bellard
{
875 7bfdb6d1 bellard
    ESP += PARAM1;
876 7bfdb6d1 bellard
}
877 367e86e8 bellard
878 dab2ed99 bellard
void op_addw_ESP_im(void)
879 dab2ed99 bellard
{
880 dab2ed99 bellard
    ESP = (ESP & ~0xffff) | ((ESP + PARAM1) & 0xffff);
881 27362c82 bellard
}
882 27362c82 bellard
883 27362c82 bellard
/* rdtsc */
884 27362c82 bellard
#ifndef __i386__
885 27362c82 bellard
uint64_t emu_time;
886 27362c82 bellard
#endif
887 a4a0ffdb bellard
888 a4a0ffdb bellard
void OPPROTO op_rdtsc(void)
889 27362c82 bellard
{
890 27362c82 bellard
    uint64_t val;
891 27362c82 bellard
#ifdef __i386__
892 27362c82 bellard
    asm("rdtsc" : "=A" (val));
893 27362c82 bellard
#else
894 27362c82 bellard
    /* better than nothing: the time increases */
895 27362c82 bellard
    val = emu_time++;
896 27362c82 bellard
#endif
897 27362c82 bellard
    EAX = val;
898 27362c82 bellard
    EDX = val >> 32;
899 27362c82 bellard
}
900 27362c82 bellard
901 a4a0ffdb bellard
/* We simulate a pre-MMX pentium as in valgrind */
902 a4a0ffdb bellard
#define CPUID_FP87 (1 << 0)
903 a4a0ffdb bellard
#define CPUID_VME  (1 << 1)
904 a4a0ffdb bellard
#define CPUID_DE   (1 << 2)
905 a4a0ffdb bellard
#define CPUID_PSE  (1 << 3)
906 a4a0ffdb bellard
#define CPUID_TSC  (1 << 4)
907 a4a0ffdb bellard
#define CPUID_MSR  (1 << 5)
908 a4a0ffdb bellard
#define CPUID_PAE  (1 << 6)
909 a4a0ffdb bellard
#define CPUID_MCE  (1 << 7)
910 a4a0ffdb bellard
#define CPUID_CX8  (1 << 8)
911 a4a0ffdb bellard
#define CPUID_APIC (1 << 9)
912 a4a0ffdb bellard
#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
913 a4a0ffdb bellard
#define CPUID_MTRR (1 << 12)
914 a4a0ffdb bellard
#define CPUID_PGE  (1 << 13)
915 a4a0ffdb bellard
#define CPUID_MCA  (1 << 14)
916 a4a0ffdb bellard
#define CPUID_CMOV (1 << 15)
917 a4a0ffdb bellard
/* ... */
918 a4a0ffdb bellard
#define CPUID_MMX  (1 << 23)
919 a4a0ffdb bellard
#define CPUID_FXSR (1 << 24)
920 a4a0ffdb bellard
#define CPUID_SSE  (1 << 25)
921 a4a0ffdb bellard
#define CPUID_SSE2 (1 << 26)
922 a4a0ffdb bellard
923 a4a0ffdb bellard
void helper_cpuid(void)
924 a4a0ffdb bellard
{
925 a4a0ffdb bellard
    if (EAX == 0) {
926 a4a0ffdb bellard
        EAX = 1; /* max EAX index supported */
927 a4a0ffdb bellard
        EBX = 0x756e6547;
928 a4a0ffdb bellard
        ECX = 0x6c65746e;
929 a4a0ffdb bellard
        EDX = 0x49656e69;
930 a4a0ffdb bellard
    } else {
931 a4a0ffdb bellard
        /* EAX = 1 info */
932 a4a0ffdb bellard
        EAX = 0x52b;
933 a4a0ffdb bellard
        EBX = 0;
934 a4a0ffdb bellard
        ECX = 0;
935 a4a0ffdb bellard
        EDX = CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
936 a4a0ffdb bellard
            CPUID_TSC | CPUID_MSR | CPUID_MCE |
937 a4a0ffdb bellard
            CPUID_CX8;
938 a4a0ffdb bellard
    }
939 a4a0ffdb bellard
}
940 a4a0ffdb bellard
941 a4a0ffdb bellard
void OPPROTO op_cpuid(void)
942 a4a0ffdb bellard
{
943 a4a0ffdb bellard
    helper_cpuid();
944 a4a0ffdb bellard
}
945 a4a0ffdb bellard
946 27362c82 bellard
/* bcd */
947 27362c82 bellard
948 27362c82 bellard
/* XXX: exception */
949 27362c82 bellard
void OPPROTO op_aam(void)
950 27362c82 bellard
{
951 27362c82 bellard
    int base = PARAM1;
952 27362c82 bellard
    int al, ah;
953 27362c82 bellard
    al = EAX & 0xff;
954 27362c82 bellard
    ah = al / base;
955 27362c82 bellard
    al = al % base;
956 27362c82 bellard
    EAX = (EAX & ~0xffff) | al | (ah << 8);
957 27362c82 bellard
    CC_DST = al;
958 27362c82 bellard
}
959 27362c82 bellard
960 27362c82 bellard
void OPPROTO op_aad(void)
961 27362c82 bellard
{
962 27362c82 bellard
    int base = PARAM1;
963 27362c82 bellard
    int al, ah;
964 27362c82 bellard
    al = EAX & 0xff;
965 27362c82 bellard
    ah = (EAX >> 8) & 0xff;
966 27362c82 bellard
    al = ((ah * base) + al) & 0xff;
967 27362c82 bellard
    EAX = (EAX & ~0xffff) | al;
968 27362c82 bellard
    CC_DST = al;
969 27362c82 bellard
}
970 27362c82 bellard
971 27362c82 bellard
void OPPROTO op_aaa(void)
972 27362c82 bellard
{
973 27362c82 bellard
    int icarry;
974 27362c82 bellard
    int al, ah, af;
975 27362c82 bellard
    int eflags;
976 27362c82 bellard
977 27362c82 bellard
    eflags = cc_table[CC_OP].compute_all();
978 27362c82 bellard
    af = eflags & CC_A;
979 27362c82 bellard
    al = EAX & 0xff;
980 27362c82 bellard
    ah = (EAX >> 8) & 0xff;
981 27362c82 bellard
982 27362c82 bellard
    icarry = (al > 0xf9);
983 27362c82 bellard
    if (((al & 0x0f) > 9 ) || af) {
984 27362c82 bellard
        al = (al + 6) & 0x0f;
985 27362c82 bellard
        ah = (ah + 1 + icarry) & 0xff;
986 27362c82 bellard
        eflags |= CC_C | CC_A;
987 27362c82 bellard
    } else {
988 27362c82 bellard
        eflags &= ~(CC_C | CC_A);
989 27362c82 bellard
        al &= 0x0f;
990 27362c82 bellard
    }
991 27362c82 bellard
    EAX = (EAX & ~0xffff) | al | (ah << 8);
992 27362c82 bellard
    CC_SRC = eflags;
993 27362c82 bellard
}
994 27362c82 bellard
995 27362c82 bellard
void OPPROTO op_aas(void)
996 27362c82 bellard
{
997 27362c82 bellard
    int icarry;
998 27362c82 bellard
    int al, ah, af;
999 27362c82 bellard
    int eflags;
1000 27362c82 bellard
1001 27362c82 bellard
    eflags = cc_table[CC_OP].compute_all();
1002 27362c82 bellard
    af = eflags & CC_A;
1003 27362c82 bellard
    al = EAX & 0xff;
1004 27362c82 bellard
    ah = (EAX >> 8) & 0xff;
1005 27362c82 bellard
1006 27362c82 bellard
    icarry = (al < 6);
1007 27362c82 bellard
    if (((al & 0x0f) > 9 ) || af) {
1008 27362c82 bellard
        al = (al - 6) & 0x0f;
1009 27362c82 bellard
        ah = (ah - 1 - icarry) & 0xff;
1010 27362c82 bellard
        eflags |= CC_C | CC_A;
1011 27362c82 bellard
    } else {
1012 27362c82 bellard
        eflags &= ~(CC_C | CC_A);
1013 27362c82 bellard
        al &= 0x0f;
1014 27362c82 bellard
    }
1015 27362c82 bellard
    EAX = (EAX & ~0xffff) | al | (ah << 8);
1016 27362c82 bellard
    CC_SRC = eflags;
1017 27362c82 bellard
}
1018 27362c82 bellard
1019 27362c82 bellard
void OPPROTO op_daa(void)
1020 27362c82 bellard
{
1021 27362c82 bellard
    int al, af, cf;
1022 27362c82 bellard
    int eflags;
1023 27362c82 bellard
1024 27362c82 bellard
    eflags = cc_table[CC_OP].compute_all();
1025 27362c82 bellard
    cf = eflags & CC_C;
1026 27362c82 bellard
    af = eflags & CC_A;
1027 27362c82 bellard
    al = EAX & 0xff;
1028 27362c82 bellard
1029 27362c82 bellard
    eflags = 0;
1030 27362c82 bellard
    if (((al & 0x0f) > 9 ) || af) {
1031 27362c82 bellard
        al = (al + 6) & 0xff;
1032 27362c82 bellard
        eflags |= CC_A;
1033 27362c82 bellard
    }
1034 27362c82 bellard
    if ((al > 0x9f) || cf) {
1035 27362c82 bellard
        al = (al + 0x60) & 0xff;
1036 27362c82 bellard
        eflags |= CC_C;
1037 27362c82 bellard
    }
1038 27362c82 bellard
    EAX = (EAX & ~0xff) | al;
1039 27362c82 bellard
    /* well, speed is not an issue here, so we compute the flags by hand */
1040 27362c82 bellard
    eflags |= (al == 0) << 6; /* zf */
1041 27362c82 bellard
    eflags |= parity_table[al]; /* pf */
1042 27362c82 bellard
    eflags |= (al & 0x80); /* sf */
1043 27362c82 bellard
    CC_SRC = eflags;
1044 27362c82 bellard
}
1045 27362c82 bellard
1046 27362c82 bellard
void OPPROTO op_das(void)
1047 27362c82 bellard
{
1048 27362c82 bellard
    int al, al1, af, cf;
1049 27362c82 bellard
    int eflags;
1050 27362c82 bellard
1051 27362c82 bellard
    eflags = cc_table[CC_OP].compute_all();
1052 27362c82 bellard
    cf = eflags & CC_C;
1053 27362c82 bellard
    af = eflags & CC_A;
1054 27362c82 bellard
    al = EAX & 0xff;
1055 27362c82 bellard
1056 27362c82 bellard
    eflags = 0;
1057 27362c82 bellard
    al1 = al;
1058 27362c82 bellard
    if (((al & 0x0f) > 9 ) || af) {
1059 27362c82 bellard
        eflags |= CC_A;
1060 27362c82 bellard
        if (al < 6 || cf)
1061 27362c82 bellard
            eflags |= CC_C;
1062 27362c82 bellard
        al = (al - 6) & 0xff;
1063 27362c82 bellard
    }
1064 27362c82 bellard
    if ((al1 > 0x99) || cf) {
1065 27362c82 bellard
        al = (al - 0x60) & 0xff;
1066 27362c82 bellard
        eflags |= CC_C;
1067 27362c82 bellard
    }
1068 27362c82 bellard
    EAX = (EAX & ~0xff) | al;
1069 27362c82 bellard
    /* well, speed is not an issue here, so we compute the flags by hand */
1070 27362c82 bellard
    eflags |= (al == 0) << 6; /* zf */
1071 27362c82 bellard
    eflags |= parity_table[al]; /* pf */
1072 27362c82 bellard
    eflags |= (al & 0x80); /* sf */
1073 27362c82 bellard
    CC_SRC = eflags;
1074 27362c82 bellard
}
1075 27362c82 bellard
1076 6dbad63e bellard
/* segment handling */
1077 6dbad63e bellard
1078 a4a0ffdb bellard
/* XXX: use static VM86 information */
1079 6dbad63e bellard
void load_seg(int seg_reg, int selector)
1080 6dbad63e bellard
{
1081 6dbad63e bellard
    SegmentCache *sc;
1082 6dbad63e bellard
    SegmentDescriptorTable *dt;
1083 6dbad63e bellard
    int index;
1084 6dbad63e bellard
    uint32_t e1, e2;
1085 6dbad63e bellard
    uint8_t *ptr;
1086 6dbad63e bellard
1087 6dbad63e bellard
    env->segs[seg_reg] = selector;
1088 6dbad63e bellard
    sc = &env->seg_cache[seg_reg];
1089 a4a0ffdb bellard
    if (env->eflags & VM_MASK) {
1090 6dbad63e bellard
        sc->base = (void *)(selector << 4);
1091 6dbad63e bellard
        sc->limit = 0xffff;
1092 6dbad63e bellard
        sc->seg_32bit = 0;
1093 6dbad63e bellard
    } else {
1094 6dbad63e bellard
        if (selector & 0x4)
1095 6dbad63e bellard
            dt = &env->ldt;
1096 6dbad63e bellard
        else
1097 6dbad63e bellard
            dt = &env->gdt;
1098 6dbad63e bellard
        index = selector & ~7;
1099 6dbad63e bellard
        if ((index + 7) > dt->limit)
1100 6dbad63e bellard
            raise_exception(EXCP0D_GPF);
1101 6dbad63e bellard
        ptr = dt->base + index;
1102 6dbad63e bellard
        e1 = ldl(ptr);
1103 6dbad63e bellard
        e2 = ldl(ptr + 4);
1104 6dbad63e bellard
        sc->base = (void *)((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
1105 6dbad63e bellard
        sc->limit = (e1 & 0xffff) | (e2 & 0x000f0000);
1106 6dbad63e bellard
        if (e2 & (1 << 23))
1107 6dbad63e bellard
            sc->limit = (sc->limit << 12) | 0xfff;
1108 6dbad63e bellard
        sc->seg_32bit = (e2 >> 22) & 1;
1109 6dbad63e bellard
#if 0
1110 6dbad63e bellard
        fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx seg_32bit=%d\n", 
1111 6dbad63e bellard
                selector, (unsigned long)sc->base, sc->limit, sc->seg_32bit);
1112 6dbad63e bellard
#endif
1113 6dbad63e bellard
    }
1114 6dbad63e bellard
}
1115 6dbad63e bellard
1116 6dbad63e bellard
void OPPROTO op_movl_seg_T0(void)
1117 6dbad63e bellard
{
1118 6dbad63e bellard
    load_seg(PARAM1, T0 & 0xffff);
1119 6dbad63e bellard
}
1120 6dbad63e bellard
1121 6dbad63e bellard
void OPPROTO op_movl_T0_seg(void)
1122 6dbad63e bellard
{
1123 6dbad63e bellard
    T0 = env->segs[PARAM1];
1124 6dbad63e bellard
}
1125 6dbad63e bellard
1126 a4a0ffdb bellard
void OPPROTO op_movl_A0_seg(void)
1127 a4a0ffdb bellard
{
1128 a4a0ffdb bellard
    A0 = *(unsigned long *)((char *)env + PARAM1);
1129 a4a0ffdb bellard
}
1130 a4a0ffdb bellard
1131 6dbad63e bellard
void OPPROTO op_addl_A0_seg(void)
1132 6dbad63e bellard
{
1133 6dbad63e bellard
    A0 += *(unsigned long *)((char *)env + PARAM1);
1134 6dbad63e bellard
}
1135 6dbad63e bellard
1136 367e86e8 bellard
/* flags handling */
1137 367e86e8 bellard
1138 367e86e8 bellard
/* slow jumps cases (compute x86 flags) */
1139 367e86e8 bellard
void OPPROTO op_jo_cc(void)
1140 367e86e8 bellard
{
1141 367e86e8 bellard
    int eflags;
1142 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1143 367e86e8 bellard
    if (eflags & CC_O)
1144 dab2ed99 bellard
        EIP = PARAM1;
1145 367e86e8 bellard
    else
1146 dab2ed99 bellard
        EIP = PARAM2;
1147 0ecfa993 bellard
    FORCE_RET();
1148 367e86e8 bellard
}
1149 367e86e8 bellard
1150 367e86e8 bellard
void OPPROTO op_jb_cc(void)
1151 367e86e8 bellard
{
1152 367e86e8 bellard
    if (cc_table[CC_OP].compute_c())
1153 dab2ed99 bellard
        EIP = PARAM1;
1154 367e86e8 bellard
    else
1155 dab2ed99 bellard
        EIP = PARAM2;
1156 0ecfa993 bellard
    FORCE_RET();
1157 367e86e8 bellard
}
1158 367e86e8 bellard
1159 367e86e8 bellard
void OPPROTO op_jz_cc(void)
1160 367e86e8 bellard
{
1161 367e86e8 bellard
    int eflags;
1162 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1163 367e86e8 bellard
    if (eflags & CC_Z)
1164 dab2ed99 bellard
        EIP = PARAM1;
1165 367e86e8 bellard
    else
1166 dab2ed99 bellard
        EIP = PARAM2;
1167 0ecfa993 bellard
    FORCE_RET();
1168 367e86e8 bellard
}
1169 367e86e8 bellard
1170 367e86e8 bellard
void OPPROTO op_jbe_cc(void)
1171 367e86e8 bellard
{
1172 367e86e8 bellard
    int eflags;
1173 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1174 367e86e8 bellard
    if (eflags & (CC_Z | CC_C))
1175 dab2ed99 bellard
        EIP = PARAM1;
1176 367e86e8 bellard
    else
1177 dab2ed99 bellard
        EIP = PARAM2;
1178 0ecfa993 bellard
    FORCE_RET();
1179 367e86e8 bellard
}
1180 367e86e8 bellard
1181 367e86e8 bellard
void OPPROTO op_js_cc(void)
1182 367e86e8 bellard
{
1183 367e86e8 bellard
    int eflags;
1184 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1185 367e86e8 bellard
    if (eflags & CC_S)
1186 dab2ed99 bellard
        EIP = PARAM1;
1187 367e86e8 bellard
    else
1188 dab2ed99 bellard
        EIP = PARAM2;
1189 0ecfa993 bellard
    FORCE_RET();
1190 367e86e8 bellard
}
1191 367e86e8 bellard
1192 367e86e8 bellard
void OPPROTO op_jp_cc(void)
1193 367e86e8 bellard
{
1194 367e86e8 bellard
    int eflags;
1195 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1196 367e86e8 bellard
    if (eflags & CC_P)
1197 dab2ed99 bellard
        EIP = PARAM1;
1198 367e86e8 bellard
    else
1199 dab2ed99 bellard
        EIP = PARAM2;
1200 0ecfa993 bellard
    FORCE_RET();
1201 367e86e8 bellard
}
1202 367e86e8 bellard
1203 367e86e8 bellard
void OPPROTO op_jl_cc(void)
1204 367e86e8 bellard
{
1205 367e86e8 bellard
    int eflags;
1206 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1207 367e86e8 bellard
    if ((eflags ^ (eflags >> 4)) & 0x80)
1208 dab2ed99 bellard
        EIP = PARAM1;
1209 367e86e8 bellard
    else
1210 dab2ed99 bellard
        EIP = PARAM2;
1211 0ecfa993 bellard
    FORCE_RET();
1212 367e86e8 bellard
}
1213 367e86e8 bellard
1214 367e86e8 bellard
void OPPROTO op_jle_cc(void)
1215 367e86e8 bellard
{
1216 367e86e8 bellard
    int eflags;
1217 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1218 367e86e8 bellard
    if (((eflags ^ (eflags >> 4)) & 0x80) || (eflags & CC_Z))
1219 dab2ed99 bellard
        EIP = PARAM1;
1220 367e86e8 bellard
    else
1221 dab2ed99 bellard
        EIP = PARAM2;
1222 0ecfa993 bellard
    FORCE_RET();
1223 367e86e8 bellard
}
1224 367e86e8 bellard
1225 367e86e8 bellard
/* slow set cases (compute x86 flags) */
1226 367e86e8 bellard
void OPPROTO op_seto_T0_cc(void)
1227 367e86e8 bellard
{
1228 367e86e8 bellard
    int eflags;
1229 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1230 367e86e8 bellard
    T0 = (eflags >> 11) & 1;
1231 367e86e8 bellard
}
1232 367e86e8 bellard
1233 367e86e8 bellard
void OPPROTO op_setb_T0_cc(void)
1234 367e86e8 bellard
{
1235 367e86e8 bellard
    T0 = cc_table[CC_OP].compute_c();
1236 367e86e8 bellard
}
1237 367e86e8 bellard
1238 367e86e8 bellard
void OPPROTO op_setz_T0_cc(void)
1239 367e86e8 bellard
{
1240 367e86e8 bellard
    int eflags;
1241 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1242 367e86e8 bellard
    T0 = (eflags >> 6) & 1;
1243 367e86e8 bellard
}
1244 367e86e8 bellard
1245 367e86e8 bellard
void OPPROTO op_setbe_T0_cc(void)
1246 367e86e8 bellard
{
1247 367e86e8 bellard
    int eflags;
1248 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1249 367e86e8 bellard
    T0 = (eflags & (CC_Z | CC_C)) != 0;
1250 367e86e8 bellard
}
1251 367e86e8 bellard
1252 367e86e8 bellard
void OPPROTO op_sets_T0_cc(void)
1253 367e86e8 bellard
{
1254 367e86e8 bellard
    int eflags;
1255 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1256 367e86e8 bellard
    T0 = (eflags >> 7) & 1;
1257 367e86e8 bellard
}
1258 367e86e8 bellard
1259 367e86e8 bellard
void OPPROTO op_setp_T0_cc(void)
1260 367e86e8 bellard
{
1261 367e86e8 bellard
    int eflags;
1262 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1263 367e86e8 bellard
    T0 = (eflags >> 2) & 1;
1264 367e86e8 bellard
}
1265 367e86e8 bellard
1266 367e86e8 bellard
void OPPROTO op_setl_T0_cc(void)
1267 367e86e8 bellard
{
1268 367e86e8 bellard
    int eflags;
1269 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1270 367e86e8 bellard
    T0 = ((eflags ^ (eflags >> 4)) >> 7) & 1;
1271 367e86e8 bellard
}
1272 367e86e8 bellard
1273 367e86e8 bellard
void OPPROTO op_setle_T0_cc(void)
1274 367e86e8 bellard
{
1275 367e86e8 bellard
    int eflags;
1276 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1277 367e86e8 bellard
    T0 = (((eflags ^ (eflags >> 4)) & 0x80) || (eflags & CC_Z)) != 0;
1278 367e86e8 bellard
}
1279 367e86e8 bellard
1280 367e86e8 bellard
void OPPROTO op_xor_T0_1(void)
1281 367e86e8 bellard
{
1282 367e86e8 bellard
    T0 ^= 1;
1283 367e86e8 bellard
}
1284 367e86e8 bellard
1285 367e86e8 bellard
void OPPROTO op_set_cc_op(void)
1286 367e86e8 bellard
{
1287 367e86e8 bellard
    CC_OP = PARAM1;
1288 367e86e8 bellard
}
1289 367e86e8 bellard
1290 f631ef9b bellard
#define FL_UPDATE_MASK32 (TF_MASK | AC_MASK | ID_MASK)
1291 f631ef9b bellard
#define FL_UPDATE_MASK16 (TF_MASK)
1292 a4a0ffdb bellard
1293 367e86e8 bellard
void OPPROTO op_movl_eflags_T0(void)
1294 367e86e8 bellard
{
1295 a4a0ffdb bellard
    int eflags;
1296 a4a0ffdb bellard
    eflags = T0;
1297 a4a0ffdb bellard
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1298 a4a0ffdb bellard
    DF = 1 - (2 * ((eflags >> 10) & 1));
1299 a4a0ffdb bellard
    /* we also update some system flags as in user mode */
1300 f631ef9b bellard
    env->eflags = (env->eflags & ~FL_UPDATE_MASK32) | (eflags & FL_UPDATE_MASK32);
1301 f631ef9b bellard
}
1302 f631ef9b bellard
1303 f631ef9b bellard
void OPPROTO op_movw_eflags_T0(void)
1304 f631ef9b bellard
{
1305 f631ef9b bellard
    int eflags;
1306 f631ef9b bellard
    eflags = T0;
1307 f631ef9b bellard
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1308 f631ef9b bellard
    DF = 1 - (2 * ((eflags >> 10) & 1));
1309 f631ef9b bellard
    /* we also update some system flags as in user mode */
1310 f631ef9b bellard
    env->eflags = (env->eflags & ~FL_UPDATE_MASK16) | (eflags & FL_UPDATE_MASK16);
1311 f631ef9b bellard
}
1312 f631ef9b bellard
1313 f631ef9b bellard
/* vm86 version */
1314 f631ef9b bellard
void OPPROTO op_movw_eflags_T0_vm(void)
1315 f631ef9b bellard
{
1316 f631ef9b bellard
    int eflags;
1317 f631ef9b bellard
    eflags = T0;
1318 f631ef9b bellard
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1319 f631ef9b bellard
    DF = 1 - (2 * ((eflags >> 10) & 1));
1320 f631ef9b bellard
    /* we also update some system flags as in user mode */
1321 f631ef9b bellard
    env->eflags = (env->eflags & ~(FL_UPDATE_MASK16 | VIF_MASK)) |
1322 f631ef9b bellard
        (eflags & FL_UPDATE_MASK16);
1323 f631ef9b bellard
    if (eflags & IF_MASK) {
1324 f631ef9b bellard
        env->eflags |= VIF_MASK;
1325 f631ef9b bellard
        if (env->eflags & VIP_MASK) {
1326 f631ef9b bellard
            EIP = PARAM1;
1327 f631ef9b bellard
            raise_exception(EXCP0D_GPF);
1328 f631ef9b bellard
        }
1329 f631ef9b bellard
    }
1330 f631ef9b bellard
    FORCE_RET();
1331 f631ef9b bellard
}
1332 f631ef9b bellard
1333 f631ef9b bellard
void OPPROTO op_movl_eflags_T0_vm(void)
1334 f631ef9b bellard
{
1335 f631ef9b bellard
    int eflags;
1336 f631ef9b bellard
    eflags = T0;
1337 f631ef9b bellard
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1338 f631ef9b bellard
    DF = 1 - (2 * ((eflags >> 10) & 1));
1339 f631ef9b bellard
    /* we also update some system flags as in user mode */
1340 f631ef9b bellard
    env->eflags = (env->eflags & ~(FL_UPDATE_MASK32 | VIF_MASK)) |
1341 f631ef9b bellard
        (eflags & FL_UPDATE_MASK32);
1342 f631ef9b bellard
    if (eflags & IF_MASK) {
1343 f631ef9b bellard
        env->eflags |= VIF_MASK;
1344 f631ef9b bellard
        if (env->eflags & VIP_MASK) {
1345 f631ef9b bellard
            EIP = PARAM1;
1346 f631ef9b bellard
            raise_exception(EXCP0D_GPF);
1347 f631ef9b bellard
        }
1348 f631ef9b bellard
    }
1349 f631ef9b bellard
    FORCE_RET();
1350 367e86e8 bellard
}
1351 367e86e8 bellard
1352 367e86e8 bellard
/* XXX: compute only O flag */
1353 367e86e8 bellard
void OPPROTO op_movb_eflags_T0(void)
1354 367e86e8 bellard
{
1355 367e86e8 bellard
    int of;
1356 367e86e8 bellard
    of = cc_table[CC_OP].compute_all() & CC_O;
1357 a4a0ffdb bellard
    CC_SRC = (T0 & (CC_S | CC_Z | CC_A | CC_P | CC_C)) | of;
1358 367e86e8 bellard
}
1359 367e86e8 bellard
1360 367e86e8 bellard
void OPPROTO op_movl_T0_eflags(void)
1361 367e86e8 bellard
{
1362 a4a0ffdb bellard
    int eflags;
1363 a4a0ffdb bellard
    eflags = cc_table[CC_OP].compute_all();
1364 a4a0ffdb bellard
    eflags |= (DF & DF_MASK);
1365 a4a0ffdb bellard
    eflags |= env->eflags & ~(VM_MASK | RF_MASK);
1366 a4a0ffdb bellard
    T0 = eflags;
1367 367e86e8 bellard
}
1368 367e86e8 bellard
1369 f631ef9b bellard
/* vm86 version */
1370 f631ef9b bellard
void OPPROTO op_movl_T0_eflags_vm(void)
1371 f631ef9b bellard
{
1372 f631ef9b bellard
    int eflags;
1373 f631ef9b bellard
    eflags = cc_table[CC_OP].compute_all();
1374 f631ef9b bellard
    eflags |= (DF & DF_MASK);
1375 f631ef9b bellard
    eflags |= env->eflags & ~(VM_MASK | RF_MASK | IF_MASK);
1376 f631ef9b bellard
    if (env->eflags & VIF_MASK)
1377 f631ef9b bellard
        eflags |= IF_MASK;
1378 f631ef9b bellard
    T0 = eflags;
1379 f631ef9b bellard
}
1380 f631ef9b bellard
1381 367e86e8 bellard
void OPPROTO op_cld(void)
1382 367e86e8 bellard
{
1383 367e86e8 bellard
    DF = 1;
1384 367e86e8 bellard
}
1385 367e86e8 bellard
1386 367e86e8 bellard
void OPPROTO op_std(void)
1387 367e86e8 bellard
{
1388 367e86e8 bellard
    DF = -1;
1389 367e86e8 bellard
}
1390 367e86e8 bellard
1391 367e86e8 bellard
void OPPROTO op_clc(void)
1392 367e86e8 bellard
{
1393 367e86e8 bellard
    int eflags;
1394 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1395 367e86e8 bellard
    eflags &= ~CC_C;
1396 367e86e8 bellard
    CC_SRC = eflags;
1397 367e86e8 bellard
}
1398 367e86e8 bellard
1399 367e86e8 bellard
void OPPROTO op_stc(void)
1400 367e86e8 bellard
{
1401 367e86e8 bellard
    int eflags;
1402 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1403 367e86e8 bellard
    eflags |= CC_C;
1404 367e86e8 bellard
    CC_SRC = eflags;
1405 367e86e8 bellard
}
1406 367e86e8 bellard
1407 367e86e8 bellard
void OPPROTO op_cmc(void)
1408 367e86e8 bellard
{
1409 367e86e8 bellard
    int eflags;
1410 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
1411 367e86e8 bellard
    eflags ^= CC_C;
1412 367e86e8 bellard
    CC_SRC = eflags;
1413 367e86e8 bellard
}
1414 367e86e8 bellard
1415 27362c82 bellard
void OPPROTO op_salc(void)
1416 27362c82 bellard
{
1417 27362c82 bellard
    int cf;
1418 27362c82 bellard
    cf = cc_table[CC_OP].compute_c();
1419 27362c82 bellard
    EAX = (EAX & ~0xff) | ((-cf) & 0xff);
1420 27362c82 bellard
}
1421 27362c82 bellard
1422 367e86e8 bellard
static int compute_all_eflags(void)
1423 367e86e8 bellard
{
1424 367e86e8 bellard
    return CC_SRC;
1425 367e86e8 bellard
}
1426 367e86e8 bellard
1427 367e86e8 bellard
static int compute_c_eflags(void)
1428 367e86e8 bellard
{
1429 367e86e8 bellard
    return CC_SRC & CC_C;
1430 367e86e8 bellard
}
1431 367e86e8 bellard
1432 367e86e8 bellard
static int compute_c_mul(void)
1433 367e86e8 bellard
{
1434 367e86e8 bellard
    int cf;
1435 367e86e8 bellard
    cf = (CC_SRC != 0);
1436 367e86e8 bellard
    return cf;
1437 367e86e8 bellard
}
1438 367e86e8 bellard
1439 367e86e8 bellard
static int compute_all_mul(void)
1440 367e86e8 bellard
{
1441 367e86e8 bellard
    int cf, pf, af, zf, sf, of;
1442 367e86e8 bellard
    cf = (CC_SRC != 0);
1443 367e86e8 bellard
    pf = 0; /* undefined */
1444 367e86e8 bellard
    af = 0; /* undefined */
1445 367e86e8 bellard
    zf = 0; /* undefined */
1446 367e86e8 bellard
    sf = 0; /* undefined */
1447 367e86e8 bellard
    of = cf << 11;
1448 367e86e8 bellard
    return cf | pf | af | zf | sf | of;
1449 367e86e8 bellard
}
1450 367e86e8 bellard
    
1451 367e86e8 bellard
CCTable cc_table[CC_OP_NB] = {
1452 367e86e8 bellard
    [CC_OP_DYNAMIC] = { /* should never happen */ },
1453 367e86e8 bellard
1454 367e86e8 bellard
    [CC_OP_EFLAGS] = { compute_all_eflags, compute_c_eflags },
1455 367e86e8 bellard
1456 367e86e8 bellard
    [CC_OP_MUL] = { compute_all_mul, compute_c_mul },
1457 367e86e8 bellard
1458 367e86e8 bellard
    [CC_OP_ADDB] = { compute_all_addb, compute_c_addb },
1459 367e86e8 bellard
    [CC_OP_ADDW] = { compute_all_addw, compute_c_addw  },
1460 367e86e8 bellard
    [CC_OP_ADDL] = { compute_all_addl, compute_c_addl  },
1461 367e86e8 bellard
1462 4b74fe1f bellard
    [CC_OP_ADCB] = { compute_all_adcb, compute_c_adcb },
1463 4b74fe1f bellard
    [CC_OP_ADCW] = { compute_all_adcw, compute_c_adcw  },
1464 4b74fe1f bellard
    [CC_OP_ADCL] = { compute_all_adcl, compute_c_adcl  },
1465 4b74fe1f bellard
1466 367e86e8 bellard
    [CC_OP_SUBB] = { compute_all_subb, compute_c_subb  },
1467 367e86e8 bellard
    [CC_OP_SUBW] = { compute_all_subw, compute_c_subw  },
1468 367e86e8 bellard
    [CC_OP_SUBL] = { compute_all_subl, compute_c_subl  },
1469 367e86e8 bellard
    
1470 4b74fe1f bellard
    [CC_OP_SBBB] = { compute_all_sbbb, compute_c_sbbb  },
1471 4b74fe1f bellard
    [CC_OP_SBBW] = { compute_all_sbbw, compute_c_sbbw  },
1472 4b74fe1f bellard
    [CC_OP_SBBL] = { compute_all_sbbl, compute_c_sbbl  },
1473 4b74fe1f bellard
    
1474 367e86e8 bellard
    [CC_OP_LOGICB] = { compute_all_logicb, compute_c_logicb },
1475 367e86e8 bellard
    [CC_OP_LOGICW] = { compute_all_logicw, compute_c_logicw },
1476 367e86e8 bellard
    [CC_OP_LOGICL] = { compute_all_logicl, compute_c_logicl },
1477 367e86e8 bellard
    
1478 4b74fe1f bellard
    [CC_OP_INCB] = { compute_all_incb, compute_c_incl },
1479 4b74fe1f bellard
    [CC_OP_INCW] = { compute_all_incw, compute_c_incl },
1480 367e86e8 bellard
    [CC_OP_INCL] = { compute_all_incl, compute_c_incl },
1481 367e86e8 bellard
    
1482 4b74fe1f bellard
    [CC_OP_DECB] = { compute_all_decb, compute_c_incl },
1483 4b74fe1f bellard
    [CC_OP_DECW] = { compute_all_decw, compute_c_incl },
1484 367e86e8 bellard
    [CC_OP_DECL] = { compute_all_decl, compute_c_incl },
1485 367e86e8 bellard
    
1486 4b74fe1f bellard
    [CC_OP_SHLB] = { compute_all_shlb, compute_c_shll },
1487 4b74fe1f bellard
    [CC_OP_SHLW] = { compute_all_shlw, compute_c_shll },
1488 367e86e8 bellard
    [CC_OP_SHLL] = { compute_all_shll, compute_c_shll },
1489 4b74fe1f bellard
1490 4b74fe1f bellard
    [CC_OP_SARB] = { compute_all_sarb, compute_c_shll },
1491 4b74fe1f bellard
    [CC_OP_SARW] = { compute_all_sarw, compute_c_shll },
1492 4b74fe1f bellard
    [CC_OP_SARL] = { compute_all_sarl, compute_c_shll },
1493 367e86e8 bellard
};
1494 927f621e bellard
1495 f631ef9b bellard
/* floating point support. Some of the code for complicated x87
1496 f631ef9b bellard
   functions comes from the LGPL'ed x86 emulator found in the Willows
1497 f631ef9b bellard
   TWIN windows emulator. */
1498 927f621e bellard
1499 927f621e bellard
#ifdef USE_X86LDOUBLE
1500 927f621e bellard
/* use long double functions */
1501 927f621e bellard
#define lrint lrintl
1502 927f621e bellard
#define llrint llrintl
1503 927f621e bellard
#define fabs fabsl
1504 927f621e bellard
#define sin sinl
1505 927f621e bellard
#define cos cosl
1506 927f621e bellard
#define sqrt sqrtl
1507 927f621e bellard
#define pow powl
1508 927f621e bellard
#define log logl
1509 927f621e bellard
#define tan tanl
1510 927f621e bellard
#define atan2 atan2l
1511 927f621e bellard
#define floor floorl
1512 927f621e bellard
#define ceil ceill
1513 927f621e bellard
#define rint rintl
1514 927f621e bellard
#endif
1515 927f621e bellard
1516 927f621e bellard
extern int lrint(CPU86_LDouble x);
1517 927f621e bellard
extern int64_t llrint(CPU86_LDouble x);
1518 927f621e bellard
extern CPU86_LDouble fabs(CPU86_LDouble x);
1519 927f621e bellard
extern CPU86_LDouble sin(CPU86_LDouble x);
1520 927f621e bellard
extern CPU86_LDouble cos(CPU86_LDouble x);
1521 927f621e bellard
extern CPU86_LDouble sqrt(CPU86_LDouble x);
1522 927f621e bellard
extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
1523 927f621e bellard
extern CPU86_LDouble log(CPU86_LDouble x);
1524 927f621e bellard
extern CPU86_LDouble tan(CPU86_LDouble x);
1525 927f621e bellard
extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
1526 927f621e bellard
extern CPU86_LDouble floor(CPU86_LDouble x);
1527 927f621e bellard
extern CPU86_LDouble ceil(CPU86_LDouble x);
1528 927f621e bellard
extern CPU86_LDouble rint(CPU86_LDouble x);
1529 927f621e bellard
1530 51fe6890 bellard
#if defined(__powerpc__)
1531 51fe6890 bellard
extern CPU86_LDouble copysign(CPU86_LDouble, CPU86_LDouble);
1532 51fe6890 bellard
1533 51fe6890 bellard
/* correct (but slow) PowerPC rint() (glibc version is incorrect) */
1534 51fe6890 bellard
double qemu_rint(double x)
1535 51fe6890 bellard
{
1536 51fe6890 bellard
    double y = 4503599627370496.0;
1537 51fe6890 bellard
    if (fabs(x) >= y)
1538 51fe6890 bellard
        return x;
1539 51fe6890 bellard
    if (x < 0) 
1540 51fe6890 bellard
        y = -y;
1541 51fe6890 bellard
    y = (x + y) - y;
1542 51fe6890 bellard
    if (y == 0.0)
1543 51fe6890 bellard
        y = copysign(y, x);
1544 51fe6890 bellard
    return y;
1545 51fe6890 bellard
}
1546 51fe6890 bellard
1547 51fe6890 bellard
#define rint qemu_rint
1548 51fe6890 bellard
#endif
1549 51fe6890 bellard
1550 927f621e bellard
#define RC_MASK         0xc00
1551 927f621e bellard
#define RC_NEAR                0x000
1552 927f621e bellard
#define RC_DOWN                0x400
1553 927f621e bellard
#define RC_UP                0x800
1554 927f621e bellard
#define RC_CHOP                0xc00
1555 927f621e bellard
1556 927f621e bellard
#define MAXTAN 9223372036854775808.0
1557 927f621e bellard
1558 927f621e bellard
#ifdef USE_X86LDOUBLE
1559 927f621e bellard
1560 927f621e bellard
/* only for x86 */
1561 927f621e bellard
typedef union {
1562 927f621e bellard
    long double d;
1563 927f621e bellard
    struct {
1564 927f621e bellard
        unsigned long long lower;
1565 927f621e bellard
        unsigned short upper;
1566 927f621e bellard
    } l;
1567 927f621e bellard
} CPU86_LDoubleU;
1568 927f621e bellard
1569 927f621e bellard
/* the following deal with x86 long double-precision numbers */
1570 927f621e bellard
#define MAXEXPD 0x7fff
1571 927f621e bellard
#define EXPBIAS 16383
1572 927f621e bellard
#define EXPD(fp)        (fp.l.upper & 0x7fff)
1573 927f621e bellard
#define SIGND(fp)        ((fp.l.upper) & 0x8000)
1574 927f621e bellard
#define MANTD(fp)       (fp.l.lower)
1575 927f621e bellard
#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
1576 927f621e bellard
1577 927f621e bellard
#else
1578 927f621e bellard
1579 77f8dd5a bellard
typedef union {
1580 927f621e bellard
    double d;
1581 927f621e bellard
#ifndef WORDS_BIGENDIAN
1582 927f621e bellard
    struct {
1583 927f621e bellard
        unsigned long lower;
1584 927f621e bellard
        long upper;
1585 927f621e bellard
    } l;
1586 927f621e bellard
#else
1587 927f621e bellard
    struct {
1588 927f621e bellard
        long upper;
1589 927f621e bellard
        unsigned long lower;
1590 927f621e bellard
    } l;
1591 927f621e bellard
#endif
1592 927f621e bellard
    long long ll;
1593 927f621e bellard
} CPU86_LDoubleU;
1594 927f621e bellard
1595 927f621e bellard
/* the following deal with IEEE double-precision numbers */
1596 927f621e bellard
#define MAXEXPD 0x7ff
1597 927f621e bellard
#define EXPBIAS 1023
1598 927f621e bellard
#define EXPD(fp)        (((fp.l.upper) >> 20) & 0x7FF)
1599 927f621e bellard
#define SIGND(fp)        ((fp.l.upper) & 0x80000000)
1600 927f621e bellard
#define MANTD(fp)        (fp.ll & ((1LL << 52) - 1))
1601 927f621e bellard
#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20)
1602 927f621e bellard
#endif
1603 927f621e bellard
1604 927f621e bellard
/* fp load FT0 */
1605 927f621e bellard
1606 927f621e bellard
void OPPROTO op_flds_FT0_A0(void)
1607 927f621e bellard
{
1608 d014c98c bellard
#ifdef USE_FP_CONVERT
1609 d014c98c bellard
    FP_CONVERT.i32 = ldl((void *)A0);
1610 d014c98c bellard
    FT0 = FP_CONVERT.f;
1611 d014c98c bellard
#else
1612 927f621e bellard
    FT0 = ldfl((void *)A0);
1613 d014c98c bellard
#endif
1614 927f621e bellard
}
1615 927f621e bellard
1616 927f621e bellard
void OPPROTO op_fldl_FT0_A0(void)
1617 927f621e bellard
{
1618 d014c98c bellard
#ifdef USE_FP_CONVERT
1619 d014c98c bellard
    FP_CONVERT.i64 = ldq((void *)A0);
1620 d014c98c bellard
    FT0 = FP_CONVERT.d;
1621 d014c98c bellard
#else
1622 927f621e bellard
    FT0 = ldfq((void *)A0);
1623 d014c98c bellard
#endif
1624 927f621e bellard
}
1625 927f621e bellard
1626 04369ff2 bellard
/* helpers are needed to avoid static constant reference. XXX: find a better way */
1627 04369ff2 bellard
#ifdef USE_INT_TO_FLOAT_HELPERS
1628 04369ff2 bellard
1629 04369ff2 bellard
void helper_fild_FT0_A0(void)
1630 04369ff2 bellard
{
1631 04369ff2 bellard
    FT0 = (CPU86_LDouble)ldsw((void *)A0);
1632 04369ff2 bellard
}
1633 04369ff2 bellard
1634 04369ff2 bellard
void helper_fildl_FT0_A0(void)
1635 04369ff2 bellard
{
1636 04369ff2 bellard
    FT0 = (CPU86_LDouble)((int32_t)ldl((void *)A0));
1637 04369ff2 bellard
}
1638 04369ff2 bellard
1639 04369ff2 bellard
void helper_fildll_FT0_A0(void)
1640 04369ff2 bellard
{
1641 04369ff2 bellard
    FT0 = (CPU86_LDouble)((int64_t)ldq((void *)A0));
1642 04369ff2 bellard
}
1643 04369ff2 bellard
1644 04369ff2 bellard
void OPPROTO op_fild_FT0_A0(void)
1645 04369ff2 bellard
{
1646 04369ff2 bellard
    helper_fild_FT0_A0();
1647 04369ff2 bellard
}
1648 04369ff2 bellard
1649 04369ff2 bellard
void OPPROTO op_fildl_FT0_A0(void)
1650 04369ff2 bellard
{
1651 04369ff2 bellard
    helper_fildl_FT0_A0();
1652 04369ff2 bellard
}
1653 04369ff2 bellard
1654 04369ff2 bellard
void OPPROTO op_fildll_FT0_A0(void)
1655 04369ff2 bellard
{
1656 04369ff2 bellard
    helper_fildll_FT0_A0();
1657 04369ff2 bellard
}
1658 04369ff2 bellard
1659 04369ff2 bellard
#else
1660 04369ff2 bellard
1661 927f621e bellard
void OPPROTO op_fild_FT0_A0(void)
1662 927f621e bellard
{
1663 d014c98c bellard
#ifdef USE_FP_CONVERT
1664 d014c98c bellard
    FP_CONVERT.i32 = ldsw((void *)A0);
1665 d014c98c bellard
    FT0 = (CPU86_LDouble)FP_CONVERT.i32;
1666 d014c98c bellard
#else
1667 927f621e bellard
    FT0 = (CPU86_LDouble)ldsw((void *)A0);
1668 d014c98c bellard
#endif
1669 927f621e bellard
}
1670 927f621e bellard
1671 927f621e bellard
void OPPROTO op_fildl_FT0_A0(void)
1672 927f621e bellard
{
1673 d014c98c bellard
#ifdef USE_FP_CONVERT
1674 d014c98c bellard
    FP_CONVERT.i32 = (int32_t) ldl((void *)A0);
1675 d014c98c bellard
    FT0 = (CPU86_LDouble)FP_CONVERT.i32;
1676 d014c98c bellard
#else
1677 927f621e bellard
    FT0 = (CPU86_LDouble)((int32_t)ldl((void *)A0));
1678 d014c98c bellard
#endif
1679 927f621e bellard
}
1680 927f621e bellard
1681 927f621e bellard
void OPPROTO op_fildll_FT0_A0(void)
1682 927f621e bellard
{
1683 d014c98c bellard
#ifdef USE_FP_CONVERT
1684 d014c98c bellard
    FP_CONVERT.i64 = (int64_t) ldq((void *)A0);
1685 d014c98c bellard
    FT0 = (CPU86_LDouble)FP_CONVERT.i64;
1686 d014c98c bellard
#else
1687 927f621e bellard
    FT0 = (CPU86_LDouble)((int64_t)ldq((void *)A0));
1688 d014c98c bellard
#endif
1689 927f621e bellard
}
1690 04369ff2 bellard
#endif
1691 927f621e bellard
1692 927f621e bellard
/* fp load ST0 */
1693 927f621e bellard
1694 927f621e bellard
void OPPROTO op_flds_ST0_A0(void)
1695 927f621e bellard
{
1696 d014c98c bellard
#ifdef USE_FP_CONVERT
1697 d014c98c bellard
    FP_CONVERT.i32 = ldl((void *)A0);
1698 d014c98c bellard
    ST0 = FP_CONVERT.f;
1699 d014c98c bellard
#else
1700 927f621e bellard
    ST0 = ldfl((void *)A0);
1701 d014c98c bellard
#endif
1702 927f621e bellard
}
1703 927f621e bellard
1704 927f621e bellard
void OPPROTO op_fldl_ST0_A0(void)
1705 927f621e bellard
{
1706 d014c98c bellard
#ifdef USE_FP_CONVERT
1707 d014c98c bellard
    FP_CONVERT.i64 = ldq((void *)A0);
1708 d014c98c bellard
    ST0 = FP_CONVERT.d;
1709 d014c98c bellard
#else
1710 927f621e bellard
    ST0 = ldfq((void *)A0);
1711 d014c98c bellard
#endif
1712 927f621e bellard
}
1713 927f621e bellard
1714 77f8dd5a bellard
#ifdef USE_X86LDOUBLE
1715 77f8dd5a bellard
void OPPROTO op_fldt_ST0_A0(void)
1716 77f8dd5a bellard
{
1717 77f8dd5a bellard
    ST0 = *(long double *)A0;
1718 77f8dd5a bellard
}
1719 77f8dd5a bellard
#else
1720 77f8dd5a bellard
void helper_fldt_ST0_A0(void)
1721 77f8dd5a bellard
{
1722 77f8dd5a bellard
    CPU86_LDoubleU temp;
1723 77f8dd5a bellard
    int upper, e;
1724 77f8dd5a bellard
    /* mantissa */
1725 77f8dd5a bellard
    upper = lduw((uint8_t *)A0 + 8);
1726 77f8dd5a bellard
    /* XXX: handle overflow ? */
1727 77f8dd5a bellard
    e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
1728 77f8dd5a bellard
    e |= (upper >> 4) & 0x800; /* sign */
1729 77f8dd5a bellard
    temp.ll = ((ldq((void *)A0) >> 11) & ((1LL << 52) - 1)) | ((uint64_t)e << 52);
1730 77f8dd5a bellard
    ST0 = temp.d;
1731 77f8dd5a bellard
}
1732 77f8dd5a bellard
1733 77f8dd5a bellard
void OPPROTO op_fldt_ST0_A0(void)
1734 77f8dd5a bellard
{
1735 77f8dd5a bellard
    helper_fldt_ST0_A0();
1736 77f8dd5a bellard
}
1737 77f8dd5a bellard
#endif
1738 77f8dd5a bellard
1739 04369ff2 bellard
/* helpers are needed to avoid static constant reference. XXX: find a better way */
1740 04369ff2 bellard
#ifdef USE_INT_TO_FLOAT_HELPERS
1741 04369ff2 bellard
1742 04369ff2 bellard
void helper_fild_ST0_A0(void)
1743 04369ff2 bellard
{
1744 04369ff2 bellard
    ST0 = (CPU86_LDouble)ldsw((void *)A0);
1745 04369ff2 bellard
}
1746 04369ff2 bellard
1747 04369ff2 bellard
void helper_fildl_ST0_A0(void)
1748 04369ff2 bellard
{
1749 04369ff2 bellard
    ST0 = (CPU86_LDouble)((int32_t)ldl((void *)A0));
1750 04369ff2 bellard
}
1751 04369ff2 bellard
1752 04369ff2 bellard
void helper_fildll_ST0_A0(void)
1753 04369ff2 bellard
{
1754 04369ff2 bellard
    ST0 = (CPU86_LDouble)((int64_t)ldq((void *)A0));
1755 04369ff2 bellard
}
1756 04369ff2 bellard
1757 04369ff2 bellard
void OPPROTO op_fild_ST0_A0(void)
1758 04369ff2 bellard
{
1759 04369ff2 bellard
    helper_fild_ST0_A0();
1760 04369ff2 bellard
}
1761 04369ff2 bellard
1762 04369ff2 bellard
void OPPROTO op_fildl_ST0_A0(void)
1763 04369ff2 bellard
{
1764 04369ff2 bellard
    helper_fildl_ST0_A0();
1765 04369ff2 bellard
}
1766 04369ff2 bellard
1767 04369ff2 bellard
void OPPROTO op_fildll_ST0_A0(void)
1768 04369ff2 bellard
{
1769 04369ff2 bellard
    helper_fildll_ST0_A0();
1770 04369ff2 bellard
}
1771 04369ff2 bellard
1772 04369ff2 bellard
#else
1773 04369ff2 bellard
1774 927f621e bellard
void OPPROTO op_fild_ST0_A0(void)
1775 927f621e bellard
{
1776 d014c98c bellard
#ifdef USE_FP_CONVERT
1777 d014c98c bellard
    FP_CONVERT.i32 = ldsw((void *)A0);
1778 d014c98c bellard
    ST0 = (CPU86_LDouble)FP_CONVERT.i32;
1779 d014c98c bellard
#else
1780 927f621e bellard
    ST0 = (CPU86_LDouble)ldsw((void *)A0);
1781 d014c98c bellard
#endif
1782 927f621e bellard
}
1783 927f621e bellard
1784 927f621e bellard
void OPPROTO op_fildl_ST0_A0(void)
1785 927f621e bellard
{
1786 d014c98c bellard
#ifdef USE_FP_CONVERT
1787 d014c98c bellard
    FP_CONVERT.i32 = (int32_t) ldl((void *)A0);
1788 d014c98c bellard
    ST0 = (CPU86_LDouble)FP_CONVERT.i32;
1789 d014c98c bellard
#else
1790 927f621e bellard
    ST0 = (CPU86_LDouble)((int32_t)ldl((void *)A0));
1791 d014c98c bellard
#endif
1792 927f621e bellard
}
1793 927f621e bellard
1794 927f621e bellard
void OPPROTO op_fildll_ST0_A0(void)
1795 927f621e bellard
{
1796 d014c98c bellard
#ifdef USE_FP_CONVERT
1797 d014c98c bellard
    FP_CONVERT.i64 = (int64_t) ldq((void *)A0);
1798 d014c98c bellard
    ST0 = (CPU86_LDouble)FP_CONVERT.i64;
1799 d014c98c bellard
#else
1800 927f621e bellard
    ST0 = (CPU86_LDouble)((int64_t)ldq((void *)A0));
1801 d014c98c bellard
#endif
1802 927f621e bellard
}
1803 927f621e bellard
1804 04369ff2 bellard
#endif
1805 04369ff2 bellard
1806 927f621e bellard
/* fp store */
1807 927f621e bellard
1808 927f621e bellard
void OPPROTO op_fsts_ST0_A0(void)
1809 927f621e bellard
{
1810 d014c98c bellard
#ifdef USE_FP_CONVERT
1811 d014c98c bellard
    FP_CONVERT.d = ST0;
1812 d014c98c bellard
    stfl((void *)A0, FP_CONVERT.f);
1813 d014c98c bellard
#else
1814 927f621e bellard
    stfl((void *)A0, (float)ST0);
1815 d014c98c bellard
#endif
1816 927f621e bellard
}
1817 927f621e bellard
1818 927f621e bellard
void OPPROTO op_fstl_ST0_A0(void)
1819 927f621e bellard
{
1820 77f8dd5a bellard
    stfq((void *)A0, (double)ST0);
1821 927f621e bellard
}
1822 927f621e bellard
1823 77f8dd5a bellard
#ifdef USE_X86LDOUBLE
1824 77f8dd5a bellard
void OPPROTO op_fstt_ST0_A0(void)
1825 77f8dd5a bellard
{
1826 77f8dd5a bellard
    *(long double *)A0 = ST0;
1827 77f8dd5a bellard
}
1828 77f8dd5a bellard
#else
1829 77f8dd5a bellard
void helper_fstt_ST0_A0(void)
1830 77f8dd5a bellard
{
1831 77f8dd5a bellard
    CPU86_LDoubleU temp;
1832 77f8dd5a bellard
    int e;
1833 77f8dd5a bellard
    temp.d = ST0;
1834 77f8dd5a bellard
    /* mantissa */
1835 77f8dd5a bellard
    stq((void *)A0, (MANTD(temp) << 11) | (1LL << 63));
1836 77f8dd5a bellard
    /* exponent + sign */
1837 77f8dd5a bellard
    e = EXPD(temp) - EXPBIAS + 16383;
1838 77f8dd5a bellard
    e |= SIGND(temp) >> 16;
1839 77f8dd5a bellard
    stw((uint8_t *)A0 + 8, e);
1840 77f8dd5a bellard
}
1841 77f8dd5a bellard
1842 77f8dd5a bellard
void OPPROTO op_fstt_ST0_A0(void)
1843 77f8dd5a bellard
{
1844 77f8dd5a bellard
    helper_fstt_ST0_A0();
1845 77f8dd5a bellard
}
1846 77f8dd5a bellard
#endif
1847 77f8dd5a bellard
1848 927f621e bellard
void OPPROTO op_fist_ST0_A0(void)
1849 927f621e bellard
{
1850 d014c98c bellard
#if defined(__sparc__) && !defined(__sparc_v9__)
1851 d014c98c bellard
    register CPU86_LDouble d asm("o0");
1852 d014c98c bellard
#else
1853 d014c98c bellard
    CPU86_LDouble d;
1854 d014c98c bellard
#endif
1855 927f621e bellard
    int val;
1856 d014c98c bellard
1857 d014c98c bellard
    d = ST0;
1858 d014c98c bellard
    val = lrint(d);
1859 927f621e bellard
    stw((void *)A0, val);
1860 927f621e bellard
}
1861 927f621e bellard
1862 927f621e bellard
void OPPROTO op_fistl_ST0_A0(void)
1863 927f621e bellard
{
1864 d014c98c bellard
#if defined(__sparc__) && !defined(__sparc_v9__)
1865 d014c98c bellard
    register CPU86_LDouble d asm("o0");
1866 d014c98c bellard
#else
1867 d014c98c bellard
    CPU86_LDouble d;
1868 d014c98c bellard
#endif
1869 927f621e bellard
    int val;
1870 d014c98c bellard
1871 d014c98c bellard
    d = ST0;
1872 d014c98c bellard
    val = lrint(d);
1873 927f621e bellard
    stl((void *)A0, val);
1874 927f621e bellard
}
1875 927f621e bellard
1876 927f621e bellard
void OPPROTO op_fistll_ST0_A0(void)
1877 927f621e bellard
{
1878 d014c98c bellard
#if defined(__sparc__) && !defined(__sparc_v9__)
1879 d014c98c bellard
    register CPU86_LDouble d asm("o0");
1880 d014c98c bellard
#else
1881 d014c98c bellard
    CPU86_LDouble d;
1882 d014c98c bellard
#endif
1883 927f621e bellard
    int64_t val;
1884 d014c98c bellard
1885 d014c98c bellard
    d = ST0;
1886 d014c98c bellard
    val = llrint(d);
1887 927f621e bellard
    stq((void *)A0, val);
1888 927f621e bellard
}
1889 927f621e bellard
1890 77f8dd5a bellard
/* BCD ops */
1891 77f8dd5a bellard
1892 77f8dd5a bellard
#define MUL10(iv) ( iv + iv + (iv << 3) )
1893 77f8dd5a bellard
1894 77f8dd5a bellard
void helper_fbld_ST0_A0(void)
1895 77f8dd5a bellard
{
1896 77f8dd5a bellard
    uint8_t *seg;
1897 77f8dd5a bellard
    CPU86_LDouble fpsrcop;
1898 77f8dd5a bellard
    int m32i;
1899 77f8dd5a bellard
    unsigned int v;
1900 77f8dd5a bellard
1901 77f8dd5a bellard
    /* in this code, seg/m32i will be used as temporary ptr/int */
1902 77f8dd5a bellard
    seg = (uint8_t *)A0 + 8;
1903 77f8dd5a bellard
    v = ldub(seg--);
1904 77f8dd5a bellard
    /* XXX: raise exception */
1905 77f8dd5a bellard
    if (v != 0)
1906 77f8dd5a bellard
        return;
1907 77f8dd5a bellard
    v = ldub(seg--);
1908 77f8dd5a bellard
    /* XXX: raise exception */
1909 77f8dd5a bellard
    if ((v & 0xf0) != 0)
1910 77f8dd5a bellard
        return;
1911 77f8dd5a bellard
    m32i = v;  /* <-- d14 */
1912 77f8dd5a bellard
    v = ldub(seg--);
1913 77f8dd5a bellard
    m32i = MUL10(m32i) + (v >> 4);  /* <-- val * 10 + d13 */
1914 77f8dd5a bellard
    m32i = MUL10(m32i) + (v & 0xf); /* <-- val * 10 + d12 */
1915 77f8dd5a bellard
    v = ldub(seg--);
1916 77f8dd5a bellard
    m32i = MUL10(m32i) + (v >> 4);  /* <-- val * 10 + d11 */
1917 77f8dd5a bellard
    m32i = MUL10(m32i) + (v & 0xf); /* <-- val * 10 + d10 */
1918 77f8dd5a bellard
    v = ldub(seg--);
1919 77f8dd5a bellard
    m32i = MUL10(m32i) + (v >> 4);  /* <-- val * 10 + d9 */
1920 77f8dd5a bellard
    m32i = MUL10(m32i) + (v & 0xf); /* <-- val * 10 + d8 */
1921 77f8dd5a bellard
    fpsrcop = ((CPU86_LDouble)m32i) * 100000000.0;
1922 77f8dd5a bellard
1923 77f8dd5a bellard
    v = ldub(seg--);
1924 77f8dd5a bellard
    m32i = (v >> 4);  /* <-- d7 */
1925 77f8dd5a bellard
    m32i = MUL10(m32i) + (v & 0xf); /* <-- val * 10 + d6 */
1926 77f8dd5a bellard
    v = ldub(seg--);
1927 77f8dd5a bellard
    m32i = MUL10(m32i) + (v >> 4);  /* <-- val * 10 + d5 */
1928 77f8dd5a bellard
    m32i = MUL10(m32i) + (v & 0xf); /* <-- val * 10 + d4 */
1929 77f8dd5a bellard
    v = ldub(seg--);
1930 77f8dd5a bellard
    m32i = MUL10(m32i) + (v >> 4);  /* <-- val * 10 + d3 */
1931 77f8dd5a bellard
    m32i = MUL10(m32i) + (v & 0xf); /* <-- val * 10 + d2 */
1932 77f8dd5a bellard
    v = ldub(seg);
1933 77f8dd5a bellard
    m32i = MUL10(m32i) + (v >> 4);  /* <-- val * 10 + d1 */
1934 77f8dd5a bellard
    m32i = MUL10(m32i) + (v & 0xf); /* <-- val * 10 + d0 */
1935 77f8dd5a bellard
    fpsrcop += ((CPU86_LDouble)m32i);
1936 77f8dd5a bellard
    if ( ldub(seg+9) & 0x80 )
1937 77f8dd5a bellard
        fpsrcop = -fpsrcop;
1938 77f8dd5a bellard
    ST0 = fpsrcop;
1939 77f8dd5a bellard
}
1940 77f8dd5a bellard
1941 77f8dd5a bellard
void OPPROTO op_fbld_ST0_A0(void)
1942 77f8dd5a bellard
{
1943 77f8dd5a bellard
    helper_fbld_ST0_A0();
1944 77f8dd5a bellard
}
1945 77f8dd5a bellard
1946 77f8dd5a bellard
void helper_fbst_ST0_A0(void)
1947 77f8dd5a bellard
{
1948 77f8dd5a bellard
    CPU86_LDouble fptemp;
1949 77f8dd5a bellard
    CPU86_LDouble fpsrcop;
1950 77f8dd5a bellard
    int v;
1951 77f8dd5a bellard
    uint8_t *mem_ref, *mem_end;
1952 77f8dd5a bellard
1953 77f8dd5a bellard
    fpsrcop = rint(ST0);
1954 77f8dd5a bellard
    mem_ref = (uint8_t *)A0;
1955 77f8dd5a bellard
    mem_end = mem_ref + 8;
1956 77f8dd5a bellard
    if ( fpsrcop < 0.0 ) {
1957 77f8dd5a bellard
        stw(mem_end, 0x8000);
1958 77f8dd5a bellard
        fpsrcop = -fpsrcop;
1959 77f8dd5a bellard
    } else {
1960 77f8dd5a bellard
        stw(mem_end, 0x0000);
1961 77f8dd5a bellard
    }
1962 77f8dd5a bellard
    while (mem_ref < mem_end) {
1963 77f8dd5a bellard
        if (fpsrcop == 0.0)
1964 77f8dd5a bellard
            break;
1965 77f8dd5a bellard
        fptemp = floor(fpsrcop/10.0);
1966 77f8dd5a bellard
        v = ((int)(fpsrcop - fptemp*10.0));
1967 77f8dd5a bellard
        if  (fptemp == 0.0)  { 
1968 77f8dd5a bellard
            stb(mem_ref++, v); 
1969 77f8dd5a bellard
            break; 
1970 77f8dd5a bellard
        }
1971 77f8dd5a bellard
        fpsrcop = fptemp;
1972 77f8dd5a bellard
        fptemp = floor(fpsrcop/10.0);
1973 77f8dd5a bellard
        v |= (((int)(fpsrcop - fptemp*10.0)) << 4);
1974 77f8dd5a bellard
        stb(mem_ref++, v);
1975 77f8dd5a bellard
        fpsrcop = fptemp;
1976 77f8dd5a bellard
    }
1977 77f8dd5a bellard
    while (mem_ref < mem_end) {
1978 77f8dd5a bellard
        stb(mem_ref++, 0);
1979 77f8dd5a bellard
    }
1980 77f8dd5a bellard
}
1981 77f8dd5a bellard
1982 77f8dd5a bellard
void OPPROTO op_fbst_ST0_A0(void)
1983 77f8dd5a bellard
{
1984 77f8dd5a bellard
    helper_fbst_ST0_A0();
1985 77f8dd5a bellard
}
1986 77f8dd5a bellard
1987 927f621e bellard
/* FPU move */
1988 927f621e bellard
1989 927f621e bellard
static inline void fpush(void)
1990 927f621e bellard
{
1991 927f621e bellard
    env->fpstt = (env->fpstt - 1) & 7;
1992 927f621e bellard
    env->fptags[env->fpstt] = 0; /* validate stack entry */
1993 927f621e bellard
}
1994 927f621e bellard
1995 927f621e bellard
static inline void fpop(void)
1996 927f621e bellard
{
1997 927f621e bellard
    env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
1998 927f621e bellard
    env->fpstt = (env->fpstt + 1) & 7;
1999 927f621e bellard
}
2000 927f621e bellard
2001 927f621e bellard
void OPPROTO op_fpush(void)
2002 927f621e bellard
{
2003 927f621e bellard
    fpush();
2004 927f621e bellard
}
2005 927f621e bellard
2006 927f621e bellard
void OPPROTO op_fpop(void)
2007 927f621e bellard
{
2008 927f621e bellard
    fpop();
2009 927f621e bellard
}
2010 927f621e bellard
2011 927f621e bellard
void OPPROTO op_fdecstp(void)
2012 927f621e bellard
{
2013 927f621e bellard
    env->fpstt = (env->fpstt - 1) & 7;
2014 927f621e bellard
    env->fpus &= (~0x4700);
2015 927f621e bellard
}
2016 927f621e bellard
2017 927f621e bellard
void OPPROTO op_fincstp(void)
2018 927f621e bellard
{
2019 927f621e bellard
    env->fpstt = (env->fpstt + 1) & 7;
2020 927f621e bellard
    env->fpus &= (~0x4700);
2021 927f621e bellard
}
2022 927f621e bellard
2023 927f621e bellard
void OPPROTO op_fmov_ST0_FT0(void)
2024 927f621e bellard
{
2025 927f621e bellard
    ST0 = FT0;
2026 927f621e bellard
}
2027 927f621e bellard
2028 927f621e bellard
void OPPROTO op_fmov_FT0_STN(void)
2029 927f621e bellard
{
2030 927f621e bellard
    FT0 = ST(PARAM1);
2031 927f621e bellard
}
2032 927f621e bellard
2033 927f621e bellard
void OPPROTO op_fmov_ST0_STN(void)
2034 927f621e bellard
{
2035 927f621e bellard
    ST0 = ST(PARAM1);
2036 927f621e bellard
}
2037 927f621e bellard
2038 927f621e bellard
void OPPROTO op_fmov_STN_ST0(void)
2039 927f621e bellard
{
2040 927f621e bellard
    ST(PARAM1) = ST0;
2041 927f621e bellard
}
2042 927f621e bellard
2043 927f621e bellard
void OPPROTO op_fxchg_ST0_STN(void)
2044 927f621e bellard
{
2045 927f621e bellard
    CPU86_LDouble tmp;
2046 927f621e bellard
    tmp = ST(PARAM1);
2047 927f621e bellard
    ST(PARAM1) = ST0;
2048 927f621e bellard
    ST0 = tmp;
2049 927f621e bellard
}
2050 927f621e bellard
2051 927f621e bellard
/* FPU operations */
2052 927f621e bellard
2053 927f621e bellard
/* XXX: handle nans */
2054 927f621e bellard
void OPPROTO op_fcom_ST0_FT0(void)
2055 927f621e bellard
{
2056 927f621e bellard
    env->fpus &= (~0x4500);        /* (C3,C2,C0) <-- 000 */
2057 927f621e bellard
    if (ST0 < FT0)
2058 927f621e bellard
        env->fpus |= 0x100;        /* (C3,C2,C0) <-- 001 */
2059 927f621e bellard
    else if (ST0 == FT0)
2060 927f621e bellard
        env->fpus |= 0x4000; /* (C3,C2,C0) <-- 100 */
2061 927f621e bellard
    FORCE_RET();
2062 927f621e bellard
}
2063 927f621e bellard
2064 77f8dd5a bellard
/* XXX: handle nans */
2065 77f8dd5a bellard
void OPPROTO op_fucom_ST0_FT0(void)
2066 77f8dd5a bellard
{
2067 77f8dd5a bellard
    env->fpus &= (~0x4500);        /* (C3,C2,C0) <-- 000 */
2068 77f8dd5a bellard
    if (ST0 < FT0)
2069 77f8dd5a bellard
        env->fpus |= 0x100;        /* (C3,C2,C0) <-- 001 */
2070 77f8dd5a bellard
    else if (ST0 == FT0)
2071 77f8dd5a bellard
        env->fpus |= 0x4000; /* (C3,C2,C0) <-- 100 */
2072 77f8dd5a bellard
    FORCE_RET();
2073 77f8dd5a bellard
}
2074 77f8dd5a bellard
2075 927f621e bellard
void OPPROTO op_fadd_ST0_FT0(void)
2076 927f621e bellard
{
2077 927f621e bellard
    ST0 += FT0;
2078 927f621e bellard
}
2079 927f621e bellard
2080 927f621e bellard
void OPPROTO op_fmul_ST0_FT0(void)
2081 927f621e bellard
{
2082 927f621e bellard
    ST0 *= FT0;
2083 927f621e bellard
}
2084 927f621e bellard
2085 927f621e bellard
void OPPROTO op_fsub_ST0_FT0(void)
2086 927f621e bellard
{
2087 927f621e bellard
    ST0 -= FT0;
2088 927f621e bellard
}
2089 927f621e bellard
2090 927f621e bellard
void OPPROTO op_fsubr_ST0_FT0(void)
2091 927f621e bellard
{
2092 927f621e bellard
    ST0 = FT0 - ST0;
2093 927f621e bellard
}
2094 927f621e bellard
2095 927f621e bellard
void OPPROTO op_fdiv_ST0_FT0(void)
2096 927f621e bellard
{
2097 927f621e bellard
    ST0 /= FT0;
2098 927f621e bellard
}
2099 927f621e bellard
2100 927f621e bellard
void OPPROTO op_fdivr_ST0_FT0(void)
2101 927f621e bellard
{
2102 927f621e bellard
    ST0 = FT0 / ST0;
2103 927f621e bellard
}
2104 927f621e bellard
2105 927f621e bellard
/* fp operations between STN and ST0 */
2106 927f621e bellard
2107 927f621e bellard
void OPPROTO op_fadd_STN_ST0(void)
2108 927f621e bellard
{
2109 927f621e bellard
    ST(PARAM1) += ST0;
2110 927f621e bellard
}
2111 927f621e bellard
2112 927f621e bellard
void OPPROTO op_fmul_STN_ST0(void)
2113 927f621e bellard
{
2114 927f621e bellard
    ST(PARAM1) *= ST0;
2115 927f621e bellard
}
2116 927f621e bellard
2117 927f621e bellard
void OPPROTO op_fsub_STN_ST0(void)
2118 927f621e bellard
{
2119 927f621e bellard
    ST(PARAM1) -= ST0;
2120 927f621e bellard
}
2121 927f621e bellard
2122 927f621e bellard
void OPPROTO op_fsubr_STN_ST0(void)
2123 927f621e bellard
{
2124 927f621e bellard
    CPU86_LDouble *p;
2125 927f621e bellard
    p = &ST(PARAM1);
2126 927f621e bellard
    *p = ST0 - *p;
2127 927f621e bellard
}
2128 927f621e bellard
2129 927f621e bellard
void OPPROTO op_fdiv_STN_ST0(void)
2130 927f621e bellard
{
2131 927f621e bellard
    ST(PARAM1) /= ST0;
2132 927f621e bellard
}
2133 927f621e bellard
2134 927f621e bellard
void OPPROTO op_fdivr_STN_ST0(void)
2135 927f621e bellard
{
2136 927f621e bellard
    CPU86_LDouble *p;
2137 927f621e bellard
    p = &ST(PARAM1);
2138 927f621e bellard
    *p = ST0 / *p;
2139 927f621e bellard
}
2140 927f621e bellard
2141 927f621e bellard
/* misc FPU operations */
2142 927f621e bellard
void OPPROTO op_fchs_ST0(void)
2143 927f621e bellard
{
2144 927f621e bellard
    ST0 = -ST0;
2145 927f621e bellard
}
2146 927f621e bellard
2147 927f621e bellard
void OPPROTO op_fabs_ST0(void)
2148 927f621e bellard
{
2149 927f621e bellard
    ST0 = fabs(ST0);
2150 927f621e bellard
}
2151 927f621e bellard
2152 77f8dd5a bellard
void helper_fxam_ST0(void)
2153 927f621e bellard
{
2154 927f621e bellard
    CPU86_LDoubleU temp;
2155 927f621e bellard
    int expdif;
2156 927f621e bellard
2157 927f621e bellard
    temp.d = ST0;
2158 927f621e bellard
2159 927f621e bellard
    env->fpus &= (~0x4700);  /* (C3,C2,C1,C0) <-- 0000 */
2160 927f621e bellard
    if (SIGND(temp))
2161 927f621e bellard
        env->fpus |= 0x200; /* C1 <-- 1 */
2162 927f621e bellard
2163 927f621e bellard
    expdif = EXPD(temp);
2164 927f621e bellard
    if (expdif == MAXEXPD) {
2165 927f621e bellard
        if (MANTD(temp) == 0)
2166 927f621e bellard
            env->fpus |=  0x500 /*Infinity*/;
2167 927f621e bellard
        else
2168 927f621e bellard
            env->fpus |=  0x100 /*NaN*/;
2169 927f621e bellard
    } else if (expdif == 0) {
2170 927f621e bellard
        if (MANTD(temp) == 0)
2171 927f621e bellard
            env->fpus |=  0x4000 /*Zero*/;
2172 927f621e bellard
        else
2173 927f621e bellard
            env->fpus |= 0x4400 /*Denormal*/;
2174 927f621e bellard
    } else {
2175 927f621e bellard
        env->fpus |= 0x400;
2176 927f621e bellard
    }
2177 77f8dd5a bellard
}
2178 77f8dd5a bellard
2179 77f8dd5a bellard
void OPPROTO op_fxam_ST0(void)
2180 77f8dd5a bellard
{
2181 77f8dd5a bellard
    helper_fxam_ST0();
2182 927f621e bellard
}
2183 927f621e bellard
2184 927f621e bellard
void OPPROTO op_fld1_ST0(void)
2185 927f621e bellard
{
2186 927f621e bellard
    ST0 = *(CPU86_LDouble *)&f15rk[1];
2187 927f621e bellard
}
2188 927f621e bellard
2189 77f8dd5a bellard
void OPPROTO op_fldl2t_ST0(void)
2190 927f621e bellard
{
2191 927f621e bellard
    ST0 = *(CPU86_LDouble *)&f15rk[6];
2192 927f621e bellard
}
2193 927f621e bellard
2194 77f8dd5a bellard
void OPPROTO op_fldl2e_ST0(void)
2195 927f621e bellard
{
2196 927f621e bellard
    ST0 = *(CPU86_LDouble *)&f15rk[5];
2197 927f621e bellard
}
2198 927f621e bellard
2199 927f621e bellard
void OPPROTO op_fldpi_ST0(void)
2200 927f621e bellard
{
2201 927f621e bellard
    ST0 = *(CPU86_LDouble *)&f15rk[2];
2202 927f621e bellard
}
2203 927f621e bellard
2204 927f621e bellard
void OPPROTO op_fldlg2_ST0(void)
2205 927f621e bellard
{
2206 927f621e bellard
    ST0 = *(CPU86_LDouble *)&f15rk[3];
2207 927f621e bellard
}
2208 927f621e bellard
2209 927f621e bellard
void OPPROTO op_fldln2_ST0(void)
2210 927f621e bellard
{
2211 927f621e bellard
    ST0 = *(CPU86_LDouble *)&f15rk[4];
2212 927f621e bellard
}
2213 927f621e bellard
2214 927f621e bellard
void OPPROTO op_fldz_ST0(void)
2215 927f621e bellard
{
2216 927f621e bellard
    ST0 = *(CPU86_LDouble *)&f15rk[0];
2217 927f621e bellard
}
2218 927f621e bellard
2219 927f621e bellard
void OPPROTO op_fldz_FT0(void)
2220 927f621e bellard
{
2221 927f621e bellard
    ST0 = *(CPU86_LDouble *)&f15rk[0];
2222 927f621e bellard
}
2223 927f621e bellard
2224 927f621e bellard
void helper_f2xm1(void)
2225 927f621e bellard
{
2226 927f621e bellard
    ST0 = pow(2.0,ST0) - 1.0;
2227 927f621e bellard
}
2228 927f621e bellard
2229 927f621e bellard
void helper_fyl2x(void)
2230 927f621e bellard
{
2231 927f621e bellard
    CPU86_LDouble fptemp;
2232 927f621e bellard
    
2233 927f621e bellard
    fptemp = ST0;
2234 927f621e bellard
    if (fptemp>0.0){
2235 927f621e bellard
        fptemp = log(fptemp)/log(2.0);         /* log2(ST) */
2236 927f621e bellard
        ST1 *= fptemp;
2237 927f621e bellard
        fpop();
2238 927f621e bellard
    } else { 
2239 927f621e bellard
        env->fpus &= (~0x4700);
2240 927f621e bellard
        env->fpus |= 0x400;
2241 927f621e bellard
    }
2242 927f621e bellard
}
2243 927f621e bellard
2244 927f621e bellard
void helper_fptan(void)
2245 927f621e bellard
{
2246 927f621e bellard
    CPU86_LDouble fptemp;
2247 927f621e bellard
2248 927f621e bellard
    fptemp = ST0;
2249 927f621e bellard
    if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2250 927f621e bellard
        env->fpus |= 0x400;
2251 927f621e bellard
    } else {
2252 927f621e bellard
        ST0 = tan(fptemp);
2253 927f621e bellard
        fpush();
2254 927f621e bellard
        ST0 = 1.0;
2255 927f621e bellard
        env->fpus &= (~0x400);  /* C2 <-- 0 */
2256 927f621e bellard
        /* the above code is for  |arg| < 2**52 only */
2257 927f621e bellard
    }
2258 927f621e bellard
}
2259 927f621e bellard
2260 927f621e bellard
void helper_fpatan(void)
2261 927f621e bellard
{
2262 927f621e bellard
    CPU86_LDouble fptemp, fpsrcop;
2263 927f621e bellard
2264 927f621e bellard
    fpsrcop = ST1;
2265 927f621e bellard
    fptemp = ST0;
2266 927f621e bellard
    ST1 = atan2(fpsrcop,fptemp);
2267 927f621e bellard
    fpop();
2268 927f621e bellard
}
2269 927f621e bellard
2270 927f621e bellard
void helper_fxtract(void)
2271 927f621e bellard
{
2272 927f621e bellard
    CPU86_LDoubleU temp;
2273 927f621e bellard
    unsigned int expdif;
2274 927f621e bellard
2275 927f621e bellard
    temp.d = ST0;
2276 927f621e bellard
    expdif = EXPD(temp) - EXPBIAS;
2277 927f621e bellard
    /*DP exponent bias*/
2278 927f621e bellard
    ST0 = expdif;
2279 927f621e bellard
    fpush();
2280 927f621e bellard
    BIASEXPONENT(temp);
2281 927f621e bellard
    ST0 = temp.d;
2282 927f621e bellard
}
2283 927f621e bellard
2284 927f621e bellard
void helper_fprem1(void)
2285 927f621e bellard
{
2286 927f621e bellard
    CPU86_LDouble dblq, fpsrcop, fptemp;
2287 927f621e bellard
    CPU86_LDoubleU fpsrcop1, fptemp1;
2288 927f621e bellard
    int expdif;
2289 927f621e bellard
    int q;
2290 927f621e bellard
2291 927f621e bellard
    fpsrcop = ST0;
2292 927f621e bellard
    fptemp = ST1;
2293 927f621e bellard
    fpsrcop1.d = fpsrcop;
2294 927f621e bellard
    fptemp1.d = fptemp;
2295 927f621e bellard
    expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
2296 927f621e bellard
    if (expdif < 53) {
2297 927f621e bellard
        dblq = fpsrcop / fptemp;
2298 927f621e bellard
        dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
2299 927f621e bellard
        ST0 = fpsrcop - fptemp*dblq;
2300 927f621e bellard
        q = (int)dblq; /* cutting off top bits is assumed here */
2301 927f621e bellard
        env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2302 927f621e bellard
                                /* (C0,C1,C3) <-- (q2,q1,q0) */
2303 927f621e bellard
        env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
2304 927f621e bellard
        env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
2305 927f621e bellard
        env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
2306 927f621e bellard
    } else {
2307 927f621e bellard
        env->fpus |= 0x400;  /* C2 <-- 1 */
2308 927f621e bellard
        fptemp = pow(2.0, expdif-50);
2309 927f621e bellard
        fpsrcop = (ST0 / ST1) / fptemp;
2310 927f621e bellard
        /* fpsrcop = integer obtained by rounding to the nearest */
2311 927f621e bellard
        fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
2312 927f621e bellard
            floor(fpsrcop): ceil(fpsrcop);
2313 927f621e bellard
        ST0 -= (ST1 * fpsrcop * fptemp);
2314 927f621e bellard
    }
2315 927f621e bellard
}
2316 927f621e bellard
2317 927f621e bellard
void helper_fprem(void)
2318 927f621e bellard
{
2319 927f621e bellard
    CPU86_LDouble dblq, fpsrcop, fptemp;
2320 927f621e bellard
    CPU86_LDoubleU fpsrcop1, fptemp1;
2321 927f621e bellard
    int expdif;
2322 927f621e bellard
    int q;
2323 927f621e bellard
    
2324 927f621e bellard
    fpsrcop = ST0;
2325 927f621e bellard
    fptemp = ST1;
2326 927f621e bellard
    fpsrcop1.d = fpsrcop;
2327 927f621e bellard
    fptemp1.d = fptemp;
2328 927f621e bellard
    expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
2329 927f621e bellard
    if ( expdif < 53 ) {
2330 927f621e bellard
        dblq = fpsrcop / fptemp;
2331 927f621e bellard
        dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
2332 927f621e bellard
        ST0 = fpsrcop - fptemp*dblq;
2333 927f621e bellard
        q = (int)dblq; /* cutting off top bits is assumed here */
2334 927f621e bellard
        env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
2335 927f621e bellard
                                /* (C0,C1,C3) <-- (q2,q1,q0) */
2336 927f621e bellard
        env->fpus |= (q&0x4) << 6; /* (C0) <-- q2 */
2337 927f621e bellard
        env->fpus |= (q&0x2) << 8; /* (C1) <-- q1 */
2338 927f621e bellard
        env->fpus |= (q&0x1) << 14; /* (C3) <-- q0 */
2339 927f621e bellard
    } else {
2340 927f621e bellard
        env->fpus |= 0x400;  /* C2 <-- 1 */
2341 927f621e bellard
        fptemp = pow(2.0, expdif-50);
2342 927f621e bellard
        fpsrcop = (ST0 / ST1) / fptemp;
2343 927f621e bellard
        /* fpsrcop = integer obtained by chopping */
2344 927f621e bellard
        fpsrcop = (fpsrcop < 0.0)?
2345 927f621e bellard
            -(floor(fabs(fpsrcop))): floor(fpsrcop);
2346 927f621e bellard
        ST0 -= (ST1 * fpsrcop * fptemp);
2347 927f621e bellard
    }
2348 927f621e bellard
}
2349 927f621e bellard
2350 927f621e bellard
void helper_fyl2xp1(void)
2351 927f621e bellard
{
2352 927f621e bellard
    CPU86_LDouble fptemp;
2353 927f621e bellard
2354 927f621e bellard
    fptemp = ST0;
2355 927f621e bellard
    if ((fptemp+1.0)>0.0) {
2356 927f621e bellard
        fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
2357 927f621e bellard
        ST1 *= fptemp;
2358 927f621e bellard
        fpop();
2359 927f621e bellard
    } else { 
2360 927f621e bellard
        env->fpus &= (~0x4700);
2361 927f621e bellard
        env->fpus |= 0x400;
2362 927f621e bellard
    }
2363 927f621e bellard
}
2364 927f621e bellard
2365 927f621e bellard
void helper_fsqrt(void)
2366 927f621e bellard
{
2367 927f621e bellard
    CPU86_LDouble fptemp;
2368 927f621e bellard
2369 927f621e bellard
    fptemp = ST0;
2370 927f621e bellard
    if (fptemp<0.0) { 
2371 927f621e bellard
        env->fpus &= (~0x4700);  /* (C3,C2,C1,C0) <-- 0000 */
2372 927f621e bellard
        env->fpus |= 0x400;
2373 927f621e bellard
    }
2374 927f621e bellard
    ST0 = sqrt(fptemp);
2375 927f621e bellard
}
2376 927f621e bellard
2377 927f621e bellard
void helper_fsincos(void)
2378 927f621e bellard
{
2379 927f621e bellard
    CPU86_LDouble fptemp;
2380 927f621e bellard
2381 927f621e bellard
    fptemp = ST0;
2382 927f621e bellard
    if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2383 927f621e bellard
        env->fpus |= 0x400;
2384 927f621e bellard
    } else {
2385 927f621e bellard
        ST0 = sin(fptemp);
2386 927f621e bellard
        fpush();
2387 927f621e bellard
        ST0 = cos(fptemp);
2388 927f621e bellard
        env->fpus &= (~0x400);  /* C2 <-- 0 */
2389 927f621e bellard
        /* the above code is for  |arg| < 2**63 only */
2390 927f621e bellard
    }
2391 927f621e bellard
}
2392 927f621e bellard
2393 927f621e bellard
void helper_frndint(void)
2394 927f621e bellard
{
2395 927f621e bellard
    ST0 = rint(ST0);
2396 927f621e bellard
}
2397 927f621e bellard
2398 927f621e bellard
void helper_fscale(void)
2399 927f621e bellard
{
2400 927f621e bellard
    CPU86_LDouble fpsrcop, fptemp;
2401 927f621e bellard
2402 927f621e bellard
    fpsrcop = 2.0;
2403 927f621e bellard
    fptemp = pow(fpsrcop,ST1);
2404 927f621e bellard
    ST0 *= fptemp;
2405 927f621e bellard
}
2406 927f621e bellard
2407 927f621e bellard
void helper_fsin(void)
2408 927f621e bellard
{
2409 927f621e bellard
    CPU86_LDouble fptemp;
2410 927f621e bellard
2411 927f621e bellard
    fptemp = ST0;
2412 927f621e bellard
    if ((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2413 927f621e bellard
        env->fpus |= 0x400;
2414 927f621e bellard
    } else {
2415 927f621e bellard
        ST0 = sin(fptemp);
2416 927f621e bellard
        env->fpus &= (~0x400);  /* C2 <-- 0 */
2417 927f621e bellard
        /* the above code is for  |arg| < 2**53 only */
2418 927f621e bellard
    }
2419 927f621e bellard
}
2420 927f621e bellard
2421 927f621e bellard
void helper_fcos(void)
2422 927f621e bellard
{
2423 927f621e bellard
    CPU86_LDouble fptemp;
2424 927f621e bellard
2425 927f621e bellard
    fptemp = ST0;
2426 927f621e bellard
    if((fptemp > MAXTAN)||(fptemp < -MAXTAN)) {
2427 927f621e bellard
        env->fpus |= 0x400;
2428 927f621e bellard
    } else {
2429 927f621e bellard
        ST0 = cos(fptemp);
2430 927f621e bellard
        env->fpus &= (~0x400);  /* C2 <-- 0 */
2431 927f621e bellard
        /* the above code is for  |arg5 < 2**63 only */
2432 927f621e bellard
    }
2433 927f621e bellard
}
2434 927f621e bellard
2435 927f621e bellard
/* associated heplers to reduce generated code length and to simplify
2436 927f621e bellard
   relocation (FP constants are usually stored in .rodata section) */
2437 927f621e bellard
2438 927f621e bellard
void OPPROTO op_f2xm1(void)
2439 927f621e bellard
{
2440 927f621e bellard
    helper_f2xm1();
2441 927f621e bellard
}
2442 927f621e bellard
2443 927f621e bellard
void OPPROTO op_fyl2x(void)
2444 927f621e bellard
{
2445 927f621e bellard
    helper_fyl2x();
2446 927f621e bellard
}
2447 927f621e bellard
2448 927f621e bellard
void OPPROTO op_fptan(void)
2449 927f621e bellard
{
2450 927f621e bellard
    helper_fptan();
2451 927f621e bellard
}
2452 927f621e bellard
2453 927f621e bellard
void OPPROTO op_fpatan(void)
2454 927f621e bellard
{
2455 927f621e bellard
    helper_fpatan();
2456 927f621e bellard
}
2457 927f621e bellard
2458 927f621e bellard
void OPPROTO op_fxtract(void)
2459 927f621e bellard
{
2460 927f621e bellard
    helper_fxtract();
2461 927f621e bellard
}
2462 927f621e bellard
2463 927f621e bellard
void OPPROTO op_fprem1(void)
2464 927f621e bellard
{
2465 927f621e bellard
    helper_fprem1();
2466 927f621e bellard
}
2467 927f621e bellard
2468 927f621e bellard
2469 927f621e bellard
void OPPROTO op_fprem(void)
2470 927f621e bellard
{
2471 927f621e bellard
    helper_fprem();
2472 927f621e bellard
}
2473 927f621e bellard
2474 927f621e bellard
void OPPROTO op_fyl2xp1(void)
2475 927f621e bellard
{
2476 927f621e bellard
    helper_fyl2xp1();
2477 927f621e bellard
}
2478 927f621e bellard
2479 927f621e bellard
void OPPROTO op_fsqrt(void)
2480 927f621e bellard
{
2481 927f621e bellard
    helper_fsqrt();
2482 927f621e bellard
}
2483 927f621e bellard
2484 927f621e bellard
void OPPROTO op_fsincos(void)
2485 927f621e bellard
{
2486 927f621e bellard
    helper_fsincos();
2487 927f621e bellard
}
2488 927f621e bellard
2489 927f621e bellard
void OPPROTO op_frndint(void)
2490 927f621e bellard
{
2491 927f621e bellard
    helper_frndint();
2492 927f621e bellard
}
2493 927f621e bellard
2494 927f621e bellard
void OPPROTO op_fscale(void)
2495 927f621e bellard
{
2496 927f621e bellard
    helper_fscale();
2497 927f621e bellard
}
2498 927f621e bellard
2499 927f621e bellard
void OPPROTO op_fsin(void)
2500 927f621e bellard
{
2501 927f621e bellard
    helper_fsin();
2502 927f621e bellard
}
2503 927f621e bellard
2504 927f621e bellard
void OPPROTO op_fcos(void)
2505 927f621e bellard
{
2506 927f621e bellard
    helper_fcos();
2507 927f621e bellard
}
2508 927f621e bellard
2509 4b74fe1f bellard
void OPPROTO op_fnstsw_A0(void)
2510 4b74fe1f bellard
{
2511 4b74fe1f bellard
    int fpus;
2512 4b74fe1f bellard
    fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
2513 4b74fe1f bellard
    stw((void *)A0, fpus);
2514 4b74fe1f bellard
}
2515 4b74fe1f bellard
2516 77f8dd5a bellard
void OPPROTO op_fnstsw_EAX(void)
2517 77f8dd5a bellard
{
2518 77f8dd5a bellard
    int fpus;
2519 77f8dd5a bellard
    fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
2520 77f8dd5a bellard
    EAX = (EAX & 0xffff0000) | fpus;
2521 77f8dd5a bellard
}
2522 77f8dd5a bellard
2523 4b74fe1f bellard
void OPPROTO op_fnstcw_A0(void)
2524 4b74fe1f bellard
{
2525 4b74fe1f bellard
    stw((void *)A0, env->fpuc);
2526 4b74fe1f bellard
}
2527 4b74fe1f bellard
2528 4b74fe1f bellard
void OPPROTO op_fldcw_A0(void)
2529 4b74fe1f bellard
{
2530 4b74fe1f bellard
    int rnd_type;
2531 4b74fe1f bellard
    env->fpuc = lduw((void *)A0);
2532 4b74fe1f bellard
    /* set rounding mode */
2533 4b74fe1f bellard
    switch(env->fpuc & RC_MASK) {
2534 4b74fe1f bellard
    default:
2535 4b74fe1f bellard
    case RC_NEAR:
2536 4b74fe1f bellard
        rnd_type = FE_TONEAREST;
2537 4b74fe1f bellard
        break;
2538 4b74fe1f bellard
    case RC_DOWN:
2539 4b74fe1f bellard
        rnd_type = FE_DOWNWARD;
2540 4b74fe1f bellard
        break;
2541 4b74fe1f bellard
    case RC_UP:
2542 4b74fe1f bellard
        rnd_type = FE_UPWARD;
2543 4b74fe1f bellard
        break;
2544 4b74fe1f bellard
    case RC_CHOP:
2545 4b74fe1f bellard
        rnd_type = FE_TOWARDZERO;
2546 4b74fe1f bellard
        break;
2547 4b74fe1f bellard
    }
2548 4b74fe1f bellard
    fesetround(rnd_type);
2549 4b74fe1f bellard
}
2550 4b74fe1f bellard
2551 1a9353d2 bellard
void OPPROTO op_fclex(void)
2552 1a9353d2 bellard
{
2553 1a9353d2 bellard
    env->fpus &= 0x7f00;
2554 1a9353d2 bellard
}
2555 1a9353d2 bellard
2556 1a9353d2 bellard
void OPPROTO op_fninit(void)
2557 1a9353d2 bellard
{
2558 1a9353d2 bellard
    env->fpus = 0;
2559 1a9353d2 bellard
    env->fpstt = 0;
2560 1a9353d2 bellard
    env->fpuc = 0x37f;
2561 1a9353d2 bellard
    env->fptags[0] = 1;
2562 1a9353d2 bellard
    env->fptags[1] = 1;
2563 1a9353d2 bellard
    env->fptags[2] = 1;
2564 1a9353d2 bellard
    env->fptags[3] = 1;
2565 1a9353d2 bellard
    env->fptags[4] = 1;
2566 1a9353d2 bellard
    env->fptags[5] = 1;
2567 1a9353d2 bellard
    env->fptags[6] = 1;
2568 1a9353d2 bellard
    env->fptags[7] = 1;
2569 1a9353d2 bellard
}
2570 1b6b029e bellard
2571 1b6b029e bellard
/* threading support */
2572 1b6b029e bellard
void OPPROTO op_lock(void)
2573 1b6b029e bellard
{
2574 1b6b029e bellard
    cpu_lock();
2575 1b6b029e bellard
}
2576 1b6b029e bellard
2577 1b6b029e bellard
void OPPROTO op_unlock(void)
2578 1b6b029e bellard
{
2579 1b6b029e bellard
    cpu_unlock();
2580 1b6b029e bellard
}