Revision b56dad1c exec-i386.c
| b/exec-i386.c | ||
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/* exception support */ |
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/* NOTE: not static to force relocation generation by GCC */ |
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void raise_exception(int exception_index)
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void raise_exception_err(int exception_index, int error_code)
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{
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/* NOTE: the register at this point must be saved by hand because |
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longjmp restore them */ |
| ... | ... | |
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env->regs[R_EDI] = EDI; |
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#endif |
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env->exception_index = exception_index; |
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env->error_code = error_code; |
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longjmp(env->jmp_env, 1); |
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} |
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/* short cut if error_code is 0 or not present */ |
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void raise_exception(int exception_index) |
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{
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raise_exception_err(exception_index, 0); |
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} |
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#if defined(DEBUG_EXEC) |
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static const char *cc_op_str[] = {
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"DYNAMIC", |
| ... | ... | |
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static void cpu_x86_dump_state(FILE *f) |
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{
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int eflags; |
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char cc_op_name[32]; |
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eflags = cc_table[CC_OP].compute_all(); |
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eflags |= (DF & DF_MASK); |
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if ((unsigned)env->cc_op < CC_OP_NB) |
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strcpy(cc_op_name, cc_op_str[env->cc_op]); |
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else |
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snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); |
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fprintf(f, |
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"EAX=%08x EBX=%08X ECX=%08x EDX=%08x\n" |
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"ESI=%08x EDI=%08X EBP=%08x ESP=%08x\n" |
| ... | ... | |
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"EIP=%08x\n", |
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env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX], |
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env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP], |
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env->cc_src, env->cc_dst, cc_op_str[env->cc_op],
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env->cc_src, env->cc_dst, cc_op_name,
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eflags & DF_MASK ? 'D' : '-', |
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eflags & CC_O ? 'O' : '-', |
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eflags & CC_S ? 'S' : '-', |
| ... | ... | |
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h = pc & (CODE_GEN_HASH_SIZE - 1); |
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ptb = &tb_hash[h]; |
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for(;;) {
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tb = *ptb; |
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if (!tb) |
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break; |
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if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags) |
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#if 0 |
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/* XXX: hack to handle 16 bit modyfing code */ |
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if (flags & (1 << GEN_FLAG_CODE32_SHIFT)) |
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#endif |
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for(;;) {
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tb = *ptb; |
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if (!tb) |
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break; |
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if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags) |
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return tb; |
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ptb = &tb->hash_next; |
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} |
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ptb = &tb->hash_next;
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}
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*pptb = ptb; |
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return NULL; |
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} |
| ... | ... | |
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(unsigned long)env->seg_cache[R_SS].base) != 0) << |
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GEN_FLAG_ADDSEG_SHIFT; |
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flags |= (env->eflags & VM_MASK) >> (17 - GEN_FLAG_VM_SHIFT); |
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flags |= (env->eflags & IOPL_MASK) >> (12 - GEN_FLAG_IOPL_SHIFT); |
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flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT; |
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cs_base = env->seg_cache[R_CS].base; |
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pc = cs_base + env->eip; |
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tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, |
| ... | ... | |
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#include <signal.h> |
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#include <sys/ucontext.h> |
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/* 'pc' is the host PC at which the exception was raised. 'address' is |
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the effective address of the memory exception */ |
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static inline int handle_cpu_signal(unsigned long pc, |
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unsigned long address, |
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sigset_t *old_set) |
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{
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#ifdef DEBUG_SIGNAL |
| ... | ... | |
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sigprocmask(SIG_SETMASK, old_set, NULL); |
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/* XXX: need to compute virtual pc position by retranslating |
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code. The rest of the CPU state should be correct. */ |
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raise_exception(EXCP0D_GPF); |
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env->cr2 = address; |
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/* XXX: more precise exception code */ |
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raise_exception_err(EXCP0E_PAGE, 4); |
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/* never comes here */ |
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return 1; |
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} else {
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| ... | ... | |
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#endif |
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pc = uc->uc_mcontext.gregs[REG_EIP]; |
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pold_set = &uc->uc_sigmask; |
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return handle_cpu_signal(pc, pold_set); |
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return handle_cpu_signal(pc, (unsigned long)info->si_addr, pold_set);
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#else |
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#warning No CPU specific signal handler: cannot handle target SIGSEGV events |
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return 0; |
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