Revision b5b38f61 target-i386/translate.c
| b/target-i386/translate.c | ||
|---|---|---|
| 2275 | 2275 |
gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
| 2276 | 2276 |
gen_op_st_T0_A0(ot + s->mem_index); |
| 2277 | 2277 |
if (level) {
|
| 2278 |
gen_op_enter64_level(level, (ot == OT_QUAD)); |
|
| 2278 |
/* XXX: must save state */ |
|
| 2279 |
tcg_gen_helper_0_2(helper_enter64_level, |
|
| 2280 |
tcg_const_i32(level), |
|
| 2281 |
tcg_const_i32((ot == OT_QUAD))); |
|
| 2279 | 2282 |
} |
| 2280 | 2283 |
gen_op_mov_reg_T1(ot, R_EBP); |
| 2281 | 2284 |
gen_op_addl_T1_im( -esp_addend + (-opsize * level) ); |
| ... | ... | |
| 2297 | 2300 |
gen_op_mov_TN_reg(OT_LONG, 0, R_EBP); |
| 2298 | 2301 |
gen_op_st_T0_A0(ot + s->mem_index); |
| 2299 | 2302 |
if (level) {
|
| 2300 |
gen_op_enter_level(level, s->dflag); |
|
| 2303 |
/* XXX: must save state */ |
|
| 2304 |
tcg_gen_helper_0_2(helper_enter_level, |
|
| 2305 |
tcg_const_i32(level), |
|
| 2306 |
tcg_const_i32(s->dflag)); |
|
| 2301 | 2307 |
} |
| 2302 | 2308 |
gen_op_mov_reg_T1(ot, R_EBP); |
| 2303 | 2309 |
gen_op_addl_T1_im( -esp_addend + (-opsize * level) ); |
| ... | ... | |
| 2310 | 2316 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 2311 | 2317 |
gen_op_set_cc_op(s->cc_op); |
| 2312 | 2318 |
gen_jmp_im(cur_eip); |
| 2313 |
gen_op_raise_exception(trapno);
|
|
| 2319 |
tcg_gen_helper_0_1(helper_raise_exception, tcg_const_i32(trapno));
|
|
| 2314 | 2320 |
s->is_jmp = 3; |
| 2315 | 2321 |
} |
| 2316 | 2322 |
|
| ... | ... | |
| 2322 | 2328 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 2323 | 2329 |
gen_op_set_cc_op(s->cc_op); |
| 2324 | 2330 |
gen_jmp_im(cur_eip); |
| 2325 |
gen_op_raise_interrupt(intno, (int)(next_eip - cur_eip)); |
|
| 2331 |
tcg_gen_helper_0_2(helper_raise_interrupt, |
|
| 2332 |
tcg_const_i32(intno), |
|
| 2333 |
tcg_const_i32(next_eip - cur_eip)); |
|
| 2326 | 2334 |
s->is_jmp = 3; |
| 2327 | 2335 |
} |
| 2328 | 2336 |
|
| ... | ... | |
| 2331 | 2339 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 2332 | 2340 |
gen_op_set_cc_op(s->cc_op); |
| 2333 | 2341 |
gen_jmp_im(cur_eip); |
| 2334 |
gen_op_debug();
|
|
| 2342 |
tcg_gen_helper_0_0(helper_debug);
|
|
| 2335 | 2343 |
s->is_jmp = 3; |
| 2336 | 2344 |
} |
| 2337 | 2345 |
|
| ... | ... | |
| 2342 | 2350 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 2343 | 2351 |
gen_op_set_cc_op(s->cc_op); |
| 2344 | 2352 |
if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
|
| 2345 |
gen_op_reset_inhibit_irq();
|
|
| 2353 |
tcg_gen_helper_0_0(helper_reset_inhibit_irq);
|
|
| 2346 | 2354 |
} |
| 2347 | 2355 |
if (s->singlestep_enabled) {
|
| 2348 |
gen_op_debug();
|
|
| 2356 |
tcg_gen_helper_0_0(helper_debug);
|
|
| 2349 | 2357 |
} else if (s->tf) {
|
| 2350 |
gen_op_single_step();
|
|
| 2358 |
tcg_gen_helper_0_0(helper_single_step);
|
|
| 2351 | 2359 |
} else {
|
| 2352 | 2360 |
tcg_gen_exit_tb(0); |
| 2353 | 2361 |
} |
| ... | ... | |
| 3659 | 3667 |
switch(ot) {
|
| 3660 | 3668 |
case OT_BYTE: |
| 3661 | 3669 |
gen_jmp_im(pc_start - s->cs_base); |
| 3662 |
gen_op_divb_AL_T0();
|
|
| 3670 |
tcg_gen_helper_0_1(helper_divb_AL, cpu_T[0]);
|
|
| 3663 | 3671 |
break; |
| 3664 | 3672 |
case OT_WORD: |
| 3665 | 3673 |
gen_jmp_im(pc_start - s->cs_base); |
| 3666 |
gen_op_divw_AX_T0();
|
|
| 3674 |
tcg_gen_helper_0_1(helper_divw_AX, cpu_T[0]);
|
|
| 3667 | 3675 |
break; |
| 3668 | 3676 |
default: |
| 3669 | 3677 |
case OT_LONG: |
| 3670 | 3678 |
gen_jmp_im(pc_start - s->cs_base); |
| 3671 |
#ifdef MACRO_TEST |
|
| 3672 |
/* XXX: this is just a test */ |
|
| 3673 |
tcg_gen_macro_2(cpu_T[0], cpu_T[0], MACRO_TEST); |
|
| 3674 |
#else |
|
| 3675 |
tcg_gen_helper_0_1(helper_divl_EAX_T0, cpu_T[0]); |
|
| 3676 |
#endif |
|
| 3679 |
tcg_gen_helper_0_1(helper_divl_EAX, cpu_T[0]); |
|
| 3677 | 3680 |
break; |
| 3678 | 3681 |
#ifdef TARGET_X86_64 |
| 3679 | 3682 |
case OT_QUAD: |
| 3680 | 3683 |
gen_jmp_im(pc_start - s->cs_base); |
| 3681 |
gen_op_divq_EAX_T0();
|
|
| 3684 |
tcg_gen_helper_0_1(helper_divq_EAX, cpu_T[0]);
|
|
| 3682 | 3685 |
break; |
| 3683 | 3686 |
#endif |
| 3684 | 3687 |
} |
| ... | ... | |
| 3687 | 3690 |
switch(ot) {
|
| 3688 | 3691 |
case OT_BYTE: |
| 3689 | 3692 |
gen_jmp_im(pc_start - s->cs_base); |
| 3690 |
gen_op_idivb_AL_T0();
|
|
| 3693 |
tcg_gen_helper_0_1(helper_idivb_AL, cpu_T[0]);
|
|
| 3691 | 3694 |
break; |
| 3692 | 3695 |
case OT_WORD: |
| 3693 | 3696 |
gen_jmp_im(pc_start - s->cs_base); |
| 3694 |
gen_op_idivw_AX_T0();
|
|
| 3697 |
tcg_gen_helper_0_1(helper_idivw_AX, cpu_T[0]);
|
|
| 3695 | 3698 |
break; |
| 3696 | 3699 |
default: |
| 3697 | 3700 |
case OT_LONG: |
| 3698 | 3701 |
gen_jmp_im(pc_start - s->cs_base); |
| 3699 |
tcg_gen_helper_0_1(helper_idivl_EAX_T0, cpu_T[0]);
|
|
| 3702 |
tcg_gen_helper_0_1(helper_idivl_EAX, cpu_T[0]); |
|
| 3700 | 3703 |
break; |
| 3701 | 3704 |
#ifdef TARGET_X86_64 |
| 3702 | 3705 |
case OT_QUAD: |
| 3703 | 3706 |
gen_jmp_im(pc_start - s->cs_base); |
| 3704 |
gen_op_idivq_EAX_T0();
|
|
| 3707 |
tcg_gen_helper_0_1(helper_idivq_EAX, cpu_T[0]);
|
|
| 3705 | 3708 |
break; |
| 3706 | 3709 |
#endif |
| 3707 | 3710 |
} |
| ... | ... | |
| 4088 | 4091 |
/* If several instructions disable interrupts, only the |
| 4089 | 4092 |
_first_ does it */ |
| 4090 | 4093 |
if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) |
| 4091 |
gen_op_set_inhibit_irq();
|
|
| 4094 |
tcg_gen_helper_0_0(helper_set_inhibit_irq);
|
|
| 4092 | 4095 |
s->tf = 0; |
| 4093 | 4096 |
} |
| 4094 | 4097 |
if (s->is_jmp) {
|
| ... | ... | |
| 4164 | 4167 |
/* If several instructions disable interrupts, only the |
| 4165 | 4168 |
_first_ does it */ |
| 4166 | 4169 |
if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) |
| 4167 |
gen_op_set_inhibit_irq();
|
|
| 4170 |
tcg_gen_helper_0_0(helper_set_inhibit_irq);
|
|
| 4168 | 4171 |
s->tf = 0; |
| 4169 | 4172 |
} |
| 4170 | 4173 |
if (s->is_jmp) {
|
| ... | ... | |
| 5471 | 5474 |
s->cc_op = CC_OP_EFLAGS; |
| 5472 | 5475 |
break; |
| 5473 | 5476 |
case 0xfc: /* cld */ |
| 5474 |
gen_op_cld(); |
|
| 5477 |
tcg_gen_movi_i32(cpu_tmp2, 1); |
|
| 5478 |
tcg_gen_st_i32(cpu_tmp2, cpu_env, offsetof(CPUState, df)); |
|
| 5475 | 5479 |
break; |
| 5476 | 5480 |
case 0xfd: /* std */ |
| 5477 |
gen_op_std(); |
|
| 5481 |
tcg_gen_movi_i32(cpu_tmp2, -1); |
|
| 5482 |
tcg_gen_st_i32(cpu_tmp2, cpu_env, offsetof(CPUState, df)); |
|
| 5478 | 5483 |
break; |
| 5479 | 5484 |
|
| 5480 | 5485 |
/************************/ |
| ... | ... | |
| 5670 | 5675 |
case 0xfa: /* cli */ |
| 5671 | 5676 |
if (!s->vm86) {
|
| 5672 | 5677 |
if (s->cpl <= s->iopl) {
|
| 5673 |
gen_op_cli();
|
|
| 5678 |
tcg_gen_helper_0_0(helper_cli);
|
|
| 5674 | 5679 |
} else {
|
| 5675 | 5680 |
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
| 5676 | 5681 |
} |
| 5677 | 5682 |
} else {
|
| 5678 | 5683 |
if (s->iopl == 3) {
|
| 5679 |
gen_op_cli();
|
|
| 5684 |
tcg_gen_helper_0_0(helper_cli);
|
|
| 5680 | 5685 |
} else {
|
| 5681 | 5686 |
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); |
| 5682 | 5687 |
} |
| ... | ... | |
| 5686 | 5691 |
if (!s->vm86) {
|
| 5687 | 5692 |
if (s->cpl <= s->iopl) {
|
| 5688 | 5693 |
gen_sti: |
| 5689 |
gen_op_sti();
|
|
| 5694 |
tcg_gen_helper_0_0(helper_sti);
|
|
| 5690 | 5695 |
/* interruptions are enabled only the first insn after sti */ |
| 5691 | 5696 |
/* If several instructions disable interrupts, only the |
| 5692 | 5697 |
_first_ does it */ |
| 5693 | 5698 |
if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK)) |
| 5694 |
gen_op_set_inhibit_irq();
|
|
| 5699 |
tcg_gen_helper_0_0(helper_set_inhibit_irq);
|
|
| 5695 | 5700 |
/* give a chance to handle pending irqs */ |
| 5696 | 5701 |
gen_jmp_im(s->pc - s->cs_base); |
| 5697 | 5702 |
gen_eob(s); |
| ... | ... | |
| 5719 | 5724 |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
| 5720 | 5725 |
gen_jmp_im(pc_start - s->cs_base); |
| 5721 | 5726 |
if (ot == OT_WORD) |
| 5722 |
gen_op_boundw();
|
|
| 5727 |
tcg_gen_helper_0_0(helper_boundw);
|
|
| 5723 | 5728 |
else |
| 5724 |
gen_op_boundl();
|
|
| 5729 |
tcg_gen_helper_0_0(helper_boundl);
|
|
| 5725 | 5730 |
break; |
| 5726 | 5731 |
case 0x1c8 ... 0x1cf: /* bswap reg */ |
| 5727 | 5732 |
reg = (b & 7) | REX_B(s); |
| ... | ... | |
| 5800 | 5805 |
int retval = 0; |
| 5801 | 5806 |
if (b & 2) {
|
| 5802 | 5807 |
retval = gen_svm_check_intercept_param(s, pc_start, SVM_EXIT_MSR, 0); |
| 5803 |
gen_op_rdmsr();
|
|
| 5808 |
tcg_gen_helper_0_0(helper_rdmsr);
|
|
| 5804 | 5809 |
} else {
|
| 5805 | 5810 |
retval = gen_svm_check_intercept_param(s, pc_start, SVM_EXIT_MSR, 1); |
| 5806 |
gen_op_wrmsr();
|
|
| 5811 |
tcg_gen_helper_0_0(helper_wrmsr);
|
|
| 5807 | 5812 |
} |
| 5808 | 5813 |
if(retval) |
| 5809 | 5814 |
gen_eob(s); |
| ... | ... | |
| 5813 | 5818 |
if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_RDTSC)) |
| 5814 | 5819 |
break; |
| 5815 | 5820 |
gen_jmp_im(pc_start - s->cs_base); |
| 5816 |
gen_op_rdtsc();
|
|
| 5821 |
tcg_gen_helper_0_0(helper_rdtsc);
|
|
| 5817 | 5822 |
break; |
| 5818 | 5823 |
case 0x133: /* rdpmc */ |
| 5819 | 5824 |
gen_jmp_im(pc_start - s->cs_base); |
| 5820 |
gen_op_rdpmc();
|
|
| 5825 |
tcg_gen_helper_0_0(helper_rdpmc);
|
|
| 5821 | 5826 |
break; |
| 5822 | 5827 |
case 0x134: /* sysenter */ |
| 5823 | 5828 |
if (CODE64(s)) |
| ... | ... | |
| 5830 | 5835 |
s->cc_op = CC_OP_DYNAMIC; |
| 5831 | 5836 |
} |
| 5832 | 5837 |
gen_jmp_im(pc_start - s->cs_base); |
| 5833 |
gen_op_sysenter();
|
|
| 5838 |
tcg_gen_helper_0_0(helper_sysenter);
|
|
| 5834 | 5839 |
gen_eob(s); |
| 5835 | 5840 |
} |
| 5836 | 5841 |
break; |
| ... | ... | |
| 5845 | 5850 |
s->cc_op = CC_OP_DYNAMIC; |
| 5846 | 5851 |
} |
| 5847 | 5852 |
gen_jmp_im(pc_start - s->cs_base); |
| 5848 |
gen_op_sysexit();
|
|
| 5853 |
tcg_gen_helper_0_0(helper_sysexit);
|
|
| 5849 | 5854 |
gen_eob(s); |
| 5850 | 5855 |
} |
| 5851 | 5856 |
break; |
| ... | ... | |
| 5857 | 5862 |
s->cc_op = CC_OP_DYNAMIC; |
| 5858 | 5863 |
} |
| 5859 | 5864 |
gen_jmp_im(pc_start - s->cs_base); |
| 5860 |
gen_op_syscall(s->pc - pc_start);
|
|
| 5865 |
tcg_gen_helper_0_1(helper_syscall, tcg_const_i32(s->pc - pc_start));
|
|
| 5861 | 5866 |
gen_eob(s); |
| 5862 | 5867 |
break; |
| 5863 | 5868 |
case 0x107: /* sysret */ |
| ... | ... | |
| 5869 | 5874 |
s->cc_op = CC_OP_DYNAMIC; |
| 5870 | 5875 |
} |
| 5871 | 5876 |
gen_jmp_im(pc_start - s->cs_base); |
| 5872 |
gen_op_sysret(s->dflag);
|
|
| 5877 |
tcg_gen_helper_0_1(helper_sysret, tcg_const_i32(s->dflag));
|
|
| 5873 | 5878 |
/* condition codes are modified only in long mode */ |
| 5874 | 5879 |
if (s->lma) |
| 5875 | 5880 |
s->cc_op = CC_OP_EFLAGS; |
| ... | ... | |
| 5880 | 5885 |
case 0x1a2: /* cpuid */ |
| 5881 | 5886 |
if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_CPUID)) |
| 5882 | 5887 |
break; |
| 5883 |
gen_op_cpuid();
|
|
| 5888 |
tcg_gen_helper_0_0(helper_cpuid);
|
|
| 5884 | 5889 |
break; |
| 5885 | 5890 |
case 0xf4: /* hlt */ |
| 5886 | 5891 |
if (s->cpl != 0) {
|
| ... | ... | |
| 5891 | 5896 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 5892 | 5897 |
gen_op_set_cc_op(s->cc_op); |
| 5893 | 5898 |
gen_jmp_im(s->pc - s->cs_base); |
| 5894 |
gen_op_hlt();
|
|
| 5899 |
tcg_gen_helper_0_0(helper_hlt);
|
|
| 5895 | 5900 |
s->is_jmp = 3; |
| 5896 | 5901 |
} |
| 5897 | 5902 |
break; |
| ... | ... | |
| 5921 | 5926 |
break; |
| 5922 | 5927 |
gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
| 5923 | 5928 |
gen_jmp_im(pc_start - s->cs_base); |
| 5924 |
gen_op_lldt_T0(); |
|
| 5929 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 5930 |
tcg_gen_helper_0_1(helper_lldt, cpu_tmp2); |
|
| 5925 | 5931 |
} |
| 5926 | 5932 |
break; |
| 5927 | 5933 |
case 1: /* str */ |
| ... | ... | |
| 5945 | 5951 |
break; |
| 5946 | 5952 |
gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); |
| 5947 | 5953 |
gen_jmp_im(pc_start - s->cs_base); |
| 5948 |
gen_op_ltr_T0(); |
|
| 5954 |
tcg_gen_trunc_tl_i32(cpu_tmp2, cpu_T[0]); |
|
| 5955 |
tcg_gen_helper_0_1(helper_ltr, cpu_tmp2); |
|
| 5949 | 5956 |
} |
| 5950 | 5957 |
break; |
| 5951 | 5958 |
case 4: /* verr */ |
| ... | ... | |
| 6008 | 6015 |
gen_op_andl_A0_ffff(); |
| 6009 | 6016 |
} |
| 6010 | 6017 |
gen_add_A0_ds_seg(s); |
| 6011 |
gen_op_monitor();
|
|
| 6018 |
tcg_gen_helper_0_1(helper_monitor, cpu_A0);
|
|
| 6012 | 6019 |
break; |
| 6013 | 6020 |
case 1: /* mwait */ |
| 6014 | 6021 |
if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || |
| ... | ... | |
| 6021 | 6028 |
if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_MWAIT)) |
| 6022 | 6029 |
break; |
| 6023 | 6030 |
gen_jmp_im(s->pc - s->cs_base); |
| 6024 |
gen_op_mwait();
|
|
| 6031 |
tcg_gen_helper_0_0(helper_mwait);
|
|
| 6025 | 6032 |
gen_eob(s); |
| 6026 | 6033 |
break; |
| 6027 | 6034 |
default: |
| ... | ... | |
| 6050 | 6057 |
if (s->cc_op != CC_OP_DYNAMIC) |
| 6051 | 6058 |
gen_op_set_cc_op(s->cc_op); |
| 6052 | 6059 |
gen_jmp_im(s->pc - s->cs_base); |
| 6053 |
gen_op_vmrun();
|
|
| 6060 |
tcg_gen_helper_0_0(helper_vmrun);
|
|
| 6054 | 6061 |
s->cc_op = CC_OP_EFLAGS; |
| 6055 | 6062 |
gen_eob(s); |
| 6056 | 6063 |
break; |
| ... | ... | |
| 6058 | 6065 |
if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMMCALL)) |
| 6059 | 6066 |
break; |
| 6060 | 6067 |
/* FIXME: cause #UD if hflags & SVM */ |
| 6061 |
gen_op_vmmcall();
|
|
| 6068 |
tcg_gen_helper_0_0(helper_vmmcall);
|
|
| 6062 | 6069 |
break; |
| 6063 | 6070 |
case 2: /* VMLOAD */ |
| 6064 | 6071 |
if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMLOAD)) |
| 6065 | 6072 |
break; |
| 6066 |
gen_op_vmload();
|
|
| 6073 |
tcg_gen_helper_0_0(helper_vmload);
|
|
| 6067 | 6074 |
break; |
| 6068 | 6075 |
case 3: /* VMSAVE */ |
| 6069 | 6076 |
if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMSAVE)) |
| 6070 | 6077 |
break; |
| 6071 |
gen_op_vmsave();
|
|
| 6078 |
tcg_gen_helper_0_0(helper_vmsave);
|
|
| 6072 | 6079 |
break; |
| 6073 | 6080 |
case 4: /* STGI */ |
| 6074 | 6081 |
if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_STGI)) |
| 6075 | 6082 |
break; |
| 6076 |
gen_op_stgi();
|
|
| 6083 |
tcg_gen_helper_0_0(helper_stgi);
|
|
| 6077 | 6084 |
break; |
| 6078 | 6085 |
case 5: /* CLGI */ |
| 6079 | 6086 |
if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_CLGI)) |
| 6080 | 6087 |
break; |
| 6081 |
gen_op_clgi();
|
|
| 6088 |
tcg_gen_helper_0_0(helper_clgi);
|
|
| 6082 | 6089 |
break; |
| 6083 | 6090 |
case 6: /* SKINIT */ |
| 6084 | 6091 |
if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SKINIT)) |
| 6085 | 6092 |
break; |
| 6086 |
gen_op_skinit();
|
|
| 6093 |
tcg_gen_helper_0_0(helper_skinit);
|
|
| 6087 | 6094 |
break; |
| 6088 | 6095 |
case 7: /* INVLPGA */ |
| 6089 | 6096 |
if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_INVLPGA)) |
| 6090 | 6097 |
break; |
| 6091 |
gen_op_invlpga();
|
|
| 6098 |
tcg_gen_helper_0_0(helper_invlpga);
|
|
| 6092 | 6099 |
break; |
| 6093 | 6100 |
default: |
| 6094 | 6101 |
goto illegal_op; |
| ... | ... | |
| 6153 | 6160 |
if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_INVLPG)) |
| 6154 | 6161 |
break; |
| 6155 | 6162 |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
| 6156 |
gen_op_invlpg_A0();
|
|
| 6163 |
tcg_gen_helper_0_1(helper_invlpg, cpu_A0);
|
|
| 6157 | 6164 |
gen_jmp_im(s->pc - s->cs_base); |
| 6158 | 6165 |
gen_eob(s); |
| 6159 | 6166 |
} |
| ... | ... | |
| 6458 | 6465 |
s->cc_op = CC_OP_DYNAMIC; |
| 6459 | 6466 |
} |
| 6460 | 6467 |
gen_jmp_im(s->pc - s->cs_base); |
| 6461 |
gen_op_rsm();
|
|
| 6468 |
tcg_gen_helper_0_0(helper_rsm);
|
|
| 6462 | 6469 |
gen_eob(s); |
| 6463 | 6470 |
break; |
| 6464 | 6471 |
case 0x10e ... 0x10f: |
| ... | ... | |
| 6855 | 6862 |
cpu_A0 = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "A0"); |
| 6856 | 6863 |
cpu_tmp1 = tcg_global_reg2_new_hack(TCG_TYPE_I64, TCG_AREG1, TCG_AREG2, "tmp1"); |
| 6857 | 6864 |
#endif |
| 6858 |
/* the helpers are only registered to print debug info */ |
|
| 6859 |
TCG_HELPER(helper_divl_EAX_T0); |
|
| 6860 |
TCG_HELPER(helper_idivl_EAX_T0); |
|
| 6861 | 6865 |
} |
| 6862 | 6866 |
|
| 6863 | 6867 |
/* CPU flags computation optimization: we move backward thru the |
Also available in: Unified diff