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1 | b92e5a22 | bellard | /*
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2 | b92e5a22 | bellard | * Software MMU support
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3 | 5fafdf24 | ths | *
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4 | b92e5a22 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | b92e5a22 | bellard | *
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6 | b92e5a22 | bellard | * This library is free software; you can redistribute it and/or
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7 | b92e5a22 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | b92e5a22 | bellard | * License as published by the Free Software Foundation; either
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9 | b92e5a22 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | b92e5a22 | bellard | *
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11 | b92e5a22 | bellard | * This library is distributed in the hope that it will be useful,
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12 | b92e5a22 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | b92e5a22 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | b92e5a22 | bellard | * Lesser General Public License for more details.
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15 | b92e5a22 | bellard | *
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16 | b92e5a22 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | b92e5a22 | bellard | * License along with this library; if not, write to the Free Software
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18 | b92e5a22 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | b92e5a22 | bellard | */
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20 | b92e5a22 | bellard | #define DATA_SIZE (1 << SHIFT) |
21 | b92e5a22 | bellard | |
22 | b92e5a22 | bellard | #if DATA_SIZE == 8 |
23 | b92e5a22 | bellard | #define SUFFIX q
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24 | 61382a50 | bellard | #define USUFFIX q
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25 | b92e5a22 | bellard | #define DATA_TYPE uint64_t
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26 | b92e5a22 | bellard | #elif DATA_SIZE == 4 |
27 | b92e5a22 | bellard | #define SUFFIX l
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28 | 61382a50 | bellard | #define USUFFIX l
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29 | b92e5a22 | bellard | #define DATA_TYPE uint32_t
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30 | b92e5a22 | bellard | #elif DATA_SIZE == 2 |
31 | b92e5a22 | bellard | #define SUFFIX w
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32 | 61382a50 | bellard | #define USUFFIX uw
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33 | b92e5a22 | bellard | #define DATA_TYPE uint16_t
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34 | b92e5a22 | bellard | #elif DATA_SIZE == 1 |
35 | b92e5a22 | bellard | #define SUFFIX b
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36 | 61382a50 | bellard | #define USUFFIX ub
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37 | b92e5a22 | bellard | #define DATA_TYPE uint8_t
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38 | b92e5a22 | bellard | #else
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39 | b92e5a22 | bellard | #error unsupported data size
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40 | b92e5a22 | bellard | #endif
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41 | b92e5a22 | bellard | |
42 | b769d8fe | bellard | #ifdef SOFTMMU_CODE_ACCESS
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43 | b769d8fe | bellard | #define READ_ACCESS_TYPE 2 |
44 | 84b7b8e7 | bellard | #define ADDR_READ addr_code
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45 | b769d8fe | bellard | #else
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46 | b769d8fe | bellard | #define READ_ACCESS_TYPE 0 |
47 | 84b7b8e7 | bellard | #define ADDR_READ addr_read
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48 | b769d8fe | bellard | #endif
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49 | b769d8fe | bellard | |
50 | 5fafdf24 | ths | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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51 | 6ebbf390 | j_mayer | int mmu_idx,
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52 | 61382a50 | bellard | void *retaddr);
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53 | 5fafdf24 | ths | static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr, |
54 | 0f459d16 | pbrook | target_ulong addr) |
55 | b92e5a22 | bellard | { |
56 | b92e5a22 | bellard | DATA_TYPE res; |
57 | b92e5a22 | bellard | int index;
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58 | 0f459d16 | pbrook | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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59 | 0f459d16 | pbrook | physaddr = (physaddr & TARGET_PAGE_MASK) + addr; |
60 | b92e5a22 | bellard | |
61 | b92e5a22 | bellard | #if SHIFT <= 2 |
62 | a4193c8a | bellard | res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr); |
63 | b92e5a22 | bellard | #else
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64 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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65 | a4193c8a | bellard | res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32; |
66 | a4193c8a | bellard | res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4); |
67 | b92e5a22 | bellard | #else
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68 | a4193c8a | bellard | res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
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69 | a4193c8a | bellard | res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32; |
70 | b92e5a22 | bellard | #endif
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71 | b92e5a22 | bellard | #endif /* SHIFT > 2 */ |
72 | f1c85677 | bellard | #ifdef USE_KQEMU
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73 | f1c85677 | bellard | env->last_io_time = cpu_get_time_fast(); |
74 | f1c85677 | bellard | #endif
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75 | b92e5a22 | bellard | return res;
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76 | b92e5a22 | bellard | } |
77 | b92e5a22 | bellard | |
78 | b92e5a22 | bellard | /* handle all cases except unaligned access which span two pages */
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79 | d656469f | bellard | DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr, |
80 | d656469f | bellard | int mmu_idx)
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81 | b92e5a22 | bellard | { |
82 | b92e5a22 | bellard | DATA_TYPE res; |
83 | 61382a50 | bellard | int index;
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84 | c27004ec | bellard | target_ulong tlb_addr; |
85 | 0f459d16 | pbrook | target_phys_addr_t addend; |
86 | b92e5a22 | bellard | void *retaddr;
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87 | 3b46e624 | ths | |
88 | b92e5a22 | bellard | /* test if there is match for unaligned or IO access */
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89 | b92e5a22 | bellard | /* XXX: could done more in memory macro in a non portable way */
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90 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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91 | b92e5a22 | bellard | redo:
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92 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; |
93 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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94 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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95 | b92e5a22 | bellard | /* IO access */
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96 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
97 | b92e5a22 | bellard | goto do_unaligned_access;
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98 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
99 | 0f459d16 | pbrook | res = glue(io_read, SUFFIX)(addend, addr); |
100 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
101 | b92e5a22 | bellard | /* slow unaligned access (it spans two pages or IO) */
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102 | b92e5a22 | bellard | do_unaligned_access:
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103 | 61382a50 | bellard | retaddr = GETPC(); |
104 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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105 | 6ebbf390 | j_mayer | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
106 | a64d4718 | bellard | #endif
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107 | 5fafdf24 | ths | res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr, |
108 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
109 | b92e5a22 | bellard | } else {
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110 | a64d4718 | bellard | /* unaligned/aligned access in the same page */
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111 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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112 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) { |
113 | a64d4718 | bellard | retaddr = GETPC(); |
114 | 6ebbf390 | j_mayer | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
115 | a64d4718 | bellard | } |
116 | a64d4718 | bellard | #endif
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117 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
118 | 0f459d16 | pbrook | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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119 | b92e5a22 | bellard | } |
120 | b92e5a22 | bellard | } else {
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121 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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122 | 61382a50 | bellard | retaddr = GETPC(); |
123 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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124 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
125 | 6ebbf390 | j_mayer | do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
126 | a64d4718 | bellard | #endif
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127 | 6ebbf390 | j_mayer | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
128 | b92e5a22 | bellard | goto redo;
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129 | b92e5a22 | bellard | } |
130 | b92e5a22 | bellard | return res;
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131 | b92e5a22 | bellard | } |
132 | b92e5a22 | bellard | |
133 | b92e5a22 | bellard | /* handle all unaligned cases */
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134 | 5fafdf24 | ths | static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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135 | 6ebbf390 | j_mayer | int mmu_idx,
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136 | 61382a50 | bellard | void *retaddr)
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137 | b92e5a22 | bellard | { |
138 | b92e5a22 | bellard | DATA_TYPE res, res1, res2; |
139 | 61382a50 | bellard | int index, shift;
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140 | 0f459d16 | pbrook | target_phys_addr_t addend; |
141 | c27004ec | bellard | target_ulong tlb_addr, addr1, addr2; |
142 | b92e5a22 | bellard | |
143 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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144 | b92e5a22 | bellard | redo:
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145 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; |
146 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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147 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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148 | b92e5a22 | bellard | /* IO access */
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149 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
150 | b92e5a22 | bellard | goto do_unaligned_access;
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151 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
152 | 0f459d16 | pbrook | res = glue(io_read, SUFFIX)(addend, addr); |
153 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
154 | b92e5a22 | bellard | do_unaligned_access:
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155 | b92e5a22 | bellard | /* slow unaligned access (it spans two pages) */
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156 | b92e5a22 | bellard | addr1 = addr & ~(DATA_SIZE - 1);
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157 | b92e5a22 | bellard | addr2 = addr1 + DATA_SIZE; |
158 | 5fafdf24 | ths | res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1, |
159 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
160 | 5fafdf24 | ths | res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2, |
161 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
162 | b92e5a22 | bellard | shift = (addr & (DATA_SIZE - 1)) * 8; |
163 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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164 | b92e5a22 | bellard | res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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165 | b92e5a22 | bellard | #else
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166 | b92e5a22 | bellard | res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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167 | b92e5a22 | bellard | #endif
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168 | 6986f88c | bellard | res = (DATA_TYPE)res; |
169 | b92e5a22 | bellard | } else {
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170 | b92e5a22 | bellard | /* unaligned/aligned access in the same page */
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171 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
172 | 0f459d16 | pbrook | res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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173 | b92e5a22 | bellard | } |
174 | b92e5a22 | bellard | } else {
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175 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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176 | 6ebbf390 | j_mayer | tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr); |
177 | b92e5a22 | bellard | goto redo;
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178 | b92e5a22 | bellard | } |
179 | b92e5a22 | bellard | return res;
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180 | b92e5a22 | bellard | } |
181 | b92e5a22 | bellard | |
182 | b769d8fe | bellard | #ifndef SOFTMMU_CODE_ACCESS
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183 | b769d8fe | bellard | |
184 | 5fafdf24 | ths | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
185 | 5fafdf24 | ths | DATA_TYPE val, |
186 | 6ebbf390 | j_mayer | int mmu_idx,
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187 | b769d8fe | bellard | void *retaddr);
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188 | b769d8fe | bellard | |
189 | 5fafdf24 | ths | static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr, |
190 | b769d8fe | bellard | DATA_TYPE val, |
191 | 0f459d16 | pbrook | target_ulong addr, |
192 | b769d8fe | bellard | void *retaddr)
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193 | b769d8fe | bellard | { |
194 | b769d8fe | bellard | int index;
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195 | 0f459d16 | pbrook | index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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196 | 0f459d16 | pbrook | physaddr = (physaddr & TARGET_PAGE_MASK) + addr; |
197 | b769d8fe | bellard | |
198 | 0f459d16 | pbrook | env->mem_write_vaddr = addr; |
199 | b769d8fe | bellard | env->mem_write_pc = (unsigned long)retaddr; |
200 | b769d8fe | bellard | #if SHIFT <= 2 |
201 | b769d8fe | bellard | io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val); |
202 | b769d8fe | bellard | #else
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203 | b769d8fe | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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204 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32); |
205 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val); |
206 | b769d8fe | bellard | #else
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207 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
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208 | b769d8fe | bellard | io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32); |
209 | b769d8fe | bellard | #endif
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210 | b769d8fe | bellard | #endif /* SHIFT > 2 */ |
211 | f1c85677 | bellard | #ifdef USE_KQEMU
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212 | f1c85677 | bellard | env->last_io_time = cpu_get_time_fast(); |
213 | f1c85677 | bellard | #endif
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214 | b769d8fe | bellard | } |
215 | b92e5a22 | bellard | |
216 | d656469f | bellard | void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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217 | d656469f | bellard | DATA_TYPE val, |
218 | d656469f | bellard | int mmu_idx)
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219 | b92e5a22 | bellard | { |
220 | 0f459d16 | pbrook | target_phys_addr_t addend; |
221 | c27004ec | bellard | target_ulong tlb_addr; |
222 | b92e5a22 | bellard | void *retaddr;
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223 | 61382a50 | bellard | int index;
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224 | 3b46e624 | ths | |
225 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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226 | b92e5a22 | bellard | redo:
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227 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].addr_write; |
228 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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229 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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230 | b92e5a22 | bellard | /* IO access */
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231 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
232 | b92e5a22 | bellard | goto do_unaligned_access;
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233 | d720b93d | bellard | retaddr = GETPC(); |
234 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
235 | 0f459d16 | pbrook | glue(io_write, SUFFIX)(addend, val, addr, retaddr); |
236 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
237 | b92e5a22 | bellard | do_unaligned_access:
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238 | 61382a50 | bellard | retaddr = GETPC(); |
239 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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240 | 6ebbf390 | j_mayer | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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241 | a64d4718 | bellard | #endif
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242 | 5fafdf24 | ths | glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val, |
243 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
244 | b92e5a22 | bellard | } else {
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245 | b92e5a22 | bellard | /* aligned/unaligned access in the same page */
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246 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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247 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) { |
248 | a64d4718 | bellard | retaddr = GETPC(); |
249 | 6ebbf390 | j_mayer | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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250 | a64d4718 | bellard | } |
251 | a64d4718 | bellard | #endif
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252 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
253 | 0f459d16 | pbrook | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
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254 | b92e5a22 | bellard | } |
255 | b92e5a22 | bellard | } else {
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256 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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257 | 61382a50 | bellard | retaddr = GETPC(); |
258 | a64d4718 | bellard | #ifdef ALIGNED_ONLY
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259 | a64d4718 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
260 | 6ebbf390 | j_mayer | do_unaligned_access(addr, 1, mmu_idx, retaddr);
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261 | a64d4718 | bellard | #endif
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262 | 6ebbf390 | j_mayer | tlb_fill(addr, 1, mmu_idx, retaddr);
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263 | b92e5a22 | bellard | goto redo;
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264 | b92e5a22 | bellard | } |
265 | b92e5a22 | bellard | } |
266 | b92e5a22 | bellard | |
267 | b92e5a22 | bellard | /* handles all unaligned cases */
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268 | 5fafdf24 | ths | static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr, |
269 | 61382a50 | bellard | DATA_TYPE val, |
270 | 6ebbf390 | j_mayer | int mmu_idx,
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271 | 61382a50 | bellard | void *retaddr)
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272 | b92e5a22 | bellard | { |
273 | 0f459d16 | pbrook | target_phys_addr_t addend; |
274 | c27004ec | bellard | target_ulong tlb_addr; |
275 | 61382a50 | bellard | int index, i;
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276 | b92e5a22 | bellard | |
277 | b92e5a22 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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278 | b92e5a22 | bellard | redo:
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279 | 6ebbf390 | j_mayer | tlb_addr = env->tlb_table[mmu_idx][index].addr_write; |
280 | b92e5a22 | bellard | if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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281 | b92e5a22 | bellard | if (tlb_addr & ~TARGET_PAGE_MASK) {
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282 | b92e5a22 | bellard | /* IO access */
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283 | b92e5a22 | bellard | if ((addr & (DATA_SIZE - 1)) != 0) |
284 | b92e5a22 | bellard | goto do_unaligned_access;
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285 | 0f459d16 | pbrook | addend = env->iotlb[mmu_idx][index]; |
286 | 0f459d16 | pbrook | glue(io_write, SUFFIX)(addend, val, addr, retaddr); |
287 | 98699967 | bellard | } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { |
288 | b92e5a22 | bellard | do_unaligned_access:
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289 | b92e5a22 | bellard | /* XXX: not efficient, but simple */
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290 | 6c41b272 | balrog | /* Note: relies on the fact that tlb_fill() does not remove the
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291 | 6c41b272 | balrog | * previous page from the TLB cache. */
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292 | 7221fa98 | balrog | for(i = DATA_SIZE - 1; i >= 0; i--) { |
293 | b92e5a22 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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294 | 5fafdf24 | ths | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)), |
295 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
296 | b92e5a22 | bellard | #else
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297 | 5fafdf24 | ths | glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
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298 | 6ebbf390 | j_mayer | mmu_idx, retaddr); |
299 | b92e5a22 | bellard | #endif
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300 | b92e5a22 | bellard | } |
301 | b92e5a22 | bellard | } else {
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302 | b92e5a22 | bellard | /* aligned/unaligned access in the same page */
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303 | 0f459d16 | pbrook | addend = env->tlb_table[mmu_idx][index].addend; |
304 | 0f459d16 | pbrook | glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
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305 | b92e5a22 | bellard | } |
306 | b92e5a22 | bellard | } else {
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307 | b92e5a22 | bellard | /* the page is not in the TLB : fill it */
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308 | 6ebbf390 | j_mayer | tlb_fill(addr, 1, mmu_idx, retaddr);
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309 | b92e5a22 | bellard | goto redo;
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310 | b92e5a22 | bellard | } |
311 | b92e5a22 | bellard | } |
312 | b92e5a22 | bellard | |
313 | b769d8fe | bellard | #endif /* !defined(SOFTMMU_CODE_ACCESS) */ |
314 | b769d8fe | bellard | |
315 | b769d8fe | bellard | #undef READ_ACCESS_TYPE
|
316 | b92e5a22 | bellard | #undef SHIFT
|
317 | b92e5a22 | bellard | #undef DATA_TYPE
|
318 | b92e5a22 | bellard | #undef SUFFIX
|
319 | 61382a50 | bellard | #undef USUFFIX
|
320 | b92e5a22 | bellard | #undef DATA_SIZE
|
321 | 84b7b8e7 | bellard | #undef ADDR_READ |