Revision b6343073
| b/hw/cirrus_vga.c | ||
|---|---|---|
| 2658 | 2658 |
|
| 2659 | 2659 |
static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr) |
| 2660 | 2660 |
{
|
| 2661 |
CirrusVGAState *s = opaque; |
|
| 2661 |
CirrusVGAState *c = opaque; |
|
| 2662 |
VGACommonState *s = &c->vga; |
|
| 2662 | 2663 |
int val, index; |
| 2663 | 2664 |
|
| 2664 |
if (vga_ioport_invalid(&s->vga, addr)) {
|
|
| 2665 |
if (vga_ioport_invalid(s, addr)) {
|
|
| 2665 | 2666 |
val = 0xff; |
| 2666 | 2667 |
} else {
|
| 2667 | 2668 |
switch (addr) {
|
| 2668 | 2669 |
case 0x3c0: |
| 2669 |
if (s->vga.ar_flip_flop == 0) {
|
|
| 2670 |
val = s->vga.ar_index;
|
|
| 2670 |
if (s->ar_flip_flop == 0) {
|
|
| 2671 |
val = s->ar_index; |
|
| 2671 | 2672 |
} else {
|
| 2672 | 2673 |
val = 0; |
| 2673 | 2674 |
} |
| 2674 | 2675 |
break; |
| 2675 | 2676 |
case 0x3c1: |
| 2676 |
index = s->vga.ar_index & 0x1f;
|
|
| 2677 |
index = s->ar_index & 0x1f; |
|
| 2677 | 2678 |
if (index < 21) |
| 2678 |
val = s->vga.ar[index];
|
|
| 2679 |
val = s->ar[index]; |
|
| 2679 | 2680 |
else |
| 2680 | 2681 |
val = 0; |
| 2681 | 2682 |
break; |
| 2682 | 2683 |
case 0x3c2: |
| 2683 |
val = s->vga.st00;
|
|
| 2684 |
val = s->st00; |
|
| 2684 | 2685 |
break; |
| 2685 | 2686 |
case 0x3c4: |
| 2686 |
val = s->vga.sr_index;
|
|
| 2687 |
val = s->sr_index; |
|
| 2687 | 2688 |
break; |
| 2688 | 2689 |
case 0x3c5: |
| 2689 |
if (cirrus_hook_read_sr(s, s->vga.sr_index, &val))
|
|
| 2690 |
if (cirrus_hook_read_sr(c, s->sr_index, &val))
|
|
| 2690 | 2691 |
break; |
| 2691 |
val = s->vga.sr[s->vga.sr_index];
|
|
| 2692 |
val = s->sr[s->sr_index];
|
|
| 2692 | 2693 |
#ifdef DEBUG_VGA_REG |
| 2693 |
printf("vga: read SR%x = 0x%02x\n", s->vga.sr_index, val);
|
|
| 2694 |
printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
|
|
| 2694 | 2695 |
#endif |
| 2695 | 2696 |
break; |
| 2696 | 2697 |
case 0x3c6: |
| 2697 |
cirrus_read_hidden_dac(s, &val);
|
|
| 2698 |
cirrus_read_hidden_dac(c, &val);
|
|
| 2698 | 2699 |
break; |
| 2699 | 2700 |
case 0x3c7: |
| 2700 |
val = s->vga.dac_state;
|
|
| 2701 |
val = s->dac_state; |
|
| 2701 | 2702 |
break; |
| 2702 | 2703 |
case 0x3c8: |
| 2703 |
val = s->vga.dac_write_index;
|
|
| 2704 |
s->cirrus_hidden_dac_lockindex = 0;
|
|
| 2704 |
val = s->dac_write_index; |
|
| 2705 |
c->cirrus_hidden_dac_lockindex = 0;
|
|
| 2705 | 2706 |
break; |
| 2706 | 2707 |
case 0x3c9: |
| 2707 |
if (cirrus_hook_read_palette(s, &val))
|
|
| 2708 |
if (cirrus_hook_read_palette(c, &val))
|
|
| 2708 | 2709 |
break; |
| 2709 |
val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
|
|
| 2710 |
if (++s->vga.dac_sub_index == 3) {
|
|
| 2711 |
s->vga.dac_sub_index = 0;
|
|
| 2712 |
s->vga.dac_read_index++;
|
|
| 2710 |
val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
|
|
| 2711 |
if (++s->dac_sub_index == 3) {
|
|
| 2712 |
s->dac_sub_index = 0; |
|
| 2713 |
s->dac_read_index++; |
|
| 2713 | 2714 |
} |
| 2714 | 2715 |
break; |
| 2715 | 2716 |
case 0x3ca: |
| 2716 |
val = s->vga.fcr;
|
|
| 2717 |
val = s->fcr; |
|
| 2717 | 2718 |
break; |
| 2718 | 2719 |
case 0x3cc: |
| 2719 |
val = s->vga.msr;
|
|
| 2720 |
val = s->msr; |
|
| 2720 | 2721 |
break; |
| 2721 | 2722 |
case 0x3ce: |
| 2722 |
val = s->vga.gr_index;
|
|
| 2723 |
val = s->gr_index; |
|
| 2723 | 2724 |
break; |
| 2724 | 2725 |
case 0x3cf: |
| 2725 |
if (cirrus_hook_read_gr(s, s->vga.gr_index, &val))
|
|
| 2726 |
if (cirrus_hook_read_gr(c, s->gr_index, &val))
|
|
| 2726 | 2727 |
break; |
| 2727 |
val = s->vga.gr[s->vga.gr_index];
|
|
| 2728 |
val = s->gr[s->gr_index];
|
|
| 2728 | 2729 |
#ifdef DEBUG_VGA_REG |
| 2729 |
printf("vga: read GR%x = 0x%02x\n", s->vga.gr_index, val);
|
|
| 2730 |
printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
|
|
| 2730 | 2731 |
#endif |
| 2731 | 2732 |
break; |
| 2732 | 2733 |
case 0x3b4: |
| 2733 | 2734 |
case 0x3d4: |
| 2734 |
val = s->vga.cr_index;
|
|
| 2735 |
val = s->cr_index; |
|
| 2735 | 2736 |
break; |
| 2736 | 2737 |
case 0x3b5: |
| 2737 | 2738 |
case 0x3d5: |
| 2738 |
if (cirrus_hook_read_cr(s, s->vga.cr_index, &val))
|
|
| 2739 |
if (cirrus_hook_read_cr(c, s->cr_index, &val))
|
|
| 2739 | 2740 |
break; |
| 2740 |
val = s->vga.cr[s->vga.cr_index];
|
|
| 2741 |
val = s->cr[s->cr_index];
|
|
| 2741 | 2742 |
#ifdef DEBUG_VGA_REG |
| 2742 |
printf("vga: read CR%x = 0x%02x\n", s->vga.cr_index, val);
|
|
| 2743 |
printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
|
|
| 2743 | 2744 |
#endif |
| 2744 | 2745 |
break; |
| 2745 | 2746 |
case 0x3ba: |
| 2746 | 2747 |
case 0x3da: |
| 2747 | 2748 |
/* just toggle to fool polling */ |
| 2748 |
val = s->vga.st01 = s->vga.retrace(&s->vga);
|
|
| 2749 |
s->vga.ar_flip_flop = 0;
|
|
| 2749 |
val = s->st01 = s->retrace(s);
|
|
| 2750 |
s->ar_flip_flop = 0; |
|
| 2750 | 2751 |
break; |
| 2751 | 2752 |
default: |
| 2752 | 2753 |
val = 0x00; |
| ... | ... | |
| 2761 | 2762 |
|
| 2762 | 2763 |
static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
| 2763 | 2764 |
{
|
| 2764 |
CirrusVGAState *s = opaque; |
|
| 2765 |
CirrusVGAState *c = opaque; |
|
| 2766 |
VGACommonState *s = &c->vga; |
|
| 2765 | 2767 |
int index; |
| 2766 | 2768 |
|
| 2767 | 2769 |
/* check port range access depending on color/monochrome mode */ |
| 2768 |
if (vga_ioport_invalid(&s->vga, addr)) {
|
|
| 2770 |
if (vga_ioport_invalid(s, addr)) {
|
|
| 2769 | 2771 |
return; |
| 2770 | 2772 |
} |
| 2771 | 2773 |
#ifdef DEBUG_VGA |
| ... | ... | |
| 2774 | 2776 |
|
| 2775 | 2777 |
switch (addr) {
|
| 2776 | 2778 |
case 0x3c0: |
| 2777 |
if (s->vga.ar_flip_flop == 0) {
|
|
| 2779 |
if (s->ar_flip_flop == 0) {
|
|
| 2778 | 2780 |
val &= 0x3f; |
| 2779 |
s->vga.ar_index = val;
|
|
| 2781 |
s->ar_index = val; |
|
| 2780 | 2782 |
} else {
|
| 2781 |
index = s->vga.ar_index & 0x1f;
|
|
| 2783 |
index = s->ar_index & 0x1f; |
|
| 2782 | 2784 |
switch (index) {
|
| 2783 | 2785 |
case 0x00 ... 0x0f: |
| 2784 |
s->vga.ar[index] = val & 0x3f;
|
|
| 2786 |
s->ar[index] = val & 0x3f; |
|
| 2785 | 2787 |
break; |
| 2786 | 2788 |
case 0x10: |
| 2787 |
s->vga.ar[index] = val & ~0x10;
|
|
| 2789 |
s->ar[index] = val & ~0x10; |
|
| 2788 | 2790 |
break; |
| 2789 | 2791 |
case 0x11: |
| 2790 |
s->vga.ar[index] = val;
|
|
| 2792 |
s->ar[index] = val; |
|
| 2791 | 2793 |
break; |
| 2792 | 2794 |
case 0x12: |
| 2793 |
s->vga.ar[index] = val & ~0xc0;
|
|
| 2795 |
s->ar[index] = val & ~0xc0; |
|
| 2794 | 2796 |
break; |
| 2795 | 2797 |
case 0x13: |
| 2796 |
s->vga.ar[index] = val & ~0xf0;
|
|
| 2798 |
s->ar[index] = val & ~0xf0; |
|
| 2797 | 2799 |
break; |
| 2798 | 2800 |
case 0x14: |
| 2799 |
s->vga.ar[index] = val & ~0xf0;
|
|
| 2801 |
s->ar[index] = val & ~0xf0; |
|
| 2800 | 2802 |
break; |
| 2801 | 2803 |
default: |
| 2802 | 2804 |
break; |
| 2803 | 2805 |
} |
| 2804 | 2806 |
} |
| 2805 |
s->vga.ar_flip_flop ^= 1;
|
|
| 2807 |
s->ar_flip_flop ^= 1; |
|
| 2806 | 2808 |
break; |
| 2807 | 2809 |
case 0x3c2: |
| 2808 |
s->vga.msr = val & ~0x10;
|
|
| 2809 |
s->vga.update_retrace_info(&s->vga);
|
|
| 2810 |
s->msr = val & ~0x10; |
|
| 2811 |
s->update_retrace_info(s);
|
|
| 2810 | 2812 |
break; |
| 2811 | 2813 |
case 0x3c4: |
| 2812 |
s->vga.sr_index = val;
|
|
| 2814 |
s->sr_index = val; |
|
| 2813 | 2815 |
break; |
| 2814 | 2816 |
case 0x3c5: |
| 2815 |
if (cirrus_hook_write_sr(s, s->vga.sr_index, val))
|
|
| 2817 |
if (cirrus_hook_write_sr(c, s->sr_index, val))
|
|
| 2816 | 2818 |
break; |
| 2817 | 2819 |
#ifdef DEBUG_VGA_REG |
| 2818 |
printf("vga: write SR%x = 0x%02x\n", s->vga.sr_index, val);
|
|
| 2820 |
printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
|
|
| 2819 | 2821 |
#endif |
| 2820 |
s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
|
|
| 2821 |
if (s->vga.sr_index == 1) s->vga.update_retrace_info(&s->vga);
|
|
| 2822 |
s->sr[s->sr_index] = val & sr_mask[s->sr_index];
|
|
| 2823 |
if (s->sr_index == 1) s->update_retrace_info(s);
|
|
| 2822 | 2824 |
break; |
| 2823 | 2825 |
case 0x3c6: |
| 2824 |
cirrus_write_hidden_dac(s, val);
|
|
| 2826 |
cirrus_write_hidden_dac(c, val);
|
|
| 2825 | 2827 |
break; |
| 2826 | 2828 |
case 0x3c7: |
| 2827 |
s->vga.dac_read_index = val;
|
|
| 2828 |
s->vga.dac_sub_index = 0;
|
|
| 2829 |
s->vga.dac_state = 3;
|
|
| 2829 |
s->dac_read_index = val; |
|
| 2830 |
s->dac_sub_index = 0; |
|
| 2831 |
s->dac_state = 3; |
|
| 2830 | 2832 |
break; |
| 2831 | 2833 |
case 0x3c8: |
| 2832 |
s->vga.dac_write_index = val;
|
|
| 2833 |
s->vga.dac_sub_index = 0;
|
|
| 2834 |
s->vga.dac_state = 0;
|
|
| 2834 |
s->dac_write_index = val; |
|
| 2835 |
s->dac_sub_index = 0; |
|
| 2836 |
s->dac_state = 0; |
|
| 2835 | 2837 |
break; |
| 2836 | 2838 |
case 0x3c9: |
| 2837 |
if (cirrus_hook_write_palette(s, val))
|
|
| 2839 |
if (cirrus_hook_write_palette(c, val))
|
|
| 2838 | 2840 |
break; |
| 2839 |
s->vga.dac_cache[s->vga.dac_sub_index] = val;
|
|
| 2840 |
if (++s->vga.dac_sub_index == 3) {
|
|
| 2841 |
memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
|
|
| 2842 |
s->vga.dac_sub_index = 0;
|
|
| 2843 |
s->vga.dac_write_index++;
|
|
| 2841 |
s->dac_cache[s->dac_sub_index] = val;
|
|
| 2842 |
if (++s->dac_sub_index == 3) {
|
|
| 2843 |
memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
|
|
| 2844 |
s->dac_sub_index = 0; |
|
| 2845 |
s->dac_write_index++; |
|
| 2844 | 2846 |
} |
| 2845 | 2847 |
break; |
| 2846 | 2848 |
case 0x3ce: |
| 2847 |
s->vga.gr_index = val;
|
|
| 2849 |
s->gr_index = val; |
|
| 2848 | 2850 |
break; |
| 2849 | 2851 |
case 0x3cf: |
| 2850 |
if (cirrus_hook_write_gr(s, s->vga.gr_index, val))
|
|
| 2852 |
if (cirrus_hook_write_gr(c, s->gr_index, val))
|
|
| 2851 | 2853 |
break; |
| 2852 | 2854 |
#ifdef DEBUG_VGA_REG |
| 2853 |
printf("vga: write GR%x = 0x%02x\n", s->vga.gr_index, val);
|
|
| 2855 |
printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
|
|
| 2854 | 2856 |
#endif |
| 2855 |
s->vga.gr[s->vga.gr_index] = val & gr_mask[s->vga.gr_index];
|
|
| 2857 |
s->gr[s->gr_index] = val & gr_mask[s->gr_index];
|
|
| 2856 | 2858 |
break; |
| 2857 | 2859 |
case 0x3b4: |
| 2858 | 2860 |
case 0x3d4: |
| 2859 |
s->vga.cr_index = val;
|
|
| 2861 |
s->cr_index = val; |
|
| 2860 | 2862 |
break; |
| 2861 | 2863 |
case 0x3b5: |
| 2862 | 2864 |
case 0x3d5: |
| 2863 |
if (cirrus_hook_write_cr(s, s->vga.cr_index, val))
|
|
| 2865 |
if (cirrus_hook_write_cr(c, s->cr_index, val))
|
|
| 2864 | 2866 |
break; |
| 2865 | 2867 |
#ifdef DEBUG_VGA_REG |
| 2866 |
printf("vga: write CR%x = 0x%02x\n", s->vga.cr_index, val);
|
|
| 2868 |
printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
|
|
| 2867 | 2869 |
#endif |
| 2868 | 2870 |
/* handle CR0-7 protection */ |
| 2869 |
if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
|
|
| 2871 |
if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
|
|
| 2870 | 2872 |
/* can always write bit 4 of CR7 */ |
| 2871 |
if (s->vga.cr_index == 7)
|
|
| 2872 |
s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (val & 0x10);
|
|
| 2873 |
if (s->cr_index == 7) |
|
| 2874 |
s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
|
|
| 2873 | 2875 |
return; |
| 2874 | 2876 |
} |
| 2875 |
switch (s->vga.cr_index) {
|
|
| 2877 |
switch (s->cr_index) {
|
|
| 2876 | 2878 |
case 0x01: /* horizontal display end */ |
| 2877 | 2879 |
case 0x07: |
| 2878 | 2880 |
case 0x09: |
| 2879 | 2881 |
case 0x0c: |
| 2880 | 2882 |
case 0x0d: |
| 2881 | 2883 |
case 0x12: /* vertical display end */ |
| 2882 |
s->vga.cr[s->vga.cr_index] = val;
|
|
| 2884 |
s->cr[s->cr_index] = val;
|
|
| 2883 | 2885 |
break; |
| 2884 | 2886 |
|
| 2885 | 2887 |
default: |
| 2886 |
s->vga.cr[s->vga.cr_index] = val;
|
|
| 2888 |
s->cr[s->cr_index] = val;
|
|
| 2887 | 2889 |
break; |
| 2888 | 2890 |
} |
| 2889 | 2891 |
|
| 2890 |
switch(s->vga.cr_index) {
|
|
| 2892 |
switch(s->cr_index) {
|
|
| 2891 | 2893 |
case 0x00: |
| 2892 | 2894 |
case 0x04: |
| 2893 | 2895 |
case 0x05: |
| ... | ... | |
| 2895 | 2897 |
case 0x07: |
| 2896 | 2898 |
case 0x11: |
| 2897 | 2899 |
case 0x17: |
| 2898 |
s->vga.update_retrace_info(&s->vga);
|
|
| 2900 |
s->update_retrace_info(s);
|
|
| 2899 | 2901 |
break; |
| 2900 | 2902 |
} |
| 2901 | 2903 |
break; |
| 2902 | 2904 |
case 0x3ba: |
| 2903 | 2905 |
case 0x3da: |
| 2904 |
s->vga.fcr = val & 0x10;
|
|
| 2906 |
s->fcr = val & 0x10; |
|
| 2905 | 2907 |
break; |
| 2906 | 2908 |
} |
| 2907 | 2909 |
} |
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