root / hw / mc146818rtc.c @ b651fc6f
History | View | Annotate | Download (19.5 kB)
1 |
/*
|
---|---|
2 |
* QEMU MC146818 RTC emulation
|
3 |
*
|
4 |
* Copyright (c) 2003-2004 Fabrice Bellard
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to deal
|
8 |
* in the Software without restriction, including without limitation the rights
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 |
* copies of the Software, and to permit persons to whom the Software is
|
11 |
* furnished to do so, subject to the following conditions:
|
12 |
*
|
13 |
* The above copyright notice and this permission notice shall be included in
|
14 |
* all copies or substantial portions of the Software.
|
15 |
*
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 |
* THE SOFTWARE.
|
23 |
*/
|
24 |
#include "hw.h" |
25 |
#include "qemu-timer.h" |
26 |
#include "sysemu.h" |
27 |
#include "pc.h" |
28 |
#include "apic.h" |
29 |
#include "isa.h" |
30 |
#include "mc146818rtc.h" |
31 |
|
32 |
//#define DEBUG_CMOS
|
33 |
//#define DEBUG_COALESCED
|
34 |
|
35 |
#ifdef DEBUG_CMOS
|
36 |
# define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
37 |
#else
|
38 |
# define CMOS_DPRINTF(format, ...) do { } while (0) |
39 |
#endif
|
40 |
|
41 |
#ifdef DEBUG_COALESCED
|
42 |
# define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__) |
43 |
#else
|
44 |
# define DPRINTF_C(format, ...) do { } while (0) |
45 |
#endif
|
46 |
|
47 |
#define RTC_REINJECT_ON_ACK_COUNT 20 |
48 |
|
49 |
#define RTC_SECONDS 0 |
50 |
#define RTC_SECONDS_ALARM 1 |
51 |
#define RTC_MINUTES 2 |
52 |
#define RTC_MINUTES_ALARM 3 |
53 |
#define RTC_HOURS 4 |
54 |
#define RTC_HOURS_ALARM 5 |
55 |
#define RTC_ALARM_DONT_CARE 0xC0 |
56 |
|
57 |
#define RTC_DAY_OF_WEEK 6 |
58 |
#define RTC_DAY_OF_MONTH 7 |
59 |
#define RTC_MONTH 8 |
60 |
#define RTC_YEAR 9 |
61 |
|
62 |
#define RTC_REG_A 10 |
63 |
#define RTC_REG_B 11 |
64 |
#define RTC_REG_C 12 |
65 |
#define RTC_REG_D 13 |
66 |
|
67 |
#define REG_A_UIP 0x80 |
68 |
|
69 |
#define REG_B_SET 0x80 |
70 |
#define REG_B_PIE 0x40 |
71 |
#define REG_B_AIE 0x20 |
72 |
#define REG_B_UIE 0x10 |
73 |
#define REG_B_SQWE 0x08 |
74 |
#define REG_B_DM 0x04 |
75 |
#define REG_B_24H 0x02 |
76 |
|
77 |
#define REG_C_UF 0x10 |
78 |
#define REG_C_IRQF 0x80 |
79 |
#define REG_C_PF 0x40 |
80 |
#define REG_C_AF 0x20 |
81 |
|
82 |
typedef struct RTCState { |
83 |
ISADevice dev; |
84 |
uint8_t cmos_data[128];
|
85 |
uint8_t cmos_index; |
86 |
struct tm current_tm;
|
87 |
int32_t base_year; |
88 |
qemu_irq irq; |
89 |
qemu_irq sqw_irq; |
90 |
int it_shift;
|
91 |
/* periodic timer */
|
92 |
QEMUTimer *periodic_timer; |
93 |
int64_t next_periodic_time; |
94 |
/* second update */
|
95 |
int64_t next_second_time; |
96 |
uint16_t irq_reinject_on_ack_count; |
97 |
uint32_t irq_coalesced; |
98 |
uint32_t period; |
99 |
QEMUTimer *coalesced_timer; |
100 |
QEMUTimer *second_timer; |
101 |
QEMUTimer *second_timer2; |
102 |
} RTCState; |
103 |
|
104 |
static void rtc_set_time(RTCState *s); |
105 |
static void rtc_copy_date(RTCState *s); |
106 |
|
107 |
#ifdef TARGET_I386
|
108 |
static void rtc_coalesced_timer_update(RTCState *s) |
109 |
{ |
110 |
if (s->irq_coalesced == 0) { |
111 |
qemu_del_timer(s->coalesced_timer); |
112 |
} else {
|
113 |
/* divide each RTC interval to 2 - 8 smaller intervals */
|
114 |
int c = MIN(s->irq_coalesced, 7) + 1; |
115 |
int64_t next_clock = qemu_get_clock(rtc_clock) + |
116 |
muldiv64(s->period / c, get_ticks_per_sec(), 32768);
|
117 |
qemu_mod_timer(s->coalesced_timer, next_clock); |
118 |
} |
119 |
} |
120 |
|
121 |
static void rtc_coalesced_timer(void *opaque) |
122 |
{ |
123 |
RTCState *s = opaque; |
124 |
|
125 |
if (s->irq_coalesced != 0) { |
126 |
apic_reset_irq_delivered(); |
127 |
s->cmos_data[RTC_REG_C] |= 0xc0;
|
128 |
DPRINTF_C("cmos: injecting from timer\n");
|
129 |
qemu_irq_raise(s->irq); |
130 |
if (apic_get_irq_delivered()) {
|
131 |
s->irq_coalesced--; |
132 |
DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
|
133 |
s->irq_coalesced); |
134 |
} |
135 |
} |
136 |
|
137 |
rtc_coalesced_timer_update(s); |
138 |
} |
139 |
#endif
|
140 |
|
141 |
static void rtc_timer_update(RTCState *s, int64_t current_time) |
142 |
{ |
143 |
int period_code, period;
|
144 |
int64_t cur_clock, next_irq_clock; |
145 |
|
146 |
period_code = s->cmos_data[RTC_REG_A] & 0x0f;
|
147 |
if (period_code != 0 |
148 |
&& ((s->cmos_data[RTC_REG_B] & REG_B_PIE) |
149 |
|| ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { |
150 |
if (period_code <= 2) |
151 |
period_code += 7;
|
152 |
/* period in 32 Khz cycles */
|
153 |
period = 1 << (period_code - 1); |
154 |
#ifdef TARGET_I386
|
155 |
if (period != s->period) {
|
156 |
s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
157 |
DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
|
158 |
} |
159 |
s->period = period; |
160 |
#endif
|
161 |
/* compute 32 khz clock */
|
162 |
cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
|
163 |
next_irq_clock = (cur_clock & ~(period - 1)) + period;
|
164 |
s->next_periodic_time = |
165 |
muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1; |
166 |
qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
167 |
} else {
|
168 |
#ifdef TARGET_I386
|
169 |
s->irq_coalesced = 0;
|
170 |
#endif
|
171 |
qemu_del_timer(s->periodic_timer); |
172 |
} |
173 |
} |
174 |
|
175 |
static void rtc_periodic_timer(void *opaque) |
176 |
{ |
177 |
RTCState *s = opaque; |
178 |
|
179 |
rtc_timer_update(s, s->next_periodic_time); |
180 |
if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
|
181 |
s->cmos_data[RTC_REG_C] |= 0xc0;
|
182 |
#ifdef TARGET_I386
|
183 |
if(rtc_td_hack) {
|
184 |
if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
|
185 |
s->irq_reinject_on_ack_count = 0;
|
186 |
apic_reset_irq_delivered(); |
187 |
qemu_irq_raise(s->irq); |
188 |
if (!apic_get_irq_delivered()) {
|
189 |
s->irq_coalesced++; |
190 |
rtc_coalesced_timer_update(s); |
191 |
DPRINTF_C("cmos: coalesced irqs increased to %d\n",
|
192 |
s->irq_coalesced); |
193 |
} |
194 |
} else
|
195 |
#endif
|
196 |
qemu_irq_raise(s->irq); |
197 |
} |
198 |
if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
|
199 |
/* Not square wave at all but we don't want 2048Hz interrupts!
|
200 |
Must be seen as a pulse. */
|
201 |
qemu_irq_raise(s->sqw_irq); |
202 |
} |
203 |
} |
204 |
|
205 |
static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
206 |
{ |
207 |
RTCState *s = opaque; |
208 |
|
209 |
if ((addr & 1) == 0) { |
210 |
s->cmos_index = data & 0x7f;
|
211 |
} else {
|
212 |
CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
|
213 |
s->cmos_index, data); |
214 |
switch(s->cmos_index) {
|
215 |
case RTC_SECONDS_ALARM:
|
216 |
case RTC_MINUTES_ALARM:
|
217 |
case RTC_HOURS_ALARM:
|
218 |
s->cmos_data[s->cmos_index] = data; |
219 |
break;
|
220 |
case RTC_SECONDS:
|
221 |
case RTC_MINUTES:
|
222 |
case RTC_HOURS:
|
223 |
case RTC_DAY_OF_WEEK:
|
224 |
case RTC_DAY_OF_MONTH:
|
225 |
case RTC_MONTH:
|
226 |
case RTC_YEAR:
|
227 |
s->cmos_data[s->cmos_index] = data; |
228 |
/* if in set mode, do not update the time */
|
229 |
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
230 |
rtc_set_time(s); |
231 |
} |
232 |
break;
|
233 |
case RTC_REG_A:
|
234 |
/* UIP bit is read only */
|
235 |
s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
236 |
(s->cmos_data[RTC_REG_A] & REG_A_UIP); |
237 |
rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
238 |
break;
|
239 |
case RTC_REG_B:
|
240 |
if (data & REG_B_SET) {
|
241 |
/* set mode: reset UIP mode */
|
242 |
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
243 |
data &= ~REG_B_UIE; |
244 |
} else {
|
245 |
/* if disabling set mode, update the time */
|
246 |
if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
|
247 |
rtc_set_time(s); |
248 |
} |
249 |
} |
250 |
if (((s->cmos_data[RTC_REG_B] ^ data) & (REG_B_DM | REG_B_24H)) &&
|
251 |
!(data & REG_B_SET)) { |
252 |
/* If the time format has changed and not in set mode,
|
253 |
update the registers immediately. */
|
254 |
s->cmos_data[RTC_REG_B] = data; |
255 |
rtc_copy_date(s); |
256 |
} else {
|
257 |
s->cmos_data[RTC_REG_B] = data; |
258 |
} |
259 |
rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
260 |
break;
|
261 |
case RTC_REG_C:
|
262 |
case RTC_REG_D:
|
263 |
/* cannot write to them */
|
264 |
break;
|
265 |
default:
|
266 |
s->cmos_data[s->cmos_index] = data; |
267 |
break;
|
268 |
} |
269 |
} |
270 |
} |
271 |
|
272 |
static inline int rtc_to_bcd(RTCState *s, int a) |
273 |
{ |
274 |
if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
|
275 |
return a;
|
276 |
} else {
|
277 |
return ((a / 10) << 4) | (a % 10); |
278 |
} |
279 |
} |
280 |
|
281 |
static inline int rtc_from_bcd(RTCState *s, int a) |
282 |
{ |
283 |
if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
|
284 |
return a;
|
285 |
} else {
|
286 |
return ((a >> 4) * 10) + (a & 0x0f); |
287 |
} |
288 |
} |
289 |
|
290 |
static void rtc_set_time(RTCState *s) |
291 |
{ |
292 |
struct tm *tm = &s->current_tm;
|
293 |
|
294 |
tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
295 |
tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); |
296 |
tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
|
297 |
if (!(s->cmos_data[RTC_REG_B] & REG_B_24H) &&
|
298 |
(s->cmos_data[RTC_HOURS] & 0x80)) {
|
299 |
tm->tm_hour += 12;
|
300 |
} |
301 |
tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
|
302 |
tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
303 |
tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
|
304 |
tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
|
305 |
|
306 |
rtc_change_mon_event(tm); |
307 |
} |
308 |
|
309 |
static void rtc_copy_date(RTCState *s) |
310 |
{ |
311 |
const struct tm *tm = &s->current_tm; |
312 |
int year;
|
313 |
|
314 |
s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
315 |
s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); |
316 |
if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
|
317 |
/* 24 hour format */
|
318 |
s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
319 |
} else {
|
320 |
/* 12 hour format */
|
321 |
s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
|
322 |
if (tm->tm_hour >= 12) |
323 |
s->cmos_data[RTC_HOURS] |= 0x80;
|
324 |
} |
325 |
s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
|
326 |
s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); |
327 |
s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
|
328 |
year = (tm->tm_year - s->base_year) % 100;
|
329 |
if (year < 0) |
330 |
year += 100;
|
331 |
s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year); |
332 |
} |
333 |
|
334 |
/* month is between 0 and 11. */
|
335 |
static int get_days_in_month(int month, int year) |
336 |
{ |
337 |
static const int days_tab[12] = { |
338 |
31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
339 |
}; |
340 |
int d;
|
341 |
if ((unsigned )month >= 12) |
342 |
return 31; |
343 |
d = days_tab[month]; |
344 |
if (month == 1) { |
345 |
if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
346 |
d++; |
347 |
} |
348 |
return d;
|
349 |
} |
350 |
|
351 |
/* update 'tm' to the next second */
|
352 |
static void rtc_next_second(struct tm *tm) |
353 |
{ |
354 |
int days_in_month;
|
355 |
|
356 |
tm->tm_sec++; |
357 |
if ((unsigned)tm->tm_sec >= 60) { |
358 |
tm->tm_sec = 0;
|
359 |
tm->tm_min++; |
360 |
if ((unsigned)tm->tm_min >= 60) { |
361 |
tm->tm_min = 0;
|
362 |
tm->tm_hour++; |
363 |
if ((unsigned)tm->tm_hour >= 24) { |
364 |
tm->tm_hour = 0;
|
365 |
/* next day */
|
366 |
tm->tm_wday++; |
367 |
if ((unsigned)tm->tm_wday >= 7) |
368 |
tm->tm_wday = 0;
|
369 |
days_in_month = get_days_in_month(tm->tm_mon, |
370 |
tm->tm_year + 1900);
|
371 |
tm->tm_mday++; |
372 |
if (tm->tm_mday < 1) { |
373 |
tm->tm_mday = 1;
|
374 |
} else if (tm->tm_mday > days_in_month) { |
375 |
tm->tm_mday = 1;
|
376 |
tm->tm_mon++; |
377 |
if (tm->tm_mon >= 12) { |
378 |
tm->tm_mon = 0;
|
379 |
tm->tm_year++; |
380 |
} |
381 |
} |
382 |
} |
383 |
} |
384 |
} |
385 |
} |
386 |
|
387 |
|
388 |
static void rtc_update_second(void *opaque) |
389 |
{ |
390 |
RTCState *s = opaque; |
391 |
int64_t delay; |
392 |
|
393 |
/* if the oscillator is not in normal operation, we do not update */
|
394 |
if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
395 |
s->next_second_time += get_ticks_per_sec(); |
396 |
qemu_mod_timer(s->second_timer, s->next_second_time); |
397 |
} else {
|
398 |
rtc_next_second(&s->current_tm); |
399 |
|
400 |
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
401 |
/* update in progress bit */
|
402 |
s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
403 |
} |
404 |
/* should be 244 us = 8 / 32768 seconds, but currently the
|
405 |
timers do not have the necessary resolution. */
|
406 |
delay = (get_ticks_per_sec() * 1) / 100; |
407 |
if (delay < 1) |
408 |
delay = 1;
|
409 |
qemu_mod_timer(s->second_timer2, |
410 |
s->next_second_time + delay); |
411 |
} |
412 |
} |
413 |
|
414 |
static void rtc_update_second2(void *opaque) |
415 |
{ |
416 |
RTCState *s = opaque; |
417 |
|
418 |
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
419 |
rtc_copy_date(s); |
420 |
} |
421 |
|
422 |
/* check alarm */
|
423 |
if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
424 |
if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
425 |
rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]) == s->current_tm.tm_sec) && |
426 |
((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
427 |
rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]) == s->current_tm.tm_min) && |
428 |
((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
429 |
rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]) == s->current_tm.tm_hour)) { |
430 |
|
431 |
s->cmos_data[RTC_REG_C] |= 0xa0;
|
432 |
qemu_irq_raise(s->irq); |
433 |
} |
434 |
} |
435 |
|
436 |
/* update ended interrupt */
|
437 |
s->cmos_data[RTC_REG_C] |= REG_C_UF; |
438 |
if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
|
439 |
s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
440 |
qemu_irq_raise(s->irq); |
441 |
} |
442 |
|
443 |
/* clear update in progress bit */
|
444 |
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
445 |
|
446 |
s->next_second_time += get_ticks_per_sec(); |
447 |
qemu_mod_timer(s->second_timer, s->next_second_time); |
448 |
} |
449 |
|
450 |
static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
451 |
{ |
452 |
RTCState *s = opaque; |
453 |
int ret;
|
454 |
if ((addr & 1) == 0) { |
455 |
return 0xff; |
456 |
} else {
|
457 |
switch(s->cmos_index) {
|
458 |
case RTC_SECONDS:
|
459 |
case RTC_MINUTES:
|
460 |
case RTC_HOURS:
|
461 |
case RTC_DAY_OF_WEEK:
|
462 |
case RTC_DAY_OF_MONTH:
|
463 |
case RTC_MONTH:
|
464 |
case RTC_YEAR:
|
465 |
ret = s->cmos_data[s->cmos_index]; |
466 |
break;
|
467 |
case RTC_REG_A:
|
468 |
ret = s->cmos_data[s->cmos_index]; |
469 |
break;
|
470 |
case RTC_REG_C:
|
471 |
ret = s->cmos_data[s->cmos_index]; |
472 |
qemu_irq_lower(s->irq); |
473 |
#ifdef TARGET_I386
|
474 |
if(s->irq_coalesced &&
|
475 |
s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
476 |
s->irq_reinject_on_ack_count++; |
477 |
apic_reset_irq_delivered(); |
478 |
DPRINTF_C("cmos: injecting on ack\n");
|
479 |
qemu_irq_raise(s->irq); |
480 |
if (apic_get_irq_delivered()) {
|
481 |
s->irq_coalesced--; |
482 |
DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
|
483 |
s->irq_coalesced); |
484 |
} |
485 |
break;
|
486 |
} |
487 |
#endif
|
488 |
|
489 |
s->cmos_data[RTC_REG_C] = 0x00;
|
490 |
break;
|
491 |
default:
|
492 |
ret = s->cmos_data[s->cmos_index]; |
493 |
break;
|
494 |
} |
495 |
CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
|
496 |
s->cmos_index, ret); |
497 |
return ret;
|
498 |
} |
499 |
} |
500 |
|
501 |
void rtc_set_memory(ISADevice *dev, int addr, int val) |
502 |
{ |
503 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
504 |
if (addr >= 0 && addr <= 127) |
505 |
s->cmos_data[addr] = val; |
506 |
} |
507 |
|
508 |
void rtc_set_date(ISADevice *dev, const struct tm *tm) |
509 |
{ |
510 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
511 |
s->current_tm = *tm; |
512 |
rtc_copy_date(s); |
513 |
} |
514 |
|
515 |
/* PC cmos mappings */
|
516 |
#define REG_IBM_CENTURY_BYTE 0x32 |
517 |
#define REG_IBM_PS2_CENTURY_BYTE 0x37 |
518 |
|
519 |
static void rtc_set_date_from_host(ISADevice *dev) |
520 |
{ |
521 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
522 |
struct tm tm;
|
523 |
int val;
|
524 |
|
525 |
/* set the CMOS date */
|
526 |
qemu_get_timedate(&tm, 0);
|
527 |
rtc_set_date(dev, &tm); |
528 |
|
529 |
val = rtc_to_bcd(s, (tm.tm_year / 100) + 19); |
530 |
rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val); |
531 |
rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val); |
532 |
} |
533 |
|
534 |
static int rtc_post_load(void *opaque, int version_id) |
535 |
{ |
536 |
#ifdef TARGET_I386
|
537 |
RTCState *s = opaque; |
538 |
|
539 |
if (version_id >= 2) { |
540 |
if (rtc_td_hack) {
|
541 |
rtc_coalesced_timer_update(s); |
542 |
} |
543 |
} |
544 |
#endif
|
545 |
return 0; |
546 |
} |
547 |
|
548 |
static const VMStateDescription vmstate_rtc = { |
549 |
.name = "mc146818rtc",
|
550 |
.version_id = 2,
|
551 |
.minimum_version_id = 1,
|
552 |
.minimum_version_id_old = 1,
|
553 |
.post_load = rtc_post_load, |
554 |
.fields = (VMStateField []) { |
555 |
VMSTATE_BUFFER(cmos_data, RTCState), |
556 |
VMSTATE_UINT8(cmos_index, RTCState), |
557 |
VMSTATE_INT32(current_tm.tm_sec, RTCState), |
558 |
VMSTATE_INT32(current_tm.tm_min, RTCState), |
559 |
VMSTATE_INT32(current_tm.tm_hour, RTCState), |
560 |
VMSTATE_INT32(current_tm.tm_wday, RTCState), |
561 |
VMSTATE_INT32(current_tm.tm_mday, RTCState), |
562 |
VMSTATE_INT32(current_tm.tm_mon, RTCState), |
563 |
VMSTATE_INT32(current_tm.tm_year, RTCState), |
564 |
VMSTATE_TIMER(periodic_timer, RTCState), |
565 |
VMSTATE_INT64(next_periodic_time, RTCState), |
566 |
VMSTATE_INT64(next_second_time, RTCState), |
567 |
VMSTATE_TIMER(second_timer, RTCState), |
568 |
VMSTATE_TIMER(second_timer2, RTCState), |
569 |
VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
570 |
VMSTATE_UINT32_V(period, RTCState, 2),
|
571 |
VMSTATE_END_OF_LIST() |
572 |
} |
573 |
}; |
574 |
|
575 |
static void rtc_reset(void *opaque) |
576 |
{ |
577 |
RTCState *s = opaque; |
578 |
|
579 |
s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
580 |
s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); |
581 |
|
582 |
qemu_irq_lower(s->irq); |
583 |
|
584 |
#ifdef TARGET_I386
|
585 |
if (rtc_td_hack)
|
586 |
s->irq_coalesced = 0;
|
587 |
#endif
|
588 |
} |
589 |
|
590 |
static int rtc_initfn(ISADevice *dev) |
591 |
{ |
592 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
593 |
int base = 0x70; |
594 |
|
595 |
s->cmos_data[RTC_REG_A] = 0x26;
|
596 |
s->cmos_data[RTC_REG_B] = 0x02;
|
597 |
s->cmos_data[RTC_REG_C] = 0x00;
|
598 |
s->cmos_data[RTC_REG_D] = 0x80;
|
599 |
|
600 |
rtc_set_date_from_host(dev); |
601 |
|
602 |
s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s); |
603 |
#ifdef TARGET_I386
|
604 |
if (rtc_td_hack)
|
605 |
s->coalesced_timer = |
606 |
qemu_new_timer(rtc_clock, rtc_coalesced_timer, s); |
607 |
#endif
|
608 |
s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s); |
609 |
s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s); |
610 |
|
611 |
s->next_second_time = |
612 |
qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100; |
613 |
qemu_mod_timer(s->second_timer2, s->next_second_time); |
614 |
|
615 |
register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
616 |
register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
617 |
isa_init_ioport_range(dev, base, 2);
|
618 |
|
619 |
qdev_set_legacy_instance_id(&dev->qdev, base, 2);
|
620 |
qemu_register_reset(rtc_reset, s); |
621 |
return 0; |
622 |
} |
623 |
|
624 |
ISADevice *rtc_init(int base_year, qemu_irq intercept_irq)
|
625 |
{ |
626 |
ISADevice *dev; |
627 |
RTCState *s; |
628 |
|
629 |
dev = isa_create("mc146818rtc");
|
630 |
s = DO_UPCAST(RTCState, dev, dev); |
631 |
qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
632 |
qdev_init_nofail(&dev->qdev); |
633 |
if (intercept_irq) {
|
634 |
s->irq = intercept_irq; |
635 |
} else {
|
636 |
isa_init_irq(dev, &s->irq, RTC_ISA_IRQ); |
637 |
} |
638 |
return dev;
|
639 |
} |
640 |
|
641 |
static ISADeviceInfo mc146818rtc_info = {
|
642 |
.qdev.name = "mc146818rtc",
|
643 |
.qdev.size = sizeof(RTCState),
|
644 |
.qdev.no_user = 1,
|
645 |
.qdev.vmsd = &vmstate_rtc, |
646 |
.init = rtc_initfn, |
647 |
.qdev.props = (Property[]) { |
648 |
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), |
649 |
DEFINE_PROP_END_OF_LIST(), |
650 |
} |
651 |
}; |
652 |
|
653 |
static void mc146818rtc_register(void) |
654 |
{ |
655 |
isa_qdev_register(&mc146818rtc_info); |
656 |
} |
657 |
device_init(mc146818rtc_register) |