root / op_string.h @ b67d5959
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| 1 | 24f9e90b | bellard | |
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| 2 | 24f9e90b | bellard | void OPPROTO glue(glue(op_repz_scas, SUFFIX), STRING_SUFFIX)(void) |
| 3 | 24f9e90b | bellard | {
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| 4 | 24f9e90b | bellard | int v1, v2, inc;
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| 5 | 24f9e90b | bellard | |
| 6 | 24f9e90b | bellard | if (CX != 0) { |
| 7 | 24f9e90b | bellard | /* NOTE: the flags are not modified if CX == 0 */
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| 8 | 24f9e90b | bellard | v1 = EAX & DATA_MASK; |
| 9 | 24f9e90b | bellard | inc = (DF << SHIFT); |
| 10 | 24f9e90b | bellard | do {
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| 11 | 24f9e90b | bellard | v2 = glue(ldu, SUFFIX)(DI_ADDR); |
| 12 | 24f9e90b | bellard | INC_DI(); |
| 13 | 24f9e90b | bellard | DEC_CX(); |
| 14 | 24f9e90b | bellard | if (v1 != v2)
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| 15 | 24f9e90b | bellard | break;
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| 16 | 24f9e90b | bellard | } while (CX != 0); |
| 17 | 5797fa5d | bellard | CC_SRC = v2; |
| 18 | 24f9e90b | bellard | CC_DST = v1 - v2; |
| 19 | 24f9e90b | bellard | CC_OP = CC_OP_SUBB + SHIFT; |
| 20 | 24f9e90b | bellard | } |
| 21 | 24f9e90b | bellard | FORCE_RET(); |
| 22 | 24f9e90b | bellard | } |
| 23 | 24f9e90b | bellard | |
| 24 | 24f9e90b | bellard | void OPPROTO glue(glue(op_repnz_scas, SUFFIX), STRING_SUFFIX)(void) |
| 25 | 24f9e90b | bellard | {
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| 26 | 24f9e90b | bellard | int v1, v2, inc;
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| 27 | 24f9e90b | bellard | |
| 28 | 24f9e90b | bellard | if (CX != 0) { |
| 29 | 24f9e90b | bellard | /* NOTE: the flags are not modified if CX == 0 */
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| 30 | 24f9e90b | bellard | v1 = EAX & DATA_MASK; |
| 31 | 24f9e90b | bellard | inc = (DF << SHIFT); |
| 32 | 24f9e90b | bellard | do {
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| 33 | 24f9e90b | bellard | v2 = glue(ldu, SUFFIX)(DI_ADDR); |
| 34 | 24f9e90b | bellard | INC_DI(); |
| 35 | 24f9e90b | bellard | DEC_CX(); |
| 36 | 24f9e90b | bellard | if (v1 == v2)
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| 37 | 24f9e90b | bellard | break;
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| 38 | 24f9e90b | bellard | } while (CX != 0); |
| 39 | 5797fa5d | bellard | CC_SRC = v2; |
| 40 | 24f9e90b | bellard | CC_DST = v1 - v2; |
| 41 | 24f9e90b | bellard | CC_OP = CC_OP_SUBB + SHIFT; |
| 42 | 24f9e90b | bellard | } |
| 43 | 24f9e90b | bellard | FORCE_RET(); |
| 44 | 24f9e90b | bellard | } |
| 45 | 24f9e90b | bellard | |
| 46 | 24f9e90b | bellard | void OPPROTO glue(glue(op_repz_cmps, SUFFIX), STRING_SUFFIX)(void) |
| 47 | 24f9e90b | bellard | {
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| 48 | 24f9e90b | bellard | int v1, v2, inc;
|
| 49 | 24f9e90b | bellard | if (CX != 0) { |
| 50 | 24f9e90b | bellard | inc = (DF << SHIFT); |
| 51 | 24f9e90b | bellard | do {
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| 52 | 24f9e90b | bellard | v1 = glue(ldu, SUFFIX)(SI_ADDR); |
| 53 | 24f9e90b | bellard | v2 = glue(ldu, SUFFIX)(DI_ADDR); |
| 54 | 24f9e90b | bellard | INC_SI(); |
| 55 | 24f9e90b | bellard | INC_DI(); |
| 56 | 24f9e90b | bellard | DEC_CX(); |
| 57 | 24f9e90b | bellard | if (v1 != v2)
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| 58 | 24f9e90b | bellard | break;
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| 59 | 24f9e90b | bellard | } while (CX != 0); |
| 60 | 5797fa5d | bellard | CC_SRC = v2; |
| 61 | 24f9e90b | bellard | CC_DST = v1 - v2; |
| 62 | 24f9e90b | bellard | CC_OP = CC_OP_SUBB + SHIFT; |
| 63 | 24f9e90b | bellard | } |
| 64 | 24f9e90b | bellard | FORCE_RET(); |
| 65 | 24f9e90b | bellard | } |
| 66 | 24f9e90b | bellard | |
| 67 | 24f9e90b | bellard | void OPPROTO glue(glue(op_repnz_cmps, SUFFIX), STRING_SUFFIX)(void) |
| 68 | 24f9e90b | bellard | {
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| 69 | 24f9e90b | bellard | int v1, v2, inc;
|
| 70 | 24f9e90b | bellard | if (CX != 0) { |
| 71 | 24f9e90b | bellard | inc = (DF << SHIFT); |
| 72 | 24f9e90b | bellard | do {
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| 73 | 24f9e90b | bellard | v1 = glue(ldu, SUFFIX)(SI_ADDR); |
| 74 | 24f9e90b | bellard | v2 = glue(ldu, SUFFIX)(DI_ADDR); |
| 75 | 24f9e90b | bellard | INC_SI(); |
| 76 | 24f9e90b | bellard | INC_DI(); |
| 77 | 24f9e90b | bellard | DEC_CX(); |
| 78 | 24f9e90b | bellard | if (v1 == v2)
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| 79 | 24f9e90b | bellard | break;
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| 80 | 24f9e90b | bellard | } while (CX != 0); |
| 81 | 5797fa5d | bellard | CC_SRC = v2; |
| 82 | 24f9e90b | bellard | CC_DST = v1 - v2; |
| 83 | 24f9e90b | bellard | CC_OP = CC_OP_SUBB + SHIFT; |
| 84 | 24f9e90b | bellard | } |
| 85 | 24f9e90b | bellard | FORCE_RET(); |
| 86 | 24f9e90b | bellard | } |
| 87 | 24f9e90b | bellard | |
| 88 | 24f9e90b | bellard | #undef STRING_SUFFIX
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| 89 | 24f9e90b | bellard | #undef SI_ADDR
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| 90 | 24f9e90b | bellard | #undef DI_ADDR
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| 91 | 24f9e90b | bellard | #undef INC_SI
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| 92 | 24f9e90b | bellard | #undef INC_DI
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| 93 | 24f9e90b | bellard | #undef CX
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| 94 | 24f9e90b | bellard | #undef DEC_CX |