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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "monitor.h" |
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#include "net.h" |
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#include "sysemu.h" |
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//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
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#else
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# define PCI_DPRINTF(format, ...) do { } while (0) |
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#endif
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struct PCIBus {
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BusState qbus; |
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int devfn_min;
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pci_set_irq_fn set_irq; |
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pci_map_irq_fn map_irq; |
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pci_hotplug_fn hotplug; |
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uint32_t config_reg; /* XXX: suppress */
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void *irq_opaque;
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PCIDevice *devices[256];
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PCIDevice *parent_dev; |
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QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
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QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int *irq_count;
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}; |
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
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static struct BusInfo pci_bus_info = { |
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.name = "PCI",
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.size = sizeof(PCIBus),
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.print_dev = pcibus_dev_print, |
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.props = (Property[]) { |
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DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
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DEFINE_PROP_END_OF_LIST() |
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} |
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}; |
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static void pci_update_mappings(PCIDevice *d); |
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static void pci_set_irq(void *opaque, int irq_num, int level); |
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target_phys_addr_t pci_mem_base; |
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
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static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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struct PCIHostBus {
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int domain;
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struct PCIBus *bus;
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QLIST_ENTRY(PCIHostBus) next; |
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}; |
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static QLIST_HEAD(, PCIHostBus) host_buses;
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static const VMStateDescription vmstate_pcibus = { |
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.name = "PCIBUS",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_INT32_EQUAL(nirq, PCIBus), |
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VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static int pci_bar(PCIDevice *d, int reg) |
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{ |
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uint8_t type; |
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if (reg != PCI_ROM_SLOT)
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return PCI_BASE_ADDRESS_0 + reg * 4; |
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type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
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return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
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} |
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static inline int pci_irq_state(PCIDevice *d, int irq_num) |
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{ |
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return (d->irq_state >> irq_num) & 0x1; |
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} |
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static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) |
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{ |
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d->irq_state &= ~(0x1 << irq_num);
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d->irq_state |= level << irq_num; |
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} |
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static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) |
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{ |
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PCIBus *bus; |
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for (;;) {
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bus = pci_dev->bus; |
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irq_num = bus->map_irq(pci_dev, irq_num); |
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if (bus->set_irq)
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break;
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pci_dev = bus->parent_dev; |
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} |
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bus->irq_count[irq_num] += change; |
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bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
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} |
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/* Update interrupt status bit in config space on interrupt
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* state change. */
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static void pci_update_irq_status(PCIDevice *dev) |
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{ |
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if (dev->irq_state) {
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dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; |
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} else {
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dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; |
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} |
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} |
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static void pci_device_reset(PCIDevice *dev) |
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{ |
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int r;
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dev->irq_state = 0;
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pci_update_irq_status(dev); |
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dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
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PCI_COMMAND_MASTER); |
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dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
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dev->config[PCI_INTERRUPT_LINE] = 0x0;
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for (r = 0; r < PCI_NUM_REGIONS; ++r) { |
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if (!dev->io_regions[r].size) {
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continue;
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} |
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pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type); |
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} |
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pci_update_mappings(dev); |
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} |
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static void pci_bus_reset(void *opaque) |
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{ |
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PCIBus *bus = opaque; |
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int i;
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for (i = 0; i < bus->nirq; i++) { |
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bus->irq_count[i] = 0;
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} |
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for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
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if (bus->devices[i]) {
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pci_device_reset(bus->devices[i]); |
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} |
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} |
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} |
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static void pci_host_bus_register(int domain, PCIBus *bus) |
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{ |
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struct PCIHostBus *host;
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host = qemu_mallocz(sizeof(*host));
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host->domain = domain; |
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host->bus = bus; |
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QLIST_INSERT_HEAD(&host_buses, host, next); |
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} |
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PCIBus *pci_find_root_bus(int domain)
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{ |
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struct PCIHostBus *host;
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QLIST_FOREACH(host, &host_buses, next) { |
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if (host->domain == domain) {
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return host->bus;
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} |
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} |
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return NULL; |
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} |
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void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
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const char *name, int devfn_min) |
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{ |
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qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); |
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bus->devfn_min = devfn_min; |
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/* host bridge */
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QLIST_INIT(&bus->child); |
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pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ |
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vmstate_register(-1, &vmstate_pcibus, bus);
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qemu_register_reset(pci_bus_reset, bus); |
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} |
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PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min) |
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{ |
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PCIBus *bus; |
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bus = qemu_mallocz(sizeof(*bus));
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bus->qbus.qdev_allocated = 1;
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pci_bus_new_inplace(bus, parent, name, devfn_min); |
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return bus;
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} |
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void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *irq_opaque, int nirq) |
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{ |
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bus->set_irq = set_irq; |
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bus->map_irq = map_irq; |
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bus->irq_opaque = irq_opaque; |
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bus->nirq = nirq; |
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bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); |
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} |
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void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
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{ |
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bus->qbus.allow_hotplug = 1;
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bus->hotplug = hotplug; |
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} |
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PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
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void *irq_opaque, int devfn_min, int nirq) |
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{ |
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PCIBus *bus; |
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bus = pci_bus_new(parent, name, devfn_min); |
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pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
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return bus;
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} |
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static void pci_register_secondary_bus(PCIBus *parent, |
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PCIBus *bus, |
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PCIDevice *dev, |
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pci_map_irq_fn map_irq, |
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const char *name) |
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{ |
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qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name); |
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bus->map_irq = map_irq; |
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bus->parent_dev = dev; |
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QLIST_INIT(&bus->child); |
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QLIST_INSERT_HEAD(&parent->child, bus, sibling); |
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} |
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static void pci_unregister_secondary_bus(PCIBus *bus) |
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{ |
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assert(QLIST_EMPTY(&bus->child)); |
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QLIST_REMOVE(bus, sibling); |
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} |
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int pci_bus_num(PCIBus *s)
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{ |
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if (!s->parent_dev)
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return 0; /* pci host bridge */ |
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return s->parent_dev->config[PCI_SECONDARY_BUS];
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} |
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static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
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{ |
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PCIDevice *s = container_of(pv, PCIDevice, config); |
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uint8_t *config; |
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int i;
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assert(size == pci_config_size(s)); |
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config = qemu_malloc(size); |
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qemu_get_buffer(f, config, size); |
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for (i = 0; i < size; ++i) { |
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if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
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qemu_free(config); |
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return -EINVAL;
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} |
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} |
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memcpy(s->config, config, size); |
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pci_update_mappings(s); |
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qemu_free(config); |
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return 0; |
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} |
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/* just put buffer */
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static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
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{ |
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const uint8_t **v = pv;
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assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
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qemu_put_buffer(f, *v, size); |
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} |
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static VMStateInfo vmstate_info_pci_config = {
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.name = "pci config",
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.get = get_pci_config_device, |
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.put = put_pci_config_device, |
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}; |
313 |
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static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
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{ |
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PCIDevice *s = container_of(pv, PCIDevice, config); |
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uint32_t irq_state[PCI_NUM_PINS]; |
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int i;
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for (i = 0; i < PCI_NUM_PINS; ++i) { |
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irq_state[i] = qemu_get_be32(f); |
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if (irq_state[i] != 0x1 && irq_state[i] != 0) { |
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fprintf(stderr, "irq state %d: must be 0 or 1.\n",
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irq_state[i]); |
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return -EINVAL;
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} |
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} |
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for (i = 0; i < PCI_NUM_PINS; ++i) { |
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pci_set_irq_state(s, i, irq_state[i]); |
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} |
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return 0; |
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} |
334 |
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static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
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{ |
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int i;
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PCIDevice *s = container_of(pv, PCIDevice, config); |
339 |
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for (i = 0; i < PCI_NUM_PINS; ++i) { |
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qemu_put_be32(f, pci_irq_state(s, i)); |
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} |
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} |
344 |
|
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static VMStateInfo vmstate_info_pci_irq_state = {
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.name = "pci irq state",
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.get = get_pci_irq_state, |
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.put = put_pci_irq_state, |
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}; |
350 |
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const VMStateDescription vmstate_pci_device = {
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.name = "PCIDevice",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_INT32_LE(version_id, PCIDevice), |
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VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
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vmstate_info_pci_config, |
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PCI_CONFIG_SPACE_SIZE), |
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VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
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vmstate_info_pci_irq_state, |
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PCI_NUM_PINS * sizeof(int32_t)),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
367 |
|
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const VMStateDescription vmstate_pcie_device = {
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.name = "PCIDevice",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_INT32_LE(version_id, PCIDevice), |
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VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
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vmstate_info_pci_config, |
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PCIE_CONFIG_SPACE_SIZE), |
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VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
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vmstate_info_pci_irq_state, |
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PCI_NUM_PINS * sizeof(int32_t)),
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VMSTATE_END_OF_LIST() |
382 |
} |
383 |
}; |
384 |
|
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static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
386 |
{ |
387 |
return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
|
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} |
389 |
|
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void pci_device_save(PCIDevice *s, QEMUFile *f)
|
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{ |
392 |
/* Clear interrupt status bit: it is implicit
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* in irq_state which we are saving.
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* This makes us compatible with old devices
|
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* which never set or clear this bit. */
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s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; |
397 |
vmstate_save_state(f, pci_get_vmstate(s), s); |
398 |
/* Restore the interrupt status bit. */
|
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pci_update_irq_status(s); |
400 |
} |
401 |
|
402 |
int pci_device_load(PCIDevice *s, QEMUFile *f)
|
403 |
{ |
404 |
int ret;
|
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ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); |
406 |
/* Restore the interrupt status bit. */
|
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pci_update_irq_status(s); |
408 |
return ret;
|
409 |
} |
410 |
|
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static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
412 |
{ |
413 |
uint16_t *id; |
414 |
|
415 |
id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
|
416 |
id[0] = cpu_to_le16(pci_default_sub_vendor_id);
|
417 |
id[1] = cpu_to_le16(pci_default_sub_device_id);
|
418 |
return 0; |
419 |
} |
420 |
|
421 |
/*
|
422 |
* Parse [[<domain>:]<bus>:]<slot>, return -1 on error
|
423 |
*/
|
424 |
static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) |
425 |
{ |
426 |
const char *p; |
427 |
char *e;
|
428 |
unsigned long val; |
429 |
unsigned long dom = 0, bus = 0; |
430 |
unsigned slot = 0; |
431 |
|
432 |
p = addr; |
433 |
val = strtoul(p, &e, 16);
|
434 |
if (e == p)
|
435 |
return -1; |
436 |
if (*e == ':') { |
437 |
bus = val; |
438 |
p = e + 1;
|
439 |
val = strtoul(p, &e, 16);
|
440 |
if (e == p)
|
441 |
return -1; |
442 |
if (*e == ':') { |
443 |
dom = bus; |
444 |
bus = val; |
445 |
p = e + 1;
|
446 |
val = strtoul(p, &e, 16);
|
447 |
if (e == p)
|
448 |
return -1; |
449 |
} |
450 |
} |
451 |
|
452 |
if (dom > 0xffff || bus > 0xff || val > 0x1f) |
453 |
return -1; |
454 |
|
455 |
slot = val; |
456 |
|
457 |
if (*e)
|
458 |
return -1; |
459 |
|
460 |
/* Note: QEMU doesn't implement domains other than 0 */
|
461 |
if (!pci_find_bus(pci_find_root_bus(dom), bus))
|
462 |
return -1; |
463 |
|
464 |
*domp = dom; |
465 |
*busp = bus; |
466 |
*slotp = slot; |
467 |
return 0; |
468 |
} |
469 |
|
470 |
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
471 |
unsigned *slotp)
|
472 |
{ |
473 |
/* strip legacy tag */
|
474 |
if (!strncmp(addr, "pci_addr=", 9)) { |
475 |
addr += 9;
|
476 |
} |
477 |
if (pci_parse_devaddr(addr, domp, busp, slotp)) {
|
478 |
monitor_printf(mon, "Invalid pci address\n");
|
479 |
return -1; |
480 |
} |
481 |
return 0; |
482 |
} |
483 |
|
484 |
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
485 |
{ |
486 |
int dom, bus;
|
487 |
unsigned slot;
|
488 |
|
489 |
if (!devaddr) {
|
490 |
*devfnp = -1;
|
491 |
return pci_find_bus(pci_find_root_bus(0), 0); |
492 |
} |
493 |
|
494 |
if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { |
495 |
return NULL; |
496 |
} |
497 |
|
498 |
*devfnp = slot << 3;
|
499 |
return pci_find_bus(pci_find_root_bus(0), bus); |
500 |
} |
501 |
|
502 |
static void pci_init_cmask(PCIDevice *dev) |
503 |
{ |
504 |
pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
|
505 |
pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
|
506 |
dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; |
507 |
dev->cmask[PCI_REVISION_ID] = 0xff;
|
508 |
dev->cmask[PCI_CLASS_PROG] = 0xff;
|
509 |
pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
|
510 |
dev->cmask[PCI_HEADER_TYPE] = 0xff;
|
511 |
dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
|
512 |
} |
513 |
|
514 |
static void pci_init_wmask(PCIDevice *dev) |
515 |
{ |
516 |
int config_size = pci_config_size(dev);
|
517 |
|
518 |
dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
|
519 |
dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
|
520 |
pci_set_word(dev->wmask + PCI_COMMAND, |
521 |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
522 |
PCI_COMMAND_INTX_DISABLE); |
523 |
|
524 |
memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
|
525 |
config_size - PCI_CONFIG_HEADER_SIZE); |
526 |
} |
527 |
|
528 |
static void pci_init_wmask_bridge(PCIDevice *d) |
529 |
{ |
530 |
/* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
|
531 |
PCI_SEC_LETENCY_TIMER */
|
532 |
memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); |
533 |
|
534 |
/* base and limit */
|
535 |
d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
|
536 |
d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
|
537 |
pci_set_word(d->wmask + PCI_MEMORY_BASE, |
538 |
PCI_MEMORY_RANGE_MASK & 0xffff);
|
539 |
pci_set_word(d->wmask + PCI_MEMORY_LIMIT, |
540 |
PCI_MEMORY_RANGE_MASK & 0xffff);
|
541 |
pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, |
542 |
PCI_PREF_RANGE_MASK & 0xffff);
|
543 |
pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, |
544 |
PCI_PREF_RANGE_MASK & 0xffff);
|
545 |
|
546 |
/* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
|
547 |
memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); |
548 |
|
549 |
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
|
550 |
} |
551 |
|
552 |
static void pci_config_alloc(PCIDevice *pci_dev) |
553 |
{ |
554 |
int config_size = pci_config_size(pci_dev);
|
555 |
|
556 |
pci_dev->config = qemu_mallocz(config_size); |
557 |
pci_dev->cmask = qemu_mallocz(config_size); |
558 |
pci_dev->wmask = qemu_mallocz(config_size); |
559 |
pci_dev->used = qemu_mallocz(config_size); |
560 |
} |
561 |
|
562 |
static void pci_config_free(PCIDevice *pci_dev) |
563 |
{ |
564 |
qemu_free(pci_dev->config); |
565 |
qemu_free(pci_dev->cmask); |
566 |
qemu_free(pci_dev->wmask); |
567 |
qemu_free(pci_dev->used); |
568 |
} |
569 |
|
570 |
/* -1 for devfn means auto assign */
|
571 |
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
|
572 |
const char *name, int devfn, |
573 |
PCIConfigReadFunc *config_read, |
574 |
PCIConfigWriteFunc *config_write, |
575 |
uint8_t header_type) |
576 |
{ |
577 |
if (devfn < 0) { |
578 |
for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
|
579 |
devfn += 8) {
|
580 |
if (!bus->devices[devfn])
|
581 |
goto found;
|
582 |
} |
583 |
hw_error("PCI: no devfn available for %s, all in use\n", name);
|
584 |
found: ;
|
585 |
} else if (bus->devices[devfn]) { |
586 |
hw_error("PCI: devfn %d not available for %s, in use by %s\n", devfn,
|
587 |
name, bus->devices[devfn]->name); |
588 |
} |
589 |
pci_dev->bus = bus; |
590 |
pci_dev->devfn = devfn; |
591 |
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
592 |
pci_dev->irq_state = 0;
|
593 |
pci_config_alloc(pci_dev); |
594 |
|
595 |
header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
596 |
if (header_type == PCI_HEADER_TYPE_NORMAL) {
|
597 |
pci_set_default_subsystem_id(pci_dev); |
598 |
} |
599 |
pci_init_cmask(pci_dev); |
600 |
pci_init_wmask(pci_dev); |
601 |
if (header_type == PCI_HEADER_TYPE_BRIDGE) {
|
602 |
pci_init_wmask_bridge(pci_dev); |
603 |
} |
604 |
|
605 |
if (!config_read)
|
606 |
config_read = pci_default_read_config; |
607 |
if (!config_write)
|
608 |
config_write = pci_default_write_config; |
609 |
pci_dev->config_read = config_read; |
610 |
pci_dev->config_write = config_write; |
611 |
bus->devices[devfn] = pci_dev; |
612 |
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
613 |
pci_dev->version_id = 2; /* Current pci device vmstate version */ |
614 |
return pci_dev;
|
615 |
} |
616 |
|
617 |
PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
618 |
int instance_size, int devfn, |
619 |
PCIConfigReadFunc *config_read, |
620 |
PCIConfigWriteFunc *config_write) |
621 |
{ |
622 |
PCIDevice *pci_dev; |
623 |
|
624 |
pci_dev = qemu_mallocz(instance_size); |
625 |
pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, |
626 |
config_read, config_write, |
627 |
PCI_HEADER_TYPE_NORMAL); |
628 |
return pci_dev;
|
629 |
} |
630 |
static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
|
631 |
{ |
632 |
return addr + pci_mem_base;
|
633 |
} |
634 |
|
635 |
static void pci_unregister_io_regions(PCIDevice *pci_dev) |
636 |
{ |
637 |
PCIIORegion *r; |
638 |
int i;
|
639 |
|
640 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
641 |
r = &pci_dev->io_regions[i]; |
642 |
if (!r->size || r->addr == PCI_BAR_UNMAPPED)
|
643 |
continue;
|
644 |
if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
|
645 |
isa_unassign_ioport(r->addr, r->filtered_size); |
646 |
} else {
|
647 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
648 |
r->filtered_size, |
649 |
IO_MEM_UNASSIGNED); |
650 |
} |
651 |
} |
652 |
} |
653 |
|
654 |
static int pci_unregister_device(DeviceState *dev) |
655 |
{ |
656 |
PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev); |
657 |
PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info); |
658 |
int ret = 0; |
659 |
|
660 |
if (info->exit)
|
661 |
ret = info->exit(pci_dev); |
662 |
if (ret)
|
663 |
return ret;
|
664 |
|
665 |
pci_unregister_io_regions(pci_dev); |
666 |
|
667 |
qemu_free_irqs(pci_dev->irq); |
668 |
pci_dev->bus->devices[pci_dev->devfn] = NULL;
|
669 |
pci_config_free(pci_dev); |
670 |
return 0; |
671 |
} |
672 |
|
673 |
void pci_register_bar(PCIDevice *pci_dev, int region_num, |
674 |
pcibus_t size, int type,
|
675 |
PCIMapIORegionFunc *map_func) |
676 |
{ |
677 |
PCIIORegion *r; |
678 |
uint32_t addr; |
679 |
pcibus_t wmask; |
680 |
|
681 |
if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
682 |
return;
|
683 |
|
684 |
if (size & (size-1)) { |
685 |
fprintf(stderr, "ERROR: PCI region size must be pow2 "
|
686 |
"type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
687 |
exit(1);
|
688 |
} |
689 |
|
690 |
r = &pci_dev->io_regions[region_num]; |
691 |
r->addr = PCI_BAR_UNMAPPED; |
692 |
r->size = size; |
693 |
r->filtered_size = size; |
694 |
r->type = type; |
695 |
r->map_func = map_func; |
696 |
|
697 |
wmask = ~(size - 1);
|
698 |
addr = pci_bar(pci_dev, region_num); |
699 |
if (region_num == PCI_ROM_SLOT) {
|
700 |
/* ROM enable bit is writeable */
|
701 |
wmask |= PCI_ROM_ADDRESS_ENABLE; |
702 |
} |
703 |
pci_set_long(pci_dev->config + addr, type); |
704 |
if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
|
705 |
r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
706 |
pci_set_quad(pci_dev->wmask + addr, wmask); |
707 |
pci_set_quad(pci_dev->cmask + addr, ~0ULL);
|
708 |
} else {
|
709 |
pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
|
710 |
pci_set_long(pci_dev->cmask + addr, 0xffffffff);
|
711 |
} |
712 |
} |
713 |
|
714 |
static uint32_t pci_config_get_io_base(PCIDevice *d,
|
715 |
uint32_t base, uint32_t base_upper16) |
716 |
{ |
717 |
uint32_t val; |
718 |
|
719 |
val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
|
720 |
if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
|
721 |
val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
|
722 |
} |
723 |
return val;
|
724 |
} |
725 |
|
726 |
static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
|
727 |
{ |
728 |
return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
|
729 |
<< 16;
|
730 |
} |
731 |
|
732 |
static pcibus_t pci_config_get_pref_base(PCIDevice *d,
|
733 |
uint32_t base, uint32_t upper) |
734 |
{ |
735 |
pcibus_t tmp; |
736 |
pcibus_t val; |
737 |
|
738 |
tmp = (pcibus_t)pci_get_word(d->config + base); |
739 |
val = (tmp & PCI_PREF_RANGE_MASK) << 16;
|
740 |
if (tmp & PCI_PREF_RANGE_TYPE_64) {
|
741 |
val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
|
742 |
} |
743 |
return val;
|
744 |
} |
745 |
|
746 |
static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
|
747 |
{ |
748 |
pcibus_t base; |
749 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
750 |
base = pci_config_get_io_base(bridge, |
751 |
PCI_IO_BASE, PCI_IO_BASE_UPPER16); |
752 |
} else {
|
753 |
if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
|
754 |
base = pci_config_get_pref_base( |
755 |
bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); |
756 |
} else {
|
757 |
base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); |
758 |
} |
759 |
} |
760 |
|
761 |
return base;
|
762 |
} |
763 |
|
764 |
static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
|
765 |
{ |
766 |
pcibus_t limit; |
767 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
768 |
limit = pci_config_get_io_base(bridge, |
769 |
PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); |
770 |
limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ |
771 |
} else {
|
772 |
if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
|
773 |
limit = pci_config_get_pref_base( |
774 |
bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); |
775 |
} else {
|
776 |
limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); |
777 |
} |
778 |
limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ |
779 |
} |
780 |
return limit;
|
781 |
} |
782 |
|
783 |
static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size, |
784 |
uint8_t type) |
785 |
{ |
786 |
pcibus_t base = *addr; |
787 |
pcibus_t limit = *addr + *size - 1;
|
788 |
PCIDevice *br; |
789 |
|
790 |
for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
|
791 |
uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); |
792 |
|
793 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
794 |
if (!(cmd & PCI_COMMAND_IO)) {
|
795 |
goto no_map;
|
796 |
} |
797 |
} else {
|
798 |
if (!(cmd & PCI_COMMAND_MEMORY)) {
|
799 |
goto no_map;
|
800 |
} |
801 |
} |
802 |
|
803 |
base = MAX(base, pci_bridge_get_base(br, type)); |
804 |
limit = MIN(limit, pci_bridge_get_limit(br, type)); |
805 |
} |
806 |
|
807 |
if (base > limit) {
|
808 |
goto no_map;
|
809 |
} |
810 |
*addr = base; |
811 |
*size = limit - base + 1;
|
812 |
return;
|
813 |
no_map:
|
814 |
*addr = PCI_BAR_UNMAPPED; |
815 |
*size = 0;
|
816 |
} |
817 |
|
818 |
static pcibus_t pci_bar_address(PCIDevice *d,
|
819 |
int reg, uint8_t type, pcibus_t size)
|
820 |
{ |
821 |
pcibus_t new_addr, last_addr; |
822 |
int bar = pci_bar(d, reg);
|
823 |
uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); |
824 |
|
825 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
826 |
if (!(cmd & PCI_COMMAND_IO)) {
|
827 |
return PCI_BAR_UNMAPPED;
|
828 |
} |
829 |
new_addr = pci_get_long(d->config + bar) & ~(size - 1);
|
830 |
last_addr = new_addr + size - 1;
|
831 |
/* NOTE: we have only 64K ioports on PC */
|
832 |
if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { |
833 |
return PCI_BAR_UNMAPPED;
|
834 |
} |
835 |
return new_addr;
|
836 |
} |
837 |
|
838 |
if (!(cmd & PCI_COMMAND_MEMORY)) {
|
839 |
return PCI_BAR_UNMAPPED;
|
840 |
} |
841 |
if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
|
842 |
new_addr = pci_get_quad(d->config + bar); |
843 |
} else {
|
844 |
new_addr = pci_get_long(d->config + bar); |
845 |
} |
846 |
/* the ROM slot has a specific enable bit */
|
847 |
if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
|
848 |
return PCI_BAR_UNMAPPED;
|
849 |
} |
850 |
new_addr &= ~(size - 1);
|
851 |
last_addr = new_addr + size - 1;
|
852 |
/* NOTE: we do not support wrapping */
|
853 |
/* XXX: as we cannot support really dynamic
|
854 |
mappings, we handle specific values as invalid
|
855 |
mappings. */
|
856 |
if (last_addr <= new_addr || new_addr == 0 || |
857 |
last_addr == PCI_BAR_UNMAPPED) { |
858 |
return PCI_BAR_UNMAPPED;
|
859 |
} |
860 |
|
861 |
/* Now pcibus_t is 64bit.
|
862 |
* Check if 32 bit BAR wraps around explicitly.
|
863 |
* Without this, PC ide doesn't work well.
|
864 |
* TODO: remove this work around.
|
865 |
*/
|
866 |
if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
|
867 |
return PCI_BAR_UNMAPPED;
|
868 |
} |
869 |
|
870 |
/*
|
871 |
* OS is allowed to set BAR beyond its addressable
|
872 |
* bits. For example, 32 bit OS can set 64bit bar
|
873 |
* to >4G. Check it. TODO: we might need to support
|
874 |
* it in the future for e.g. PAE.
|
875 |
*/
|
876 |
if (last_addr >= TARGET_PHYS_ADDR_MAX) {
|
877 |
return PCI_BAR_UNMAPPED;
|
878 |
} |
879 |
|
880 |
return new_addr;
|
881 |
} |
882 |
|
883 |
static void pci_update_mappings(PCIDevice *d) |
884 |
{ |
885 |
PCIIORegion *r; |
886 |
int i;
|
887 |
pcibus_t new_addr, filtered_size; |
888 |
|
889 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
890 |
r = &d->io_regions[i]; |
891 |
|
892 |
/* this region isn't registered */
|
893 |
if (!r->size)
|
894 |
continue;
|
895 |
|
896 |
new_addr = pci_bar_address(d, i, r->type, r->size); |
897 |
|
898 |
/* bridge filtering */
|
899 |
filtered_size = r->size; |
900 |
if (new_addr != PCI_BAR_UNMAPPED) {
|
901 |
pci_bridge_filter(d, &new_addr, &filtered_size, r->type); |
902 |
} |
903 |
|
904 |
/* This bar isn't changed */
|
905 |
if (new_addr == r->addr && filtered_size == r->filtered_size)
|
906 |
continue;
|
907 |
|
908 |
/* now do the real mapping */
|
909 |
if (r->addr != PCI_BAR_UNMAPPED) {
|
910 |
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
911 |
int class;
|
912 |
/* NOTE: specific hack for IDE in PC case:
|
913 |
only one byte must be mapped. */
|
914 |
class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
915 |
if (class == 0x0101 && r->size == 4) { |
916 |
isa_unassign_ioport(r->addr + 2, 1); |
917 |
} else {
|
918 |
isa_unassign_ioport(r->addr, r->filtered_size); |
919 |
} |
920 |
} else {
|
921 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
922 |
r->filtered_size, |
923 |
IO_MEM_UNASSIGNED); |
924 |
qemu_unregister_coalesced_mmio(r->addr, r->filtered_size); |
925 |
} |
926 |
} |
927 |
r->addr = new_addr; |
928 |
r->filtered_size = filtered_size; |
929 |
if (r->addr != PCI_BAR_UNMAPPED) {
|
930 |
/*
|
931 |
* TODO: currently almost all the map funcions assumes
|
932 |
* filtered_size == size and addr & ~(size - 1) == addr.
|
933 |
* However with bridge filtering, they aren't always true.
|
934 |
* Teach them such cases, such that filtered_size < size and
|
935 |
* addr & (size - 1) != 0.
|
936 |
*/
|
937 |
r->map_func(d, i, r->addr, r->filtered_size, r->type); |
938 |
} |
939 |
} |
940 |
} |
941 |
|
942 |
static inline int pci_irq_disabled(PCIDevice *d) |
943 |
{ |
944 |
return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
|
945 |
} |
946 |
|
947 |
/* Called after interrupt disabled field update in config space,
|
948 |
* assert/deassert interrupts if necessary.
|
949 |
* Gets original interrupt disable bit value (before update). */
|
950 |
static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) |
951 |
{ |
952 |
int i, disabled = pci_irq_disabled(d);
|
953 |
if (disabled == was_irq_disabled)
|
954 |
return;
|
955 |
for (i = 0; i < PCI_NUM_PINS; ++i) { |
956 |
int state = pci_irq_state(d, i);
|
957 |
pci_change_irq_level(d, i, disabled ? -state : state); |
958 |
} |
959 |
} |
960 |
|
961 |
uint32_t pci_default_read_config(PCIDevice *d, |
962 |
uint32_t address, int len)
|
963 |
{ |
964 |
uint32_t val = 0;
|
965 |
assert(len == 1 || len == 2 || len == 4); |
966 |
len = MIN(len, pci_config_size(d) - address); |
967 |
memcpy(&val, d->config + address, len); |
968 |
return le32_to_cpu(val);
|
969 |
} |
970 |
|
971 |
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
972 |
{ |
973 |
int i, was_irq_disabled = pci_irq_disabled(d);
|
974 |
uint32_t config_size = pci_config_size(d); |
975 |
|
976 |
for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) { |
977 |
uint8_t wmask = d->wmask[addr + i]; |
978 |
d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
979 |
} |
980 |
if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
981 |
ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
|
982 |
ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
|
983 |
range_covers_byte(addr, l, PCI_COMMAND)) |
984 |
pci_update_mappings(d); |
985 |
|
986 |
if (range_covers_byte(addr, l, PCI_COMMAND))
|
987 |
pci_update_irq_disabled(d, was_irq_disabled); |
988 |
} |
989 |
|
990 |
/***********************************************************/
|
991 |
/* generic PCI irq support */
|
992 |
|
993 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
994 |
static void pci_set_irq(void *opaque, int irq_num, int level) |
995 |
{ |
996 |
PCIDevice *pci_dev = opaque; |
997 |
int change;
|
998 |
|
999 |
change = level - pci_irq_state(pci_dev, irq_num); |
1000 |
if (!change)
|
1001 |
return;
|
1002 |
|
1003 |
pci_set_irq_state(pci_dev, irq_num, level); |
1004 |
pci_update_irq_status(pci_dev); |
1005 |
if (pci_irq_disabled(pci_dev))
|
1006 |
return;
|
1007 |
pci_change_irq_level(pci_dev, irq_num, change); |
1008 |
} |
1009 |
|
1010 |
/***********************************************************/
|
1011 |
/* monitor info on PCI */
|
1012 |
|
1013 |
typedef struct { |
1014 |
uint16_t class; |
1015 |
const char *desc; |
1016 |
} pci_class_desc; |
1017 |
|
1018 |
static const pci_class_desc pci_class_descriptions[] = |
1019 |
{ |
1020 |
{ 0x0100, "SCSI controller"}, |
1021 |
{ 0x0101, "IDE controller"}, |
1022 |
{ 0x0102, "Floppy controller"}, |
1023 |
{ 0x0103, "IPI controller"}, |
1024 |
{ 0x0104, "RAID controller"}, |
1025 |
{ 0x0106, "SATA controller"}, |
1026 |
{ 0x0107, "SAS controller"}, |
1027 |
{ 0x0180, "Storage controller"}, |
1028 |
{ 0x0200, "Ethernet controller"}, |
1029 |
{ 0x0201, "Token Ring controller"}, |
1030 |
{ 0x0202, "FDDI controller"}, |
1031 |
{ 0x0203, "ATM controller"}, |
1032 |
{ 0x0280, "Network controller"}, |
1033 |
{ 0x0300, "VGA controller"}, |
1034 |
{ 0x0301, "XGA controller"}, |
1035 |
{ 0x0302, "3D controller"}, |
1036 |
{ 0x0380, "Display controller"}, |
1037 |
{ 0x0400, "Video controller"}, |
1038 |
{ 0x0401, "Audio controller"}, |
1039 |
{ 0x0402, "Phone"}, |
1040 |
{ 0x0480, "Multimedia controller"}, |
1041 |
{ 0x0500, "RAM controller"}, |
1042 |
{ 0x0501, "Flash controller"}, |
1043 |
{ 0x0580, "Memory controller"}, |
1044 |
{ 0x0600, "Host bridge"}, |
1045 |
{ 0x0601, "ISA bridge"}, |
1046 |
{ 0x0602, "EISA bridge"}, |
1047 |
{ 0x0603, "MC bridge"}, |
1048 |
{ 0x0604, "PCI bridge"}, |
1049 |
{ 0x0605, "PCMCIA bridge"}, |
1050 |
{ 0x0606, "NUBUS bridge"}, |
1051 |
{ 0x0607, "CARDBUS bridge"}, |
1052 |
{ 0x0608, "RACEWAY bridge"}, |
1053 |
{ 0x0680, "Bridge"}, |
1054 |
{ 0x0c03, "USB controller"}, |
1055 |
{ 0, NULL} |
1056 |
}; |
1057 |
|
1058 |
static void pci_info_device(PCIBus *bus, PCIDevice *d) |
1059 |
{ |
1060 |
Monitor *mon = cur_mon; |
1061 |
int i, class;
|
1062 |
PCIIORegion *r; |
1063 |
const pci_class_desc *desc;
|
1064 |
|
1065 |
monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
|
1066 |
pci_bus_num(d->bus), |
1067 |
PCI_SLOT(d->devfn), PCI_FUNC(d->devfn)); |
1068 |
class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
1069 |
monitor_printf(mon, " ");
|
1070 |
desc = pci_class_descriptions; |
1071 |
while (desc->desc && class != desc->class)
|
1072 |
desc++; |
1073 |
if (desc->desc) {
|
1074 |
monitor_printf(mon, "%s", desc->desc);
|
1075 |
} else {
|
1076 |
monitor_printf(mon, "Class %04x", class);
|
1077 |
} |
1078 |
monitor_printf(mon, ": PCI device %04x:%04x\n",
|
1079 |
pci_get_word(d->config + PCI_VENDOR_ID), |
1080 |
pci_get_word(d->config + PCI_DEVICE_ID)); |
1081 |
|
1082 |
if (d->config[PCI_INTERRUPT_PIN] != 0) { |
1083 |
monitor_printf(mon, " IRQ %d.\n",
|
1084 |
d->config[PCI_INTERRUPT_LINE]); |
1085 |
} |
1086 |
if (class == 0x0604) { |
1087 |
uint64_t base; |
1088 |
uint64_t limit; |
1089 |
|
1090 |
monitor_printf(mon, " BUS %d.\n", d->config[0x19]); |
1091 |
monitor_printf(mon, " secondary bus %d.\n",
|
1092 |
d->config[PCI_SECONDARY_BUS]); |
1093 |
monitor_printf(mon, " subordinate bus %d.\n",
|
1094 |
d->config[PCI_SUBORDINATE_BUS]); |
1095 |
|
1096 |
base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_IO); |
1097 |
limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_IO); |
1098 |
monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n", |
1099 |
base, limit); |
1100 |
|
1101 |
base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY); |
1102 |
limit= pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY); |
1103 |
monitor_printf(mon, |
1104 |
" memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n", |
1105 |
base, limit); |
1106 |
|
1107 |
base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY | |
1108 |
PCI_BASE_ADDRESS_MEM_PREFETCH); |
1109 |
limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY | |
1110 |
PCI_BASE_ADDRESS_MEM_PREFETCH); |
1111 |
monitor_printf(mon, " prefetchable memory range "
|
1112 |
"[0x%08"PRIx64", 0x%08"PRIx64"]\n", base, limit); |
1113 |
} |
1114 |
for(i = 0;i < PCI_NUM_REGIONS; i++) { |
1115 |
r = &d->io_regions[i]; |
1116 |
if (r->size != 0) { |
1117 |
monitor_printf(mon, " BAR%d: ", i);
|
1118 |
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
1119 |
monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
|
1120 |
" [0x%04"FMT_PCIBUS"].\n", |
1121 |
r->addr, r->addr + r->size - 1);
|
1122 |
} else {
|
1123 |
const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ? |
1124 |
"64 bit" : "32 bit"; |
1125 |
const char *prefetch = |
1126 |
r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ? |
1127 |
" prefetchable" : ""; |
1128 |
|
1129 |
monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS
|
1130 |
" [0x%08"FMT_PCIBUS"].\n", |
1131 |
type, prefetch, |
1132 |
r->addr, r->addr + r->size - 1);
|
1133 |
} |
1134 |
} |
1135 |
} |
1136 |
monitor_printf(mon, " id \"%s\"\n", d->qdev.id ? d->qdev.id : ""); |
1137 |
if (class == 0x0604 && d->config[0x19] != 0) { |
1138 |
pci_for_each_device(bus, d->config[0x19], pci_info_device);
|
1139 |
} |
1140 |
} |
1141 |
|
1142 |
static void pci_for_each_device_under_bus(PCIBus *bus, |
1143 |
void (*fn)(PCIBus *b, PCIDevice *d))
|
1144 |
{ |
1145 |
PCIDevice *d; |
1146 |
int devfn;
|
1147 |
|
1148 |
for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1149 |
d = bus->devices[devfn]; |
1150 |
if (d)
|
1151 |
fn(bus, d); |
1152 |
} |
1153 |
} |
1154 |
|
1155 |
void pci_for_each_device(PCIBus *bus, int bus_num, |
1156 |
void (*fn)(PCIBus *b, PCIDevice *d))
|
1157 |
{ |
1158 |
bus = pci_find_bus(bus, bus_num); |
1159 |
|
1160 |
if (bus) {
|
1161 |
pci_for_each_device_under_bus(bus, fn); |
1162 |
} |
1163 |
} |
1164 |
|
1165 |
void pci_info(Monitor *mon)
|
1166 |
{ |
1167 |
struct PCIHostBus *host;
|
1168 |
QLIST_FOREACH(host, &host_buses, next) { |
1169 |
pci_for_each_device(host->bus, 0, pci_info_device);
|
1170 |
} |
1171 |
} |
1172 |
|
1173 |
static const char * const pci_nic_models[] = { |
1174 |
"ne2k_pci",
|
1175 |
"i82551",
|
1176 |
"i82557b",
|
1177 |
"i82559er",
|
1178 |
"rtl8139",
|
1179 |
"e1000",
|
1180 |
"pcnet",
|
1181 |
"virtio",
|
1182 |
NULL
|
1183 |
}; |
1184 |
|
1185 |
static const char * const pci_nic_names[] = { |
1186 |
"ne2k_pci",
|
1187 |
"i82551",
|
1188 |
"i82557b",
|
1189 |
"i82559er",
|
1190 |
"rtl8139",
|
1191 |
"e1000",
|
1192 |
"pcnet",
|
1193 |
"virtio-net-pci",
|
1194 |
NULL
|
1195 |
}; |
1196 |
|
1197 |
/* Initialize a PCI NIC. */
|
1198 |
/* FIXME callers should check for failure, but don't */
|
1199 |
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
1200 |
const char *default_devaddr) |
1201 |
{ |
1202 |
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
1203 |
PCIBus *bus; |
1204 |
int devfn;
|
1205 |
PCIDevice *pci_dev; |
1206 |
DeviceState *dev; |
1207 |
int i;
|
1208 |
|
1209 |
i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
1210 |
if (i < 0) |
1211 |
return NULL; |
1212 |
|
1213 |
bus = pci_get_bus_devfn(&devfn, devaddr); |
1214 |
if (!bus) {
|
1215 |
qemu_error("Invalid PCI device address %s for device %s\n",
|
1216 |
devaddr, pci_nic_names[i]); |
1217 |
return NULL; |
1218 |
} |
1219 |
|
1220 |
pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
1221 |
dev = &pci_dev->qdev; |
1222 |
if (nd->name)
|
1223 |
dev->id = qemu_strdup(nd->name); |
1224 |
qdev_set_nic_properties(dev, nd); |
1225 |
if (qdev_init(dev) < 0) |
1226 |
return NULL; |
1227 |
return pci_dev;
|
1228 |
} |
1229 |
|
1230 |
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
1231 |
const char *default_devaddr) |
1232 |
{ |
1233 |
PCIDevice *res; |
1234 |
|
1235 |
if (qemu_show_nic_models(nd->model, pci_nic_models))
|
1236 |
exit(0);
|
1237 |
|
1238 |
res = pci_nic_init(nd, default_model, default_devaddr); |
1239 |
if (!res)
|
1240 |
exit(1);
|
1241 |
return res;
|
1242 |
} |
1243 |
|
1244 |
typedef struct { |
1245 |
PCIDevice dev; |
1246 |
PCIBus bus; |
1247 |
uint32_t vid; |
1248 |
uint32_t did; |
1249 |
} PCIBridge; |
1250 |
|
1251 |
|
1252 |
static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d) |
1253 |
{ |
1254 |
pci_update_mappings(d); |
1255 |
} |
1256 |
|
1257 |
static void pci_bridge_update_mappings(PCIBus *b) |
1258 |
{ |
1259 |
PCIBus *child; |
1260 |
|
1261 |
pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn); |
1262 |
|
1263 |
QLIST_FOREACH(child, &b->child, sibling) { |
1264 |
pci_bridge_update_mappings(child); |
1265 |
} |
1266 |
} |
1267 |
|
1268 |
static void pci_bridge_write_config(PCIDevice *d, |
1269 |
uint32_t address, uint32_t val, int len)
|
1270 |
{ |
1271 |
pci_default_write_config(d, address, val, len); |
1272 |
|
1273 |
if (/* io base/limit */ |
1274 |
ranges_overlap(address, len, PCI_IO_BASE, 2) ||
|
1275 |
|
1276 |
/* memory base/limit, prefetchable base/limit and
|
1277 |
io base/limit upper 16 */
|
1278 |
ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
|
1279 |
pci_bridge_update_mappings(d->bus); |
1280 |
} |
1281 |
} |
1282 |
|
1283 |
PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
|
1284 |
{ |
1285 |
PCIBus *sec; |
1286 |
|
1287 |
if (!bus)
|
1288 |
return NULL; |
1289 |
|
1290 |
if (pci_bus_num(bus) == bus_num) {
|
1291 |
return bus;
|
1292 |
} |
1293 |
|
1294 |
/* try child bus */
|
1295 |
QLIST_FOREACH(sec, &bus->child, sibling) { |
1296 |
|
1297 |
if (!bus->parent_dev /* pci host bridge */ |
1298 |
|| (pci_bus_num(sec) <= bus_num && |
1299 |
bus->parent_dev->config[PCI_SUBORDINATE_BUS])) { |
1300 |
return pci_find_bus(sec, bus_num);
|
1301 |
} |
1302 |
} |
1303 |
|
1304 |
return NULL; |
1305 |
} |
1306 |
|
1307 |
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function) |
1308 |
{ |
1309 |
bus = pci_find_bus(bus, bus_num); |
1310 |
|
1311 |
if (!bus)
|
1312 |
return NULL; |
1313 |
|
1314 |
return bus->devices[PCI_DEVFN(slot, function)];
|
1315 |
} |
1316 |
|
1317 |
static int pci_bridge_initfn(PCIDevice *dev) |
1318 |
{ |
1319 |
PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev); |
1320 |
|
1321 |
pci_config_set_vendor_id(s->dev.config, s->vid); |
1322 |
pci_config_set_device_id(s->dev.config, s->did); |
1323 |
|
1324 |
pci_set_word(dev->config + PCI_STATUS, |
1325 |
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
1326 |
pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); |
1327 |
dev->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; |
1328 |
pci_set_word(dev->config + PCI_SEC_STATUS, |
1329 |
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
1330 |
return 0; |
1331 |
} |
1332 |
|
1333 |
static int pci_bridge_exitfn(PCIDevice *pci_dev) |
1334 |
{ |
1335 |
PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); |
1336 |
PCIBus *bus = &s->bus; |
1337 |
pci_unregister_secondary_bus(bus); |
1338 |
return 0; |
1339 |
} |
1340 |
|
1341 |
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
|
1342 |
pci_map_irq_fn map_irq, const char *name) |
1343 |
{ |
1344 |
PCIDevice *dev; |
1345 |
PCIBridge *s; |
1346 |
|
1347 |
dev = pci_create(bus, devfn, "pci-bridge");
|
1348 |
qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
|
1349 |
qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
|
1350 |
qdev_init_nofail(&dev->qdev); |
1351 |
|
1352 |
s = DO_UPCAST(PCIBridge, dev, dev); |
1353 |
pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name); |
1354 |
return &s->bus;
|
1355 |
} |
1356 |
|
1357 |
PCIDevice *pci_bridge_get_device(PCIBus *bus) |
1358 |
{ |
1359 |
return bus->parent_dev;
|
1360 |
} |
1361 |
|
1362 |
static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
1363 |
{ |
1364 |
PCIDevice *pci_dev = (PCIDevice *)qdev; |
1365 |
PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
1366 |
PCIBus *bus; |
1367 |
int devfn, rc;
|
1368 |
|
1369 |
/* initialize cap_present for pci_is_express() and pci_config_size() */
|
1370 |
if (info->is_express) {
|
1371 |
pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; |
1372 |
} |
1373 |
|
1374 |
bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
1375 |
devfn = pci_dev->devfn; |
1376 |
pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
1377 |
info->config_read, info->config_write, |
1378 |
info->header_type); |
1379 |
rc = info->init(pci_dev); |
1380 |
if (rc != 0) |
1381 |
return rc;
|
1382 |
if (qdev->hotplugged)
|
1383 |
bus->hotplug(pci_dev, 1);
|
1384 |
return 0; |
1385 |
} |
1386 |
|
1387 |
static int pci_unplug_device(DeviceState *qdev) |
1388 |
{ |
1389 |
PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); |
1390 |
|
1391 |
dev->bus->hotplug(dev, 0);
|
1392 |
return 0; |
1393 |
} |
1394 |
|
1395 |
void pci_qdev_register(PCIDeviceInfo *info)
|
1396 |
{ |
1397 |
info->qdev.init = pci_qdev_init; |
1398 |
info->qdev.unplug = pci_unplug_device; |
1399 |
info->qdev.exit = pci_unregister_device; |
1400 |
info->qdev.bus_info = &pci_bus_info; |
1401 |
qdev_register(&info->qdev); |
1402 |
} |
1403 |
|
1404 |
void pci_qdev_register_many(PCIDeviceInfo *info)
|
1405 |
{ |
1406 |
while (info->qdev.name) {
|
1407 |
pci_qdev_register(info); |
1408 |
info++; |
1409 |
} |
1410 |
} |
1411 |
|
1412 |
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
1413 |
{ |
1414 |
DeviceState *dev; |
1415 |
|
1416 |
dev = qdev_create(&bus->qbus, name); |
1417 |
qdev_prop_set_uint32(dev, "addr", devfn);
|
1418 |
return DO_UPCAST(PCIDevice, qdev, dev);
|
1419 |
} |
1420 |
|
1421 |
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
1422 |
{ |
1423 |
PCIDevice *dev = pci_create(bus, devfn, name); |
1424 |
qdev_init_nofail(&dev->qdev); |
1425 |
return dev;
|
1426 |
} |
1427 |
|
1428 |
static int pci_find_space(PCIDevice *pdev, uint8_t size) |
1429 |
{ |
1430 |
int config_size = pci_config_size(pdev);
|
1431 |
int offset = PCI_CONFIG_HEADER_SIZE;
|
1432 |
int i;
|
1433 |
for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
|
1434 |
if (pdev->used[i])
|
1435 |
offset = i + 1;
|
1436 |
else if (i - offset + 1 == size) |
1437 |
return offset;
|
1438 |
return 0; |
1439 |
} |
1440 |
|
1441 |
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
|
1442 |
uint8_t *prev_p) |
1443 |
{ |
1444 |
uint8_t next, prev; |
1445 |
|
1446 |
if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
|
1447 |
return 0; |
1448 |
|
1449 |
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
1450 |
prev = next + PCI_CAP_LIST_NEXT) |
1451 |
if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
|
1452 |
break;
|
1453 |
|
1454 |
if (prev_p)
|
1455 |
*prev_p = prev; |
1456 |
return next;
|
1457 |
} |
1458 |
|
1459 |
/* Reserve space and add capability to the linked list in pci config space */
|
1460 |
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
1461 |
{ |
1462 |
uint8_t offset = pci_find_space(pdev, size); |
1463 |
uint8_t *config = pdev->config + offset; |
1464 |
if (!offset)
|
1465 |
return -ENOSPC;
|
1466 |
config[PCI_CAP_LIST_ID] = cap_id; |
1467 |
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; |
1468 |
pdev->config[PCI_CAPABILITY_LIST] = offset; |
1469 |
pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; |
1470 |
memset(pdev->used + offset, 0xFF, size);
|
1471 |
/* Make capability read-only by default */
|
1472 |
memset(pdev->wmask + offset, 0, size);
|
1473 |
/* Check capability by default */
|
1474 |
memset(pdev->cmask + offset, 0xFF, size);
|
1475 |
return offset;
|
1476 |
} |
1477 |
|
1478 |
/* Unlink capability from the pci config space. */
|
1479 |
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
1480 |
{ |
1481 |
uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); |
1482 |
if (!offset)
|
1483 |
return;
|
1484 |
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; |
1485 |
/* Make capability writeable again */
|
1486 |
memset(pdev->wmask + offset, 0xff, size);
|
1487 |
/* Clear cmask as device-specific registers can't be checked */
|
1488 |
memset(pdev->cmask + offset, 0, size);
|
1489 |
memset(pdev->used + offset, 0, size);
|
1490 |
|
1491 |
if (!pdev->config[PCI_CAPABILITY_LIST])
|
1492 |
pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; |
1493 |
} |
1494 |
|
1495 |
/* Reserve space for capability at a known offset (to call after load). */
|
1496 |
void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
|
1497 |
{ |
1498 |
memset(pdev->used + offset, 0xff, size);
|
1499 |
} |
1500 |
|
1501 |
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
1502 |
{ |
1503 |
return pci_find_capability_list(pdev, cap_id, NULL); |
1504 |
} |
1505 |
|
1506 |
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) |
1507 |
{ |
1508 |
PCIDevice *d = (PCIDevice *)dev; |
1509 |
const pci_class_desc *desc;
|
1510 |
char ctxt[64]; |
1511 |
PCIIORegion *r; |
1512 |
int i, class;
|
1513 |
|
1514 |
class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
1515 |
desc = pci_class_descriptions; |
1516 |
while (desc->desc && class != desc->class)
|
1517 |
desc++; |
1518 |
if (desc->desc) {
|
1519 |
snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); |
1520 |
} else {
|
1521 |
snprintf(ctxt, sizeof(ctxt), "Class %04x", class); |
1522 |
} |
1523 |
|
1524 |
monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
|
1525 |
"pci id %04x:%04x (sub %04x:%04x)\n",
|
1526 |
indent, "", ctxt,
|
1527 |
d->config[PCI_SECONDARY_BUS], |
1528 |
PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), |
1529 |
pci_get_word(d->config + PCI_VENDOR_ID), |
1530 |
pci_get_word(d->config + PCI_DEVICE_ID), |
1531 |
pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), |
1532 |
pci_get_word(d->config + PCI_SUBSYSTEM_ID)); |
1533 |
for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1534 |
r = &d->io_regions[i]; |
1535 |
if (!r->size)
|
1536 |
continue;
|
1537 |
monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
|
1538 |
" [0x%"FMT_PCIBUS"]\n", |
1539 |
indent, "",
|
1540 |
i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
1541 |
r->addr, r->addr + r->size - 1);
|
1542 |
} |
1543 |
} |
1544 |
|
1545 |
static PCIDeviceInfo bridge_info = {
|
1546 |
.qdev.name = "pci-bridge",
|
1547 |
.qdev.size = sizeof(PCIBridge),
|
1548 |
.init = pci_bridge_initfn, |
1549 |
.exit = pci_bridge_exitfn, |
1550 |
.config_write = pci_bridge_write_config, |
1551 |
.qdev.props = (Property[]) { |
1552 |
DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0), |
1553 |
DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0), |
1554 |
DEFINE_PROP_END_OF_LIST(), |
1555 |
} |
1556 |
}; |
1557 |
|
1558 |
static void pci_register_devices(void) |
1559 |
{ |
1560 |
pci_qdev_register(&bridge_info); |
1561 |
} |
1562 |
|
1563 |
device_init(pci_register_devices) |