Archipelago » qemu

/*

 *  MIPS emulation helpers for qemu.

 *

 *  Copyright (c) 2004-2005 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdlib.h>

#include "exec.h"

#include "host-utils.h"

/*****************************************************************************/

/* Exceptions processing helpers */

void do_raise_exception_err (uint32_t exception, int error_code)

{

#if 1

    if (logfile && exception < 0x100)

        fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);

#endif

    env->exception_index = exception;

    env->error_code = error_code;

    T0 = 0;

    cpu_loop_exit();

}

void do_raise_exception (uint32_t exception)

{

    do_raise_exception_err(exception, 0);

}

void do_interrupt_restart (void)

{

    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&

        !(env->CP0_Status & (1 << CP0St_ERL)) &&

        !(env->hflags & MIPS_HFLAG_DM) &&

        (env->CP0_Status & (1 << CP0St_IE)) &&

        (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {

        env->CP0_Cause &= ~(0x1f << CP0Ca_EC);

        do_raise_exception(EXCP_EXT_INTERRUPT);

    }

}

void do_restore_state (void *pc_ptr)

{

    TranslationBlock *tb;

    unsigned long pc = (unsigned long) pc_ptr;

    tb = tb_find_pc (pc);

    if (tb) {

        cpu_restore_state (tb, env, pc, NULL);

    }

}

void do_clo (void)

{

    T0 = clo32(T0);

}

void do_clz (void)

{

    T0 = clz32(T0);

}

#if defined(TARGET_MIPS64)

#if TARGET_LONG_BITS > HOST_LONG_BITS

/* Those might call libgcc functions.  */

void do_dsll (void)

{

    T0 = T0 << T1;

}

void do_dsll32 (void)

{

    T0 = T0 << (T1 + 32);

}

void do_dsra (void)

{

    T0 = (int64_t)T0 >> T1;

}

void do_dsra32 (void)

{

    T0 = (int64_t)T0 >> (T1 + 32);

}

void do_dsrl (void)

{

    T0 = T0 >> T1;

}

void do_dsrl32 (void)

{

    T0 = T0 >> (T1 + 32);

}

void do_drotr (void)

{

    target_ulong tmp;

    if (T1) {

        tmp = T0 << (0x40 - T1);

        T0 = (T0 >> T1) | tmp;

    }

}

void do_drotr32 (void)

{

    target_ulong tmp;

    tmp = T0 << (0x40 - (32 + T1));

    T0 = (T0 >> (32 + T1)) | tmp;

}

void do_dsllv (void)

{

    T0 = T1 << (T0 & 0x3F);

}

void do_dsrav (void)

{

    T0 = (int64_t)T1 >> (T0 & 0x3F);

}

void do_dsrlv (void)

{

    T0 = T1 >> (T0 & 0x3F);

}

void do_drotrv (void)

{

    target_ulong tmp;

    T0 &= 0x3F;

    if (T0) {

        tmp = T1 << (0x40 - T0);

        T0 = (T1 >> T0) | tmp;

    } else

        T0 = T1;

}

#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */

void do_dclo (void)

{

    T0 = clo64(T0);

}

void do_dclz (void)

{

    T0 = clz64(T0);

}

#endif /* TARGET_MIPS64 */

/* 64 bits arithmetic for 32 bits hosts */

static always_inline uint64_t get_HILO (void)

{

    return ((uint64_t)(env->HI[env->current_tc][0]) << 32) | (uint32_t)env->LO[env->current_tc][0];

}

static always_inline void set_HILO (uint64_t HILO)

{

    env->LO[env->current_tc][0] = (int32_t)HILO;

    env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);

}

static always_inline void set_HIT0_LO (uint64_t HILO)

{

    env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);

    T0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);

}

static always_inline void set_HI_LOT0 (uint64_t HILO)

{

    T0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);

    env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);

}

#if TARGET_LONG_BITS > HOST_LONG_BITS

void do_madd (void)

{

    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);

    set_HILO((int64_t)get_HILO() + tmp);

}

void do_maddu (void)

{

    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);

    set_HILO(get_HILO() + tmp);

}

void do_msub (void)

{

    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);

    set_HILO((int64_t)get_HILO() - tmp);

}

void do_msubu (void)

{

    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);

    set_HILO(get_HILO() - tmp);

}

#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */

/* Multiplication variants of the vr54xx. */

void do_muls (void)

{

    set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));

}

void do_mulsu (void)

{

    set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));

}

void do_macc (void)

{

    set_HI_LOT0(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));

}

void do_macchi (void)

{

    set_HIT0_LO(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));

}

void do_maccu (void)

{

    set_HI_LOT0(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));

}

void do_macchiu (void)

{

    set_HIT0_LO(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));

}

void do_msac (void)

{

    set_HI_LOT0(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));

}

void do_msachi (void)

{

    set_HIT0_LO(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));

}

void do_msacu (void)

{

    set_HI_LOT0(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));

}

void do_msachiu (void)

{

    set_HIT0_LO(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));

}

void do_mulhi (void)

{

    set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);

}

void do_mulhiu (void)

{

    set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);

}

void do_mulshi (void)

{

    set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));

}

void do_mulshiu (void)

{

    set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));

}

#ifdef TARGET_MIPS64

void do_dmult (void)

{

    muls64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1);

}

void do_dmultu (void)

{

    mulu64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1);

}

#endif

#ifdef TARGET_WORDS_BIGENDIAN

#define GET_LMASK(v) ((v) & 3)

#define GET_OFFSET(addr, offset) (addr + (offset))

#else

#define GET_LMASK(v) (((v) & 3) ^ 3)

#define GET_OFFSET(addr, offset) (addr - (offset))

#endif

void do_lwl(int mem_idx)

{

    target_ulong tmp;

#ifdef CONFIG_USER_ONLY

#define ldfun ldub_raw

#else

    int (*ldfun)(target_ulong);

    switch (mem_idx)

    {

    case 0: ldfun = ldub_kernel; break;

    case 1: ldfun = ldub_super; break;

    default:

    case 2: ldfun = ldub_user; break;

    }

#endif

    tmp = ldfun(T0);

    T1 = (T1 & 0x00FFFFFF) | (tmp << 24);

    if (GET_LMASK(T0) <= 2) {

        tmp = ldfun(GET_OFFSET(T0, 1));

        T1 = (T1 & 0xFF00FFFF) | (tmp << 16);

    }

    if (GET_LMASK(T0) <= 1) {

        tmp = ldfun(GET_OFFSET(T0, 2));

        T1 = (T1 & 0xFFFF00FF) | (tmp << 8);

    }

    if (GET_LMASK(T0) == 0) {

        tmp = ldfun(GET_OFFSET(T0, 3));

        T1 = (T1 & 0xFFFFFF00) | tmp;

    }

    T1 = (int32_t)T1;

}

void do_lwr(int mem_idx)

{

    target_ulong tmp;

#ifdef CONFIG_USER_ONLY

#define ldfun ldub_raw

#else

    int (*ldfun)(target_ulong);

    switch (mem_idx)

    {

    case 0: ldfun = ldub_kernel; break;

    case 1: ldfun = ldub_super; break;

    default:

    case 2: ldfun = ldub_user; break;

    }

#endif

    tmp = ldfun(T0);

    T1 = (T1 & 0xFFFFFF00) | tmp;

    if (GET_LMASK(T0) >= 1) {

        tmp = ldfun(GET_OFFSET(T0, -1));

        T1 = (T1 & 0xFFFF00FF) | (tmp << 8);

    }

    if (GET_LMASK(T0) >= 2) {

        tmp = ldfun(GET_OFFSET(T0, -2));

        T1 = (T1 & 0xFF00FFFF) | (tmp << 16);

    }

    if (GET_LMASK(T0) == 3) {

        tmp = ldfun(GET_OFFSET(T0, -3));

        T1 = (T1 & 0x00FFFFFF) | (tmp << 24);

    }

    T1 = (int32_t)T1;

}

void do_swl(int mem_idx)

{

#ifdef CONFIG_USER_ONLY

#define stfun stb_raw

#else

    void (*stfun)(target_ulong, int);

    switch (mem_idx)

    {

    case 0: stfun = stb_kernel; break;

    case 1: stfun = stb_super; break;

    default:

    case 2: stfun = stb_user; break;

    }

#endif

    stfun(T0, (uint8_t)(T1 >> 24));

    if (GET_LMASK(T0) <= 2)

        stfun(GET_OFFSET(T0, 1), (uint8_t)(T1 >> 16));

    if (GET_LMASK(T0) <= 1)

        stfun(GET_OFFSET(T0, 2), (uint8_t)(T1 >> 8));

    if (GET_LMASK(T0) == 0)

        stfun(GET_OFFSET(T0, 3), (uint8_t)T1);

}

void do_swr(int mem_idx)

{

#ifdef CONFIG_USER_ONLY

#define stfun stb_raw

#else

    void (*stfun)(target_ulong, int);

    switch (mem_idx)

    {

    case 0: stfun = stb_kernel; break;

    case 1: stfun = stb_super; break;

    default:

    case 2: stfun = stb_user; break;

    }

#endif

    stfun(T0, (uint8_t)T1);

    if (GET_LMASK(T0) >= 1)

        stfun(GET_OFFSET(T0, -1), (uint8_t)(T1 >> 8));

    if (GET_LMASK(T0) >= 2)

        stfun(GET_OFFSET(T0, -2), (uint8_t)(T1 >> 16));

    if (GET_LMASK(T0) == 3)

        stfun(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24));

}

#if defined(TARGET_MIPS64)

/* "half" load and stores.  We must do the memory access inline,

   or fault handling won't work.  */

#ifdef TARGET_WORDS_BIGENDIAN

#define GET_LMASK64(v) ((v) & 7)

#else

#define GET_LMASK64(v) (((v) & 7) ^ 7)

#endif

void do_ldl(int mem_idx)

{

    uint64_t tmp;

#ifdef CONFIG_USER_ONLY

#define ldfun ldub_raw

#else

    target_ulong (*ldfun)(target_ulong);

    switch (mem_idx)

    {

    case 0: ldfun = ldub_kernel; break;

    case 1: ldfun = ldub_super; break;

    default:

    case 2: ldfun = ldub_user; break;

    }

#endif

    tmp = ldfun(T0);

    T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);

    if (GET_LMASK64(T0) <= 6) {

        tmp = ldfun(GET_OFFSET(T0, 1));

        T1 = (T1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);

    }

    if (GET_LMASK64(T0) <= 5) {

        tmp = ldfun(GET_OFFSET(T0, 2));

        T1 = (T1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);

    }

    if (GET_LMASK64(T0) <= 4) {

        tmp = ldfun(GET_OFFSET(T0, 3));

        T1 = (T1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);

    }

    if (GET_LMASK64(T0) <= 3) {

        tmp = ldfun(GET_OFFSET(T0, 4));

        T1 = (T1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);

    }

    if (GET_LMASK64(T0) <= 2) {

        tmp = ldfun(GET_OFFSET(T0, 5));

        T1 = (T1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);

    }

    if (GET_LMASK64(T0) <= 1) {

        tmp = ldfun(GET_OFFSET(T0, 6));

        T1 = (T1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);

    }

    if (GET_LMASK64(T0) == 0) {

        tmp = ldfun(GET_OFFSET(T0, 7));

        T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;

    }

}

void do_ldr(int mem_idx)

{

    uint64_t tmp;

#ifdef CONFIG_USER_ONLY

#define ldfun ldub_raw

#else

    target_ulong (*ldfun)(target_ulong);

    switch (mem_idx)

    {

    case 0: ldfun = ldub_kernel; break;

    case 1: ldfun = ldub_super; break;

    default:

    case 2: ldfun = ldub_user; break;

    }

#endif

    tmp = ldfun(T0);

    T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;

    if (GET_LMASK64(T0) >= 1) {

        tmp = ldfun(GET_OFFSET(T0, -1));

        T1 = (T1 & 0xFFFFFFFFFFFF00FFULL) | (tmp  << 8);

    }

    if (GET_LMASK64(T0) >= 2) {

        tmp = ldfun(GET_OFFSET(T0, -2));

        T1 = (T1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);

    }

    if (GET_LMASK64(T0) >= 3) {

        tmp = ldfun(GET_OFFSET(T0, -3));

        T1 = (T1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);

    }

    if (GET_LMASK64(T0) >= 4) {

        tmp = ldfun(GET_OFFSET(T0, -4));

        T1 = (T1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);

    }

    if (GET_LMASK64(T0) >= 5) {

        tmp = ldfun(GET_OFFSET(T0, -5));

        T1 = (T1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);

    }

    if (GET_LMASK64(T0) >= 6) {

        tmp = ldfun(GET_OFFSET(T0, -6));

        T1 = (T1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);

    }

    if (GET_LMASK64(T0) == 7) {

        tmp = ldfun(GET_OFFSET(T0, -7));

        T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);

    }

}

void do_sdl(int mem_idx)

{

#ifdef CONFIG_USER_ONLY

#define stfun stb_raw

#else

    void (*stfun)(target_ulong, int);

    switch (mem_idx)

    {

    case 0: stfun = stb_kernel; break;

    case 1: stfun = stb_super; break;

    default:

    case 2: stfun = stb_user; break;

    }

#endif

    stfun(T0, (uint8_t)(T1 >> 56));

    if (GET_LMASK64(T0) <= 6)

        stfun(GET_OFFSET(T0, 1), (uint8_t)(T1 >> 48));

    if (GET_LMASK64(T0) <= 5)

        stfun(GET_OFFSET(T0, 2), (uint8_t)(T1 >> 40));

    if (GET_LMASK64(T0) <= 4)

        stfun(GET_OFFSET(T0, 3), (uint8_t)(T1 >> 32));

    if (GET_LMASK64(T0) <= 3)

        stfun(GET_OFFSET(T0, 4), (uint8_t)(T1 >> 24));

    if (GET_LMASK64(T0) <= 2)

        stfun(GET_OFFSET(T0, 5), (uint8_t)(T1 >> 16));

    if (GET_LMASK64(T0) <= 1)

        stfun(GET_OFFSET(T0, 6), (uint8_t)(T1 >> 8));

    if (GET_LMASK64(T0) <= 0)

        stfun(GET_OFFSET(T0, 7), (uint8_t)T1);

}

void do_sdr(int mem_idx)

{

#ifdef CONFIG_USER_ONLY

#define stfun stb_raw

#else

    void (*stfun)(target_ulong, int);

    switch (mem_idx)

    {

    case 0: stfun = stb_kernel; break;

    case 1: stfun = stb_super; break;

     default:

    case 2: stfun = stb_user; break;

    }

#endif

    stfun(T0, (uint8_t)T1);

    if (GET_LMASK64(T0) >= 1)

        stfun(GET_OFFSET(T0, -1), (uint8_t)(T1 >> 8));

    if (GET_LMASK64(T0) >= 2)

        stfun(GET_OFFSET(T0, -2), (uint8_t)(T1 >> 16));

    if (GET_LMASK64(T0) >= 3)

        stfun(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24));

    if (GET_LMASK64(T0) >= 4)

        stfun(GET_OFFSET(T0, -4), (uint8_t)(T1 >> 32));

    if (GET_LMASK64(T0) >= 5)

        stfun(GET_OFFSET(T0, -5), (uint8_t)(T1 >> 40));

    if (GET_LMASK64(T0) >= 6)

        stfun(GET_OFFSET(T0, -6), (uint8_t)(T1 >> 48));

    if (GET_LMASK64(T0) == 7)

        stfun(GET_OFFSET(T0, -7), (uint8_t)(T1 >> 56));

}

#endif /* TARGET_MIPS64 */

#ifdef CONFIG_USER_ONLY

void do_mfc0_random (void)

{

    cpu_abort(env, "mfc0 random\n");

}

void do_mfc0_count (void)

{

    cpu_abort(env, "mfc0 count\n");

}

void cpu_mips_store_count(CPUState *env, uint32_t value)

{

    cpu_abort(env, "mtc0 count\n");

}

void cpu_mips_store_compare(CPUState *env, uint32_t value)

{

    cpu_abort(env, "mtc0 compare\n");

}

void cpu_mips_start_count(CPUState *env)

{

    cpu_abort(env, "start count\n");

}

void cpu_mips_stop_count(CPUState *env)

{

    cpu_abort(env, "stop count\n");

}

void cpu_mips_update_irq(CPUState *env)

{

    cpu_abort(env, "mtc0 status / mtc0 cause\n");

}

void do_mtc0_status_debug(uint32_t old, uint32_t val)

{

    cpu_abort(env, "mtc0 status debug\n");

}

void do_mtc0_status_irqraise_debug (void)

{

    cpu_abort(env, "mtc0 status irqraise debug\n");

}

void cpu_mips_tlb_flush (CPUState *env, int flush_global)

{

    cpu_abort(env, "mips_tlb_flush\n");

}

#else

/* CP0 helpers */

void do_mfc0_mvpcontrol (void)

{

    T0 = env->mvp->CP0_MVPControl;

}

void do_mfc0_mvpconf0 (void)

{

    T0 = env->mvp->CP0_MVPConf0;

}

void do_mfc0_mvpconf1 (void)

{

    T0 = env->mvp->CP0_MVPConf1;

}

void do_mfc0_random (void)

{

    T0 = (int32_t)cpu_mips_get_random(env);

}

void do_mfc0_tcstatus (void)

{

    T0 = env->CP0_TCStatus[env->current_tc];

}

void do_mftc0_tcstatus(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCStatus[other_tc];

}

void do_mfc0_tcbind (void)

{

    T0 = env->CP0_TCBind[env->current_tc];

}

void do_mftc0_tcbind(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCBind[other_tc];

}

void do_mfc0_tcrestart (void)

{

    T0 = env->PC[env->current_tc];

}

void do_mftc0_tcrestart(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->PC[other_tc];

}

void do_mfc0_tchalt (void)

{

    T0 = env->CP0_TCHalt[env->current_tc];

}

void do_mftc0_tchalt(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCHalt[other_tc];

}

void do_mfc0_tccontext (void)

{

    T0 = env->CP0_TCContext[env->current_tc];

}

void do_mftc0_tccontext(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCContext[other_tc];

}

void do_mfc0_tcschedule (void)

{

    T0 = env->CP0_TCSchedule[env->current_tc];

}

void do_mftc0_tcschedule(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCSchedule[other_tc];

}

void do_mfc0_tcschefback (void)

{

    T0 = env->CP0_TCScheFBack[env->current_tc];

}

void do_mftc0_tcschefback(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = env->CP0_TCScheFBack[other_tc];

}

void do_mfc0_count (void)

{

    T0 = (int32_t)cpu_mips_get_count(env);

}

void do_mftc0_entryhi(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);

}

void do_mftc0_status(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    uint32_t tcstatus = env->CP0_TCStatus[other_tc];

    T0 = env->CP0_Status & ~0xf1000018;

    T0 |= tcstatus & (0xf << CP0TCSt_TCU0);

    T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);

    T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);

}

void do_mfc0_lladdr (void)

{

    T0 = (int32_t)env->CP0_LLAddr >> 4;

}

void do_mfc0_watchlo (uint32_t sel)

{

    T0 = (int32_t)env->CP0_WatchLo[sel];

}

void do_mfc0_watchhi (uint32_t sel)

{

    T0 = env->CP0_WatchHi[sel];

}

void do_mfc0_debug (void)

{

    T0 = env->CP0_Debug;

    if (env->hflags & MIPS_HFLAG_DM)

        T0 |= 1 << CP0DB_DM;

}

void do_mftc0_debug(void)

{

    int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);

    /* XXX: Might be wrong, check with EJTAG spec. */

    T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |

         (env->CP0_Debug_tcstatus[other_tc] &

          ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));

}

#if defined(TARGET_MIPS64)

void do_dmfc0_tcrestart (void)

{

    T0 = env->PC[env->current_tc];

}

void do_dmfc0_tchalt (void)

{

    T0 = env->CP0_TCHalt[env->current_tc];

}

void do_dmfc0_tccontext (void)

{

    T0 = env->CP0_TCContext[env->current_tc];

}

void do_dmfc0_tcschedule (void)

{

    T0 = env->CP0_TCSchedule[env->current_tc];

}

void do_dmfc0_tcschefback (void)

{

    T0 = env->CP0_TCScheFBack[env->current_tc];

}

void do_dmfc0_lladdr (void)

{

    T0 = env->CP0_LLAddr >> 4;

}

void do_dmfc0_watchlo (uint32_t sel)

{

    T0 = env->CP0_WatchLo[sel];

}

#endif /* TARGET_MIPS64 */

void do_mtc0_index (void)

{

    int num = 1;

    unsigned int tmp = env->tlb->nb_tlb;