Revision b6dcbe08
| b/hw/ppc405.h | ||
|---|---|---|
| 59 | 59 |
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, |
| 60 | 60 |
uint32_t flags); |
| 61 | 61 |
|
| 62 |
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], |
|
| 62 |
CPUState *ppc405cr_init (MemoryRegion ram_memories[4], |
|
| 63 |
target_phys_addr_t ram_bases[4], |
|
| 63 | 64 |
target_phys_addr_t ram_sizes[4], |
| 64 | 65 |
uint32_t sysclk, qemu_irq **picp, |
| 65 | 66 |
int do_init); |
| 66 |
CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], |
|
| 67 |
CPUState *ppc405ep_init (MemoryRegion ram_memories[2], |
|
| 68 |
target_phys_addr_t ram_bases[2], |
|
| 67 | 69 |
target_phys_addr_t ram_sizes[2], |
| 68 | 70 |
uint32_t sysclk, qemu_irq **picp, |
| 69 | 71 |
int do_init); |
| 70 | 72 |
/* IBM STBxxx microcontrollers */ |
| 71 |
CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2], |
|
| 73 |
CPUState *ppc_stb025_init (MemoryRegion ram_memories[2], |
|
| 74 |
target_phys_addr_t ram_bases[2], |
|
| 72 | 75 |
target_phys_addr_t ram_sizes[2], |
| 73 | 76 |
uint32_t sysclk, qemu_irq **picp, |
| 74 | 77 |
ram_addr_t *offsetp); |
| b/hw/ppc405_boards.c | ||
|---|---|---|
| 182 | 182 |
CPUPPCState *env; |
| 183 | 183 |
qemu_irq *pic; |
| 184 | 184 |
ram_addr_t sram_offset, bios_offset, bdloc; |
| 185 |
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); |
|
| 185 | 186 |
target_phys_addr_t ram_bases[2], ram_sizes[2]; |
| 186 | 187 |
target_ulong sram_size; |
| 187 | 188 |
long bios_size; |
| ... | ... | |
| 194 | 195 |
DriveInfo *dinfo; |
| 195 | 196 |
|
| 196 | 197 |
/* XXX: fix this */ |
| 197 |
ram_bases[0] = qemu_ram_alloc(NULL, "ef405ep.ram", 0x08000000); |
|
| 198 |
memory_region_init_ram(&ram_memories[0], NULL, "ef405ep.ram", 0x08000000); |
|
| 199 |
ram_bases[0] = 0; |
|
| 198 | 200 |
ram_sizes[0] = 0x08000000; |
| 201 |
memory_region_init(&ram_memories[1], "ef405ep.ram1", 0); |
|
| 199 | 202 |
ram_bases[1] = 0x00000000; |
| 200 | 203 |
ram_sizes[1] = 0x00000000; |
| 201 | 204 |
ram_size = 128 * 1024 * 1024; |
| 202 | 205 |
#ifdef DEBUG_BOARD_INIT |
| 203 | 206 |
printf("%s: register cpu\n", __func__);
|
| 204 | 207 |
#endif |
| 205 |
env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, |
|
| 208 |
env = ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
|
|
| 206 | 209 |
kernel_filename == NULL ? 0 : 1); |
| 207 | 210 |
/* allocate SRAM */ |
| 208 | 211 |
sram_size = 512 * 1024; |
| ... | ... | |
| 505 | 508 |
char *filename; |
| 506 | 509 |
qemu_irq *pic; |
| 507 | 510 |
ram_addr_t bios_offset; |
| 511 |
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); |
|
| 508 | 512 |
target_phys_addr_t ram_bases[2], ram_sizes[2]; |
| 509 | 513 |
long bios_size; |
| 510 | 514 |
target_ulong kernel_base, initrd_base; |
| ... | ... | |
| 514 | 518 |
DriveInfo *dinfo; |
| 515 | 519 |
|
| 516 | 520 |
/* RAM is soldered to the board so the size cannot be changed */ |
| 517 |
ram_bases[0] = qemu_ram_alloc(NULL, "taihu_405ep.ram-0", 0x04000000); |
|
| 521 |
memory_region_init_ram(&ram_memories[0], NULL, |
|
| 522 |
"taihu_405ep.ram-0", 0x04000000); |
|
| 523 |
ram_bases[0] = 0; |
|
| 518 | 524 |
ram_sizes[0] = 0x04000000; |
| 519 |
ram_bases[1] = qemu_ram_alloc(NULL, "taihu_405ep.ram-1", 0x04000000); |
|
| 525 |
memory_region_init_ram(&ram_memories[1], NULL, |
|
| 526 |
"taihu_405ep.ram-1", 0x04000000); |
|
| 527 |
ram_bases[1] = 0x04000000; |
|
| 520 | 528 |
ram_sizes[1] = 0x04000000; |
| 521 | 529 |
ram_size = 0x08000000; |
| 522 | 530 |
#ifdef DEBUG_BOARD_INIT |
| 523 | 531 |
printf("%s: register cpu\n", __func__);
|
| 524 | 532 |
#endif |
| 525 |
ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, |
|
| 533 |
ppc405ep_init(ram_memories, ram_bases, ram_sizes, 33333333, &pic,
|
|
| 526 | 534 |
kernel_filename == NULL ? 0 : 1); |
| 527 | 535 |
/* allocate and load BIOS */ |
| 528 | 536 |
#ifdef DEBUG_BOARD_INIT |
| b/hw/ppc405_uc.c | ||
|---|---|---|
| 2107 | 2107 |
qemu_register_reset(ppc405cr_cpc_reset, cpc); |
| 2108 | 2108 |
} |
| 2109 | 2109 |
|
| 2110 |
CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], |
|
| 2110 |
CPUState *ppc405cr_init (MemoryRegion ram_memories[4], |
|
| 2111 |
target_phys_addr_t ram_bases[4], |
|
| 2111 | 2112 |
target_phys_addr_t ram_sizes[4], |
| 2112 | 2113 |
uint32_t sysclk, qemu_irq **picp, |
| 2113 | 2114 |
int do_init) |
| ... | ... | |
| 2136 | 2137 |
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
| 2137 | 2138 |
*picp = pic; |
| 2138 | 2139 |
/* SDRAM controller */ |
| 2139 |
ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); |
|
| 2140 |
ppc4xx_sdram_init(env, pic[14], 1, ram_memories, |
|
| 2141 |
ram_bases, ram_sizes, do_init); |
|
| 2140 | 2142 |
/* External bus controller */ |
| 2141 | 2143 |
ppc405_ebc_init(env); |
| 2142 | 2144 |
/* DMA controller */ |
| ... | ... | |
| 2451 | 2453 |
#endif |
| 2452 | 2454 |
} |
| 2453 | 2455 |
|
| 2454 |
CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], |
|
| 2456 |
CPUState *ppc405ep_init (MemoryRegion ram_memories[2], |
|
| 2457 |
target_phys_addr_t ram_bases[2], |
|
| 2455 | 2458 |
target_phys_addr_t ram_sizes[2], |
| 2456 | 2459 |
uint32_t sysclk, qemu_irq **picp, |
| 2457 | 2460 |
int do_init) |
| ... | ... | |
| 2485 | 2488 |
*picp = pic; |
| 2486 | 2489 |
/* SDRAM controller */ |
| 2487 | 2490 |
/* XXX 405EP has no ECC interrupt */ |
| 2488 |
ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); |
|
| 2491 |
ppc4xx_sdram_init(env, pic[17], 2, ram_memories, |
|
| 2492 |
ram_bases, ram_sizes, do_init); |
|
| 2489 | 2493 |
/* External bus controller */ |
| 2490 | 2494 |
ppc405_ebc_init(env); |
| 2491 | 2495 |
/* DMA controller */ |
| b/hw/ppc440.c | ||
|---|---|---|
| 38 | 38 |
const unsigned int pci_irq_nrs[4], int do_init, |
| 39 | 39 |
const char *cpu_model) |
| 40 | 40 |
{
|
| 41 |
MemoryRegion *ram_memories |
|
| 42 |
= g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories)); |
|
| 41 | 43 |
target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS]; |
| 42 | 44 |
target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS]; |
| 43 | 45 |
CPUState *env; |
| ... | ... | |
| 66 | 68 |
memset(ram_bases, 0, sizeof(ram_bases)); |
| 67 | 69 |
memset(ram_sizes, 0, sizeof(ram_sizes)); |
| 68 | 70 |
*ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS, |
| 71 |
ram_memories, |
|
| 69 | 72 |
ram_bases, ram_sizes, |
| 70 | 73 |
ppc440ep_sdram_bank_sizes); |
| 71 | 74 |
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ |
| 72 |
ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_bases,
|
|
| 73 |
ram_sizes, do_init); |
|
| 75 |
ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
|
|
| 76 |
ram_bases, ram_sizes, do_init);
|
|
| 74 | 77 |
|
| 75 | 78 |
/* PCI */ |
| 76 | 79 |
pci_irqs = g_malloc(sizeof(qemu_irq) * 4); |
| b/hw/ppc4xx.h | ||
|---|---|---|
| 42 | 42 |
uint32_t dcr_base, int has_ssr, int has_vr); |
| 43 | 43 |
|
| 44 | 44 |
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, |
| 45 |
MemoryRegion ram_memories[], |
|
| 45 | 46 |
target_phys_addr_t ram_bases[], |
| 46 | 47 |
target_phys_addr_t ram_sizes[], |
| 47 | 48 |
const unsigned int sdram_bank_sizes[]); |
| 48 | 49 |
|
| 49 | 50 |
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
| 51 |
MemoryRegion ram_memories[], |
|
| 50 | 52 |
target_phys_addr_t *ram_bases, |
| 51 | 53 |
target_phys_addr_t *ram_sizes, |
| 52 | 54 |
int do_init); |
| b/hw/ppc4xx_devs.c | ||
|---|---|---|
| 25 | 25 |
#include "ppc.h" |
| 26 | 26 |
#include "ppc4xx.h" |
| 27 | 27 |
#include "qemu-log.h" |
| 28 |
#include "exec-memory.h" |
|
| 28 | 29 |
|
| 29 | 30 |
//#define DEBUG_MMIO |
| 30 | 31 |
//#define DEBUG_UNASSIGNED |
| ... | ... | |
| 313 | 314 |
struct ppc4xx_sdram_t {
|
| 314 | 315 |
uint32_t addr; |
| 315 | 316 |
int nbanks; |
| 317 |
MemoryRegion containers[4]; /* used for clipping */ |
|
| 318 |
MemoryRegion *ram_memories; |
|
| 316 | 319 |
target_phys_addr_t ram_bases[4]; |
| 317 | 320 |
target_phys_addr_t ram_sizes[4]; |
| 318 | 321 |
uint32_t besr0; |
| ... | ... | |
| 395 | 398 |
return size; |
| 396 | 399 |
} |
| 397 | 400 |
|
| 398 |
static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) |
|
| 401 |
static void sdram_set_bcr(ppc4xx_sdram_t *sdram, |
|
| 402 |
uint32_t *bcrp, uint32_t bcr, int enabled) |
|
| 399 | 403 |
{
|
| 404 |
unsigned n = bcrp - sdram->bcr; |
|
| 405 |
|
|
| 400 | 406 |
if (*bcrp & 0x00000001) {
|
| 401 | 407 |
/* Unmap RAM */ |
| 402 | 408 |
#ifdef DEBUG_SDRAM |
| 403 | 409 |
printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
|
| 404 | 410 |
__func__, sdram_base(*bcrp), sdram_size(*bcrp)); |
| 405 | 411 |
#endif |
| 406 |
cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp), |
|
| 407 |
IO_MEM_UNASSIGNED); |
|
| 412 |
memory_region_del_subregion(get_system_memory(), |
|
| 413 |
&sdram->containers[n]); |
|
| 414 |
memory_region_del_subregion(&sdram->containers[n], |
|
| 415 |
&sdram->ram_memories[n]); |
|
| 416 |
memory_region_destroy(&sdram->containers[n]); |
|
| 408 | 417 |
} |
| 409 | 418 |
*bcrp = bcr & 0xFFDEE001; |
| 410 | 419 |
if (enabled && (bcr & 0x00000001)) {
|
| ... | ... | |
| 412 | 421 |
printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
|
| 413 | 422 |
__func__, sdram_base(bcr), sdram_size(bcr)); |
| 414 | 423 |
#endif |
| 415 |
cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), |
|
| 416 |
sdram_base(bcr) | IO_MEM_RAM); |
|
| 424 |
memory_region_init(&sdram->containers[n], "sdram-containers", |
|
| 425 |
sdram_size(bcr)); |
|
| 426 |
memory_region_add_subregion(&sdram->containers[n], 0, |
|
| 427 |
&sdram->ram_memories[n]); |
|
| 428 |
memory_region_add_subregion(get_system_memory(), |
|
| 429 |
sdram_base(bcr), |
|
| 430 |
&sdram->containers[n]); |
|
| 417 | 431 |
} |
| 418 | 432 |
} |
| 419 | 433 |
|
| ... | ... | |
| 423 | 437 |
|
| 424 | 438 |
for (i = 0; i < sdram->nbanks; i++) {
|
| 425 | 439 |
if (sdram->ram_sizes[i] != 0) {
|
| 426 |
sdram_set_bcr(&sdram->bcr[i], |
|
| 440 |
sdram_set_bcr(sdram, |
|
| 441 |
&sdram->bcr[i], |
|
| 427 | 442 |
sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), |
| 428 | 443 |
1); |
| 429 | 444 |
} else {
|
| 430 |
sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0); |
|
| 445 |
sdram_set_bcr(sdram, &sdram->bcr[i], 0x00000000, 0);
|
|
| 431 | 446 |
} |
| 432 | 447 |
} |
| 433 | 448 |
} |
| ... | ... | |
| 441 | 456 |
printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
|
| 442 | 457 |
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); |
| 443 | 458 |
#endif |
| 444 |
cpu_register_physical_memory(sdram_base(sdram->bcr[i]), |
|
| 445 |
sdram_size(sdram->bcr[i]), |
|
| 446 |
IO_MEM_UNASSIGNED); |
|
| 459 |
memory_region_del_subregion(get_system_memory(), |
|
| 460 |
&sdram->ram_memories[i]); |
|
| 447 | 461 |
} |
| 448 | 462 |
} |
| 449 | 463 |
|
| ... | ... | |
| 568 | 582 |
sdram->pmit = (val & 0xF8000000) | 0x07C00000; |
| 569 | 583 |
break; |
| 570 | 584 |
case 0x40: /* SDRAM_B0CR */ |
| 571 |
sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000); |
|
| 585 |
sdram_set_bcr(sdram, &sdram->bcr[0], val, sdram->cfg & 0x80000000);
|
|
| 572 | 586 |
break; |
| 573 | 587 |
case 0x44: /* SDRAM_B1CR */ |
| 574 |
sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000); |
|
| 588 |
sdram_set_bcr(sdram, &sdram->bcr[1], val, sdram->cfg & 0x80000000);
|
|
| 575 | 589 |
break; |
| 576 | 590 |
case 0x48: /* SDRAM_B2CR */ |
| 577 |
sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000); |
|
| 591 |
sdram_set_bcr(sdram, &sdram->bcr[2], val, sdram->cfg & 0x80000000);
|
|
| 578 | 592 |
break; |
| 579 | 593 |
case 0x4C: /* SDRAM_B3CR */ |
| 580 |
sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000); |
|
| 594 |
sdram_set_bcr(sdram, &sdram->bcr[3], val, sdram->cfg & 0x80000000);
|
|
| 581 | 595 |
break; |
| 582 | 596 |
case 0x80: /* SDRAM_TR */ |
| 583 | 597 |
sdram->tr = val & 0x018FC01F; |
| ... | ... | |
| 621 | 635 |
} |
| 622 | 636 |
|
| 623 | 637 |
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
| 638 |
MemoryRegion *ram_memories, |
|
| 624 | 639 |
target_phys_addr_t *ram_bases, |
| 625 | 640 |
target_phys_addr_t *ram_sizes, |
| 626 | 641 |
int do_init) |
| ... | ... | |
| 630 | 645 |
sdram = g_malloc0(sizeof(ppc4xx_sdram_t)); |
| 631 | 646 |
sdram->irq = irq; |
| 632 | 647 |
sdram->nbanks = nbanks; |
| 648 |
sdram->ram_memories = ram_memories; |
|
| 633 | 649 |
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); |
| 634 | 650 |
memcpy(sdram->ram_bases, ram_bases, |
| 635 | 651 |
nbanks * sizeof(target_phys_addr_t)); |
| ... | ... | |
| 653 | 669 |
* must be one of a small set of sizes. The number of banks and the supported |
| 654 | 670 |
* sizes varies by SoC. */ |
| 655 | 671 |
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, |
| 672 |
MemoryRegion ram_memories[], |
|
| 656 | 673 |
target_phys_addr_t ram_bases[], |
| 657 | 674 |
target_phys_addr_t ram_sizes[], |
| 658 | 675 |
const unsigned int sdram_bank_sizes[]) |
| 659 | 676 |
{
|
| 660 | 677 |
ram_addr_t size_left = ram_size; |
| 678 |
ram_addr_t base = 0; |
|
| 661 | 679 |
int i; |
| 662 | 680 |
int j; |
| 663 | 681 |
|
| ... | ... | |
| 668 | 686 |
if (bank_size <= size_left) {
|
| 669 | 687 |
char name[32]; |
| 670 | 688 |
snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); |
| 671 |
ram_bases[i] = qemu_ram_alloc(NULL, name, bank_size); |
|
| 689 |
memory_region_init_ram(&ram_memories[i], NULL, name, bank_size); |
|
| 690 |
ram_bases[i] = base; |
|
| 672 | 691 |
ram_sizes[i] = bank_size; |
| 692 |
base += ram_size; |
|
| 673 | 693 |
size_left -= bank_size; |
| 674 | 694 |
break; |
| 675 | 695 |
} |
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