root / tcg / i386 / tcg-target.c @ b70650cb
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1 | c896fe29 | bellard | /*
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2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
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3 | c896fe29 | bellard | *
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4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
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5 | c896fe29 | bellard | *
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6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
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9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
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12 | c896fe29 | bellard | *
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13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
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15 | c896fe29 | bellard | *
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16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | c896fe29 | bellard | * THE SOFTWARE.
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23 | c896fe29 | bellard | */
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24 | d4a9eb1f | blueswir1 | |
25 | d4a9eb1f | blueswir1 | #ifndef NDEBUG
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26 | d4a9eb1f | blueswir1 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
27 | c896fe29 | bellard | "%eax",
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28 | c896fe29 | bellard | "%ecx",
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29 | c896fe29 | bellard | "%edx",
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30 | c896fe29 | bellard | "%ebx",
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31 | c896fe29 | bellard | "%esp",
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32 | c896fe29 | bellard | "%ebp",
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33 | c896fe29 | bellard | "%esi",
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34 | c896fe29 | bellard | "%edi",
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35 | c896fe29 | bellard | }; |
36 | d4a9eb1f | blueswir1 | #endif
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37 | c896fe29 | bellard | |
38 | d4a9eb1f | blueswir1 | static const int tcg_target_reg_alloc_order[] = { |
39 | c896fe29 | bellard | TCG_REG_EAX, |
40 | c896fe29 | bellard | TCG_REG_EDX, |
41 | c896fe29 | bellard | TCG_REG_ECX, |
42 | c896fe29 | bellard | TCG_REG_EBX, |
43 | c896fe29 | bellard | TCG_REG_ESI, |
44 | c896fe29 | bellard | TCG_REG_EDI, |
45 | c896fe29 | bellard | TCG_REG_EBP, |
46 | c896fe29 | bellard | }; |
47 | c896fe29 | bellard | |
48 | d4a9eb1f | blueswir1 | static const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX }; |
49 | d4a9eb1f | blueswir1 | static const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX }; |
50 | c896fe29 | bellard | |
51 | b03cce8e | bellard | static uint8_t *tb_ret_addr;
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52 | b03cce8e | bellard | |
53 | c896fe29 | bellard | static void patch_reloc(uint8_t *code_ptr, int type, |
54 | f54b3f92 | aurel32 | tcg_target_long value, tcg_target_long addend) |
55 | c896fe29 | bellard | { |
56 | f54b3f92 | aurel32 | value += addend; |
57 | c896fe29 | bellard | switch(type) {
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58 | c896fe29 | bellard | case R_386_32:
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59 | c896fe29 | bellard | *(uint32_t *)code_ptr = value; |
60 | c896fe29 | bellard | break;
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61 | c896fe29 | bellard | case R_386_PC32:
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62 | c896fe29 | bellard | *(uint32_t *)code_ptr = value - (long)code_ptr;
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63 | c896fe29 | bellard | break;
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64 | c896fe29 | bellard | default:
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65 | c896fe29 | bellard | tcg_abort(); |
66 | c896fe29 | bellard | } |
67 | c896fe29 | bellard | } |
68 | c896fe29 | bellard | |
69 | c896fe29 | bellard | /* maximum number of register used for input function arguments */
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70 | c896fe29 | bellard | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
71 | c896fe29 | bellard | { |
72 | c896fe29 | bellard | flags &= TCG_CALL_TYPE_MASK; |
73 | c896fe29 | bellard | switch(flags) {
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74 | c896fe29 | bellard | case TCG_CALL_TYPE_STD:
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75 | c896fe29 | bellard | return 0; |
76 | c896fe29 | bellard | case TCG_CALL_TYPE_REGPARM_1:
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77 | c896fe29 | bellard | case TCG_CALL_TYPE_REGPARM_2:
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78 | c896fe29 | bellard | case TCG_CALL_TYPE_REGPARM:
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79 | c896fe29 | bellard | return flags - TCG_CALL_TYPE_REGPARM_1 + 1; |
80 | c896fe29 | bellard | default:
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81 | c896fe29 | bellard | tcg_abort(); |
82 | c896fe29 | bellard | } |
83 | c896fe29 | bellard | } |
84 | c896fe29 | bellard | |
85 | c896fe29 | bellard | /* parse target specific constraints */
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86 | d4a9eb1f | blueswir1 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
87 | c896fe29 | bellard | { |
88 | c896fe29 | bellard | const char *ct_str; |
89 | c896fe29 | bellard | |
90 | c896fe29 | bellard | ct_str = *pct_str; |
91 | c896fe29 | bellard | switch(ct_str[0]) { |
92 | c896fe29 | bellard | case 'a': |
93 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
94 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX); |
95 | c896fe29 | bellard | break;
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96 | c896fe29 | bellard | case 'b': |
97 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
98 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX); |
99 | c896fe29 | bellard | break;
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100 | c896fe29 | bellard | case 'c': |
101 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
102 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX); |
103 | c896fe29 | bellard | break;
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104 | c896fe29 | bellard | case 'd': |
105 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
106 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX); |
107 | c896fe29 | bellard | break;
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108 | c896fe29 | bellard | case 'S': |
109 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
110 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI); |
111 | c896fe29 | bellard | break;
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112 | c896fe29 | bellard | case 'D': |
113 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
114 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI); |
115 | c896fe29 | bellard | break;
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116 | c896fe29 | bellard | case 'q': |
117 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
118 | c896fe29 | bellard | tcg_regset_set32(ct->u.regs, 0, 0xf); |
119 | c896fe29 | bellard | break;
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120 | c896fe29 | bellard | case 'r': |
121 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
122 | c896fe29 | bellard | tcg_regset_set32(ct->u.regs, 0, 0xff); |
123 | c896fe29 | bellard | break;
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124 | c896fe29 | bellard | |
125 | c896fe29 | bellard | /* qemu_ld/st address constraint */
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126 | c896fe29 | bellard | case 'L': |
127 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
128 | c896fe29 | bellard | tcg_regset_set32(ct->u.regs, 0, 0xff); |
129 | c896fe29 | bellard | tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX); |
130 | c896fe29 | bellard | tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX); |
131 | c896fe29 | bellard | break;
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132 | c896fe29 | bellard | default:
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133 | c896fe29 | bellard | return -1; |
134 | c896fe29 | bellard | } |
135 | c896fe29 | bellard | ct_str++; |
136 | c896fe29 | bellard | *pct_str = ct_str; |
137 | c896fe29 | bellard | return 0; |
138 | c896fe29 | bellard | } |
139 | c896fe29 | bellard | |
140 | c896fe29 | bellard | /* test if a constant matches the constraint */
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141 | c896fe29 | bellard | static inline int tcg_target_const_match(tcg_target_long val, |
142 | c896fe29 | bellard | const TCGArgConstraint *arg_ct)
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143 | c896fe29 | bellard | { |
144 | c896fe29 | bellard | int ct;
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145 | c896fe29 | bellard | ct = arg_ct->ct; |
146 | c896fe29 | bellard | if (ct & TCG_CT_CONST)
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147 | c896fe29 | bellard | return 1; |
148 | c896fe29 | bellard | else
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149 | c896fe29 | bellard | return 0; |
150 | c896fe29 | bellard | } |
151 | c896fe29 | bellard | |
152 | c896fe29 | bellard | #define ARITH_ADD 0 |
153 | c896fe29 | bellard | #define ARITH_OR 1 |
154 | c896fe29 | bellard | #define ARITH_ADC 2 |
155 | c896fe29 | bellard | #define ARITH_SBB 3 |
156 | c896fe29 | bellard | #define ARITH_AND 4 |
157 | c896fe29 | bellard | #define ARITH_SUB 5 |
158 | c896fe29 | bellard | #define ARITH_XOR 6 |
159 | c896fe29 | bellard | #define ARITH_CMP 7 |
160 | c896fe29 | bellard | |
161 | 9619376c | aurel32 | #define SHIFT_ROL 0 |
162 | 9619376c | aurel32 | #define SHIFT_ROR 1 |
163 | c896fe29 | bellard | #define SHIFT_SHL 4 |
164 | c896fe29 | bellard | #define SHIFT_SHR 5 |
165 | c896fe29 | bellard | #define SHIFT_SAR 7 |
166 | c896fe29 | bellard | |
167 | c896fe29 | bellard | #define JCC_JMP (-1) |
168 | c896fe29 | bellard | #define JCC_JO 0x0 |
169 | c896fe29 | bellard | #define JCC_JNO 0x1 |
170 | c896fe29 | bellard | #define JCC_JB 0x2 |
171 | c896fe29 | bellard | #define JCC_JAE 0x3 |
172 | c896fe29 | bellard | #define JCC_JE 0x4 |
173 | c896fe29 | bellard | #define JCC_JNE 0x5 |
174 | c896fe29 | bellard | #define JCC_JBE 0x6 |
175 | c896fe29 | bellard | #define JCC_JA 0x7 |
176 | c896fe29 | bellard | #define JCC_JS 0x8 |
177 | c896fe29 | bellard | #define JCC_JNS 0x9 |
178 | c896fe29 | bellard | #define JCC_JP 0xa |
179 | c896fe29 | bellard | #define JCC_JNP 0xb |
180 | c896fe29 | bellard | #define JCC_JL 0xc |
181 | c896fe29 | bellard | #define JCC_JGE 0xd |
182 | c896fe29 | bellard | #define JCC_JLE 0xe |
183 | c896fe29 | bellard | #define JCC_JG 0xf |
184 | c896fe29 | bellard | |
185 | c896fe29 | bellard | #define P_EXT 0x100 /* 0x0f opcode prefix */ |
186 | c896fe29 | bellard | |
187 | c896fe29 | bellard | static const uint8_t tcg_cond_to_jcc[10] = { |
188 | c896fe29 | bellard | [TCG_COND_EQ] = JCC_JE, |
189 | c896fe29 | bellard | [TCG_COND_NE] = JCC_JNE, |
190 | c896fe29 | bellard | [TCG_COND_LT] = JCC_JL, |
191 | c896fe29 | bellard | [TCG_COND_GE] = JCC_JGE, |
192 | c896fe29 | bellard | [TCG_COND_LE] = JCC_JLE, |
193 | c896fe29 | bellard | [TCG_COND_GT] = JCC_JG, |
194 | c896fe29 | bellard | [TCG_COND_LTU] = JCC_JB, |
195 | c896fe29 | bellard | [TCG_COND_GEU] = JCC_JAE, |
196 | c896fe29 | bellard | [TCG_COND_LEU] = JCC_JBE, |
197 | c896fe29 | bellard | [TCG_COND_GTU] = JCC_JA, |
198 | c896fe29 | bellard | }; |
199 | c896fe29 | bellard | |
200 | c896fe29 | bellard | static inline void tcg_out_opc(TCGContext *s, int opc) |
201 | c896fe29 | bellard | { |
202 | c896fe29 | bellard | if (opc & P_EXT)
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203 | c896fe29 | bellard | tcg_out8(s, 0x0f);
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204 | c896fe29 | bellard | tcg_out8(s, opc); |
205 | c896fe29 | bellard | } |
206 | c896fe29 | bellard | |
207 | c896fe29 | bellard | static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) |
208 | c896fe29 | bellard | { |
209 | c896fe29 | bellard | tcg_out_opc(s, opc); |
210 | c896fe29 | bellard | tcg_out8(s, 0xc0 | (r << 3) | rm); |
211 | c896fe29 | bellard | } |
212 | c896fe29 | bellard | |
213 | c896fe29 | bellard | /* rm == -1 means no register index */
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214 | c896fe29 | bellard | static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, |
215 | c896fe29 | bellard | int32_t offset) |
216 | c896fe29 | bellard | { |
217 | c896fe29 | bellard | tcg_out_opc(s, opc); |
218 | c896fe29 | bellard | if (rm == -1) { |
219 | c896fe29 | bellard | tcg_out8(s, 0x05 | (r << 3)); |
220 | c896fe29 | bellard | tcg_out32(s, offset); |
221 | c896fe29 | bellard | } else if (offset == 0 && rm != TCG_REG_EBP) { |
222 | c896fe29 | bellard | if (rm == TCG_REG_ESP) {
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223 | c896fe29 | bellard | tcg_out8(s, 0x04 | (r << 3)); |
224 | c896fe29 | bellard | tcg_out8(s, 0x24);
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225 | c896fe29 | bellard | } else {
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226 | c896fe29 | bellard | tcg_out8(s, 0x00 | (r << 3) | rm); |
227 | c896fe29 | bellard | } |
228 | c896fe29 | bellard | } else if ((int8_t)offset == offset) { |
229 | c896fe29 | bellard | if (rm == TCG_REG_ESP) {
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230 | c896fe29 | bellard | tcg_out8(s, 0x44 | (r << 3)); |
231 | c896fe29 | bellard | tcg_out8(s, 0x24);
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232 | c896fe29 | bellard | } else {
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233 | c896fe29 | bellard | tcg_out8(s, 0x40 | (r << 3) | rm); |
234 | c896fe29 | bellard | } |
235 | c896fe29 | bellard | tcg_out8(s, offset); |
236 | c896fe29 | bellard | } else {
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237 | c896fe29 | bellard | if (rm == TCG_REG_ESP) {
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238 | c896fe29 | bellard | tcg_out8(s, 0x84 | (r << 3)); |
239 | c896fe29 | bellard | tcg_out8(s, 0x24);
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240 | c896fe29 | bellard | } else {
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241 | c896fe29 | bellard | tcg_out8(s, 0x80 | (r << 3) | rm); |
242 | c896fe29 | bellard | } |
243 | c896fe29 | bellard | tcg_out32(s, offset); |
244 | c896fe29 | bellard | } |
245 | c896fe29 | bellard | } |
246 | c896fe29 | bellard | |
247 | c896fe29 | bellard | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
248 | c896fe29 | bellard | { |
249 | c896fe29 | bellard | if (arg != ret)
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250 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, ret, arg);
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251 | c896fe29 | bellard | } |
252 | c896fe29 | bellard | |
253 | c896fe29 | bellard | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
254 | c896fe29 | bellard | int ret, int32_t arg)
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255 | c896fe29 | bellard | { |
256 | c896fe29 | bellard | if (arg == 0) { |
257 | c896fe29 | bellard | /* xor r0,r0 */
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258 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); |
259 | c896fe29 | bellard | } else {
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260 | c896fe29 | bellard | tcg_out8(s, 0xb8 + ret);
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261 | c896fe29 | bellard | tcg_out32(s, arg); |
262 | c896fe29 | bellard | } |
263 | c896fe29 | bellard | } |
264 | c896fe29 | bellard | |
265 | e4d5434c | blueswir1 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
266 | e4d5434c | blueswir1 | int arg1, tcg_target_long arg2)
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267 | c896fe29 | bellard | { |
268 | c896fe29 | bellard | /* movl */
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269 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2);
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270 | c896fe29 | bellard | } |
271 | c896fe29 | bellard | |
272 | e4d5434c | blueswir1 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
273 | e4d5434c | blueswir1 | int arg1, tcg_target_long arg2)
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274 | c896fe29 | bellard | { |
275 | c896fe29 | bellard | /* movl */
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276 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2);
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277 | c896fe29 | bellard | } |
278 | c896fe29 | bellard | |
279 | c896fe29 | bellard | static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val) |
280 | c896fe29 | bellard | { |
281 | c896fe29 | bellard | if (val == (int8_t)val) {
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282 | c896fe29 | bellard | tcg_out_modrm(s, 0x83, c, r0);
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283 | c896fe29 | bellard | tcg_out8(s, val); |
284 | b70650cb | Aurelien Jarno | } else if (c == ARITH_AND && val == 0xffu && r0 < 4) { |
285 | b70650cb | Aurelien Jarno | /* movzbl */
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286 | b70650cb | Aurelien Jarno | tcg_out_modrm(s, 0xb6 | P_EXT, r0, r0);
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287 | b70650cb | Aurelien Jarno | } else if (c == ARITH_AND && val == 0xffffu) { |
288 | b70650cb | Aurelien Jarno | /* movzwl */
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289 | b70650cb | Aurelien Jarno | tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
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290 | c896fe29 | bellard | } else {
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291 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, c, r0);
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292 | c896fe29 | bellard | tcg_out32(s, val); |
293 | c896fe29 | bellard | } |
294 | c896fe29 | bellard | } |
295 | c896fe29 | bellard | |
296 | 3e9a474e | aurel32 | static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
297 | c896fe29 | bellard | { |
298 | c896fe29 | bellard | if (val != 0) |
299 | c896fe29 | bellard | tgen_arithi(s, ARITH_ADD, reg, val); |
300 | c896fe29 | bellard | } |
301 | c896fe29 | bellard | |
302 | c896fe29 | bellard | static void tcg_out_jxx(TCGContext *s, int opc, int label_index) |
303 | c896fe29 | bellard | { |
304 | c896fe29 | bellard | int32_t val, val1; |
305 | c896fe29 | bellard | TCGLabel *l = &s->labels[label_index]; |
306 | c896fe29 | bellard | |
307 | c896fe29 | bellard | if (l->has_value) {
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308 | c896fe29 | bellard | val = l->u.value - (tcg_target_long)s->code_ptr; |
309 | c896fe29 | bellard | val1 = val - 2;
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310 | c896fe29 | bellard | if ((int8_t)val1 == val1) {
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311 | c896fe29 | bellard | if (opc == -1) |
312 | c896fe29 | bellard | tcg_out8(s, 0xeb);
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313 | c896fe29 | bellard | else
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314 | c896fe29 | bellard | tcg_out8(s, 0x70 + opc);
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315 | c896fe29 | bellard | tcg_out8(s, val1); |
316 | c896fe29 | bellard | } else {
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317 | c896fe29 | bellard | if (opc == -1) { |
318 | c896fe29 | bellard | tcg_out8(s, 0xe9);
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319 | c896fe29 | bellard | tcg_out32(s, val - 5);
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320 | c896fe29 | bellard | } else {
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321 | c896fe29 | bellard | tcg_out8(s, 0x0f);
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322 | c896fe29 | bellard | tcg_out8(s, 0x80 + opc);
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323 | c896fe29 | bellard | tcg_out32(s, val - 6);
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324 | c896fe29 | bellard | } |
325 | c896fe29 | bellard | } |
326 | c896fe29 | bellard | } else {
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327 | c896fe29 | bellard | if (opc == -1) { |
328 | c896fe29 | bellard | tcg_out8(s, 0xe9);
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329 | c896fe29 | bellard | } else {
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330 | c896fe29 | bellard | tcg_out8(s, 0x0f);
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331 | c896fe29 | bellard | tcg_out8(s, 0x80 + opc);
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332 | c896fe29 | bellard | } |
333 | c896fe29 | bellard | tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
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334 | 623e265c | pbrook | s->code_ptr += 4;
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335 | c896fe29 | bellard | } |
336 | c896fe29 | bellard | } |
337 | c896fe29 | bellard | |
338 | c896fe29 | bellard | static void tcg_out_brcond(TCGContext *s, int cond, |
339 | c896fe29 | bellard | TCGArg arg1, TCGArg arg2, int const_arg2,
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340 | c896fe29 | bellard | int label_index)
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341 | c896fe29 | bellard | { |
342 | c896fe29 | bellard | if (const_arg2) {
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343 | c896fe29 | bellard | if (arg2 == 0) { |
344 | c896fe29 | bellard | /* test r, r */
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345 | c896fe29 | bellard | tcg_out_modrm(s, 0x85, arg1, arg1);
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346 | c896fe29 | bellard | } else {
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347 | c896fe29 | bellard | tgen_arithi(s, ARITH_CMP, arg1, arg2); |
348 | c896fe29 | bellard | } |
349 | c896fe29 | bellard | } else {
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350 | bb210e78 | bellard | tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3), arg2, arg1); |
351 | c896fe29 | bellard | } |
352 | affa3264 | bellard | tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index); |
353 | c896fe29 | bellard | } |
354 | c896fe29 | bellard | |
355 | c896fe29 | bellard | /* XXX: we implement it at the target level to avoid having to
|
356 | c896fe29 | bellard | handle cross basic blocks temporaries */
|
357 | c896fe29 | bellard | static void tcg_out_brcond2(TCGContext *s, |
358 | c896fe29 | bellard | const TCGArg *args, const int *const_args) |
359 | c896fe29 | bellard | { |
360 | c896fe29 | bellard | int label_next;
|
361 | c896fe29 | bellard | label_next = gen_new_label(); |
362 | c896fe29 | bellard | switch(args[4]) { |
363 | c896fe29 | bellard | case TCG_COND_EQ:
|
364 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next); |
365 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]); |
366 | c896fe29 | bellard | break;
|
367 | c896fe29 | bellard | case TCG_COND_NE:
|
368 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]); |
369 | bb210e78 | bellard | tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]); |
370 | c896fe29 | bellard | break;
|
371 | c896fe29 | bellard | case TCG_COND_LT:
|
372 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]); |
373 | affa3264 | bellard | tcg_out_jxx(s, JCC_JNE, label_next); |
374 | d643ccca | bellard | tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]); |
375 | c896fe29 | bellard | break;
|
376 | c896fe29 | bellard | case TCG_COND_LE:
|
377 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]); |
378 | affa3264 | bellard | tcg_out_jxx(s, JCC_JNE, label_next); |
379 | d643ccca | bellard | tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]); |
380 | c896fe29 | bellard | break;
|
381 | c896fe29 | bellard | case TCG_COND_GT:
|
382 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]); |
383 | affa3264 | bellard | tcg_out_jxx(s, JCC_JNE, label_next); |
384 | d643ccca | bellard | tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]); |
385 | c896fe29 | bellard | break;
|
386 | c896fe29 | bellard | case TCG_COND_GE:
|
387 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]); |
388 | affa3264 | bellard | tcg_out_jxx(s, JCC_JNE, label_next); |
389 | d643ccca | bellard | tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]); |
390 | c896fe29 | bellard | break;
|
391 | c896fe29 | bellard | case TCG_COND_LTU:
|
392 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]); |
393 | affa3264 | bellard | tcg_out_jxx(s, JCC_JNE, label_next); |
394 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]); |
395 | c896fe29 | bellard | break;
|
396 | c896fe29 | bellard | case TCG_COND_LEU:
|
397 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]); |
398 | affa3264 | bellard | tcg_out_jxx(s, JCC_JNE, label_next); |
399 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]); |
400 | c896fe29 | bellard | break;
|
401 | c896fe29 | bellard | case TCG_COND_GTU:
|
402 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]); |
403 | affa3264 | bellard | tcg_out_jxx(s, JCC_JNE, label_next); |
404 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]); |
405 | c896fe29 | bellard | break;
|
406 | c896fe29 | bellard | case TCG_COND_GEU:
|
407 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]); |
408 | affa3264 | bellard | tcg_out_jxx(s, JCC_JNE, label_next); |
409 | c896fe29 | bellard | tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]); |
410 | c896fe29 | bellard | break;
|
411 | c896fe29 | bellard | default:
|
412 | c896fe29 | bellard | tcg_abort(); |
413 | c896fe29 | bellard | } |
414 | c896fe29 | bellard | tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr); |
415 | c896fe29 | bellard | } |
416 | c896fe29 | bellard | |
417 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
418 | 79383c9c | blueswir1 | |
419 | 79383c9c | blueswir1 | #include "../../softmmu_defs.h" |
420 | c896fe29 | bellard | |
421 | c896fe29 | bellard | static void *qemu_ld_helpers[4] = { |
422 | c896fe29 | bellard | __ldb_mmu, |
423 | c896fe29 | bellard | __ldw_mmu, |
424 | c896fe29 | bellard | __ldl_mmu, |
425 | c896fe29 | bellard | __ldq_mmu, |
426 | c896fe29 | bellard | }; |
427 | c896fe29 | bellard | |
428 | c896fe29 | bellard | static void *qemu_st_helpers[4] = { |
429 | c896fe29 | bellard | __stb_mmu, |
430 | c896fe29 | bellard | __stw_mmu, |
431 | c896fe29 | bellard | __stl_mmu, |
432 | c896fe29 | bellard | __stq_mmu, |
433 | c896fe29 | bellard | }; |
434 | c896fe29 | bellard | #endif
|
435 | c896fe29 | bellard | |
436 | 379f6698 | Paul Brook | #ifndef CONFIG_USER_ONLY
|
437 | 379f6698 | Paul Brook | #define GUEST_BASE 0 |
438 | 379f6698 | Paul Brook | #endif
|
439 | 379f6698 | Paul Brook | |
440 | c896fe29 | bellard | /* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
|
441 | c896fe29 | bellard | EAX. It will be useful once fixed registers globals are less
|
442 | c896fe29 | bellard | common. */
|
443 | c896fe29 | bellard | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
444 | c896fe29 | bellard | int opc)
|
445 | c896fe29 | bellard | { |
446 | c896fe29 | bellard | int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
|
447 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
448 | c896fe29 | bellard | uint8_t *label1_ptr, *label2_ptr; |
449 | c896fe29 | bellard | #endif
|
450 | c896fe29 | bellard | #if TARGET_LONG_BITS == 64 |
451 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
452 | c896fe29 | bellard | uint8_t *label3_ptr; |
453 | c896fe29 | bellard | #endif
|
454 | c896fe29 | bellard | int addr_reg2;
|
455 | c896fe29 | bellard | #endif
|
456 | c896fe29 | bellard | |
457 | c896fe29 | bellard | data_reg = *args++; |
458 | c896fe29 | bellard | if (opc == 3) |
459 | c896fe29 | bellard | data_reg2 = *args++; |
460 | c896fe29 | bellard | else
|
461 | c896fe29 | bellard | data_reg2 = 0;
|
462 | c896fe29 | bellard | addr_reg = *args++; |
463 | c896fe29 | bellard | #if TARGET_LONG_BITS == 64 |
464 | c896fe29 | bellard | addr_reg2 = *args++; |
465 | c896fe29 | bellard | #endif
|
466 | c896fe29 | bellard | mem_index = *args; |
467 | c896fe29 | bellard | s_bits = opc & 3;
|
468 | c896fe29 | bellard | |
469 | c896fe29 | bellard | r0 = TCG_REG_EAX; |
470 | c896fe29 | bellard | r1 = TCG_REG_EDX; |
471 | c896fe29 | bellard | |
472 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
473 | c896fe29 | bellard | tcg_out_mov(s, r1, addr_reg); |
474 | c896fe29 | bellard | |
475 | c896fe29 | bellard | tcg_out_mov(s, r0, addr_reg); |
476 | c896fe29 | bellard | |
477 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */ |
478 | c896fe29 | bellard | tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
479 | c896fe29 | bellard | |
480 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */ |
481 | c896fe29 | bellard | tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
482 | c896fe29 | bellard | |
483 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
484 | c896fe29 | bellard | tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
485 | c896fe29 | bellard | |
486 | c896fe29 | bellard | tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */ |
487 | c896fe29 | bellard | tcg_out8(s, 0x80 | (r1 << 3) | 0x04); |
488 | c896fe29 | bellard | tcg_out8(s, (5 << 3) | r1); |
489 | c896fe29 | bellard | tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
|
490 | c896fe29 | bellard | |
491 | c896fe29 | bellard | /* cmp 0(r1), r0 */
|
492 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x3b, r0, r1, 0); |
493 | c896fe29 | bellard | |
494 | c896fe29 | bellard | tcg_out_mov(s, r0, addr_reg); |
495 | c896fe29 | bellard | |
496 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
497 | c896fe29 | bellard | /* je label1 */
|
498 | c896fe29 | bellard | tcg_out8(s, 0x70 + JCC_JE);
|
499 | c896fe29 | bellard | label1_ptr = s->code_ptr; |
500 | c896fe29 | bellard | s->code_ptr++; |
501 | c896fe29 | bellard | #else
|
502 | c896fe29 | bellard | /* jne label3 */
|
503 | c896fe29 | bellard | tcg_out8(s, 0x70 + JCC_JNE);
|
504 | c896fe29 | bellard | label3_ptr = s->code_ptr; |
505 | c896fe29 | bellard | s->code_ptr++; |
506 | c896fe29 | bellard | |
507 | c896fe29 | bellard | /* cmp 4(r1), addr_reg2 */
|
508 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4); |
509 | c896fe29 | bellard | |
510 | c896fe29 | bellard | /* je label1 */
|
511 | c896fe29 | bellard | tcg_out8(s, 0x70 + JCC_JE);
|
512 | c896fe29 | bellard | label1_ptr = s->code_ptr; |
513 | c896fe29 | bellard | s->code_ptr++; |
514 | c896fe29 | bellard | |
515 | c896fe29 | bellard | /* label3: */
|
516 | c896fe29 | bellard | *label3_ptr = s->code_ptr - label3_ptr - 1;
|
517 | c896fe29 | bellard | #endif
|
518 | c896fe29 | bellard | |
519 | c896fe29 | bellard | /* XXX: move that code at the end of the TB */
|
520 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
521 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EDX, mem_index); |
522 | c896fe29 | bellard | #else
|
523 | c896fe29 | bellard | tcg_out_mov(s, TCG_REG_EDX, addr_reg2); |
524 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index); |
525 | c896fe29 | bellard | #endif
|
526 | c896fe29 | bellard | tcg_out8(s, 0xe8);
|
527 | c896fe29 | bellard | tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] - |
528 | c896fe29 | bellard | (tcg_target_long)s->code_ptr - 4);
|
529 | c896fe29 | bellard | |
530 | c896fe29 | bellard | switch(opc) {
|
531 | c896fe29 | bellard | case 0 | 4: |
532 | c896fe29 | bellard | /* movsbl */
|
533 | c896fe29 | bellard | tcg_out_modrm(s, 0xbe | P_EXT, data_reg, TCG_REG_EAX);
|
534 | c896fe29 | bellard | break;
|
535 | c896fe29 | bellard | case 1 | 4: |
536 | c896fe29 | bellard | /* movswl */
|
537 | c896fe29 | bellard | tcg_out_modrm(s, 0xbf | P_EXT, data_reg, TCG_REG_EAX);
|
538 | c896fe29 | bellard | break;
|
539 | c896fe29 | bellard | case 0: |
540 | 9db3ba4d | aurel32 | /* movzbl */
|
541 | 9db3ba4d | aurel32 | tcg_out_modrm(s, 0xb6 | P_EXT, data_reg, TCG_REG_EAX);
|
542 | 9db3ba4d | aurel32 | break;
|
543 | c896fe29 | bellard | case 1: |
544 | 9db3ba4d | aurel32 | /* movzwl */
|
545 | 9db3ba4d | aurel32 | tcg_out_modrm(s, 0xb7 | P_EXT, data_reg, TCG_REG_EAX);
|
546 | 9db3ba4d | aurel32 | break;
|
547 | c896fe29 | bellard | case 2: |
548 | c896fe29 | bellard | default:
|
549 | c896fe29 | bellard | tcg_out_mov(s, data_reg, TCG_REG_EAX); |
550 | c896fe29 | bellard | break;
|
551 | c896fe29 | bellard | case 3: |
552 | c896fe29 | bellard | if (data_reg == TCG_REG_EDX) {
|
553 | c896fe29 | bellard | tcg_out_opc(s, 0x90 + TCG_REG_EDX); /* xchg %edx, %eax */ |
554 | c896fe29 | bellard | tcg_out_mov(s, data_reg2, TCG_REG_EAX); |
555 | c896fe29 | bellard | } else {
|
556 | c896fe29 | bellard | tcg_out_mov(s, data_reg, TCG_REG_EAX); |
557 | c896fe29 | bellard | tcg_out_mov(s, data_reg2, TCG_REG_EDX); |
558 | c896fe29 | bellard | } |
559 | c896fe29 | bellard | break;
|
560 | c896fe29 | bellard | } |
561 | c896fe29 | bellard | |
562 | c896fe29 | bellard | /* jmp label2 */
|
563 | c896fe29 | bellard | tcg_out8(s, 0xeb);
|
564 | c896fe29 | bellard | label2_ptr = s->code_ptr; |
565 | c896fe29 | bellard | s->code_ptr++; |
566 | c896fe29 | bellard | |
567 | c896fe29 | bellard | /* label1: */
|
568 | c896fe29 | bellard | *label1_ptr = s->code_ptr - label1_ptr - 1;
|
569 | c896fe29 | bellard | |
570 | c896fe29 | bellard | /* add x(r1), r0 */
|
571 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
|
572 | c896fe29 | bellard | offsetof(CPUTLBEntry, addr_read)); |
573 | c896fe29 | bellard | #else
|
574 | c896fe29 | bellard | r0 = addr_reg; |
575 | c896fe29 | bellard | #endif
|
576 | c896fe29 | bellard | |
577 | c896fe29 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
578 | c896fe29 | bellard | bswap = 1;
|
579 | c896fe29 | bellard | #else
|
580 | c896fe29 | bellard | bswap = 0;
|
581 | c896fe29 | bellard | #endif
|
582 | c896fe29 | bellard | switch(opc) {
|
583 | c896fe29 | bellard | case 0: |
584 | c896fe29 | bellard | /* movzbl */
|
585 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, GUEST_BASE);
|
586 | c896fe29 | bellard | break;
|
587 | c896fe29 | bellard | case 0 | 4: |
588 | c896fe29 | bellard | /* movsbl */
|
589 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xbe | P_EXT, data_reg, r0, GUEST_BASE);
|
590 | c896fe29 | bellard | break;
|
591 | c896fe29 | bellard | case 1: |
592 | c896fe29 | bellard | /* movzwl */
|
593 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, GUEST_BASE);
|
594 | c896fe29 | bellard | if (bswap) {
|
595 | c896fe29 | bellard | /* rolw $8, data_reg */
|
596 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
597 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 0, data_reg); |
598 | c896fe29 | bellard | tcg_out8(s, 8);
|
599 | c896fe29 | bellard | } |
600 | c896fe29 | bellard | break;
|
601 | c896fe29 | bellard | case 1 | 4: |
602 | c896fe29 | bellard | /* movswl */
|
603 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xbf | P_EXT, data_reg, r0, GUEST_BASE);
|
604 | c896fe29 | bellard | if (bswap) {
|
605 | c896fe29 | bellard | /* rolw $8, data_reg */
|
606 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
607 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 0, data_reg); |
608 | c896fe29 | bellard | tcg_out8(s, 8);
|
609 | c896fe29 | bellard | |
610 | c896fe29 | bellard | /* movswl data_reg, data_reg */
|
611 | c896fe29 | bellard | tcg_out_modrm(s, 0xbf | P_EXT, data_reg, data_reg);
|
612 | c896fe29 | bellard | } |
613 | c896fe29 | bellard | break;
|
614 | c896fe29 | bellard | case 2: |
615 | c896fe29 | bellard | /* movl (r0), data_reg */
|
616 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, GUEST_BASE);
|
617 | c896fe29 | bellard | if (bswap) {
|
618 | c896fe29 | bellard | /* bswap */
|
619 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + data_reg) | P_EXT);
|
620 | c896fe29 | bellard | } |
621 | c896fe29 | bellard | break;
|
622 | c896fe29 | bellard | case 3: |
623 | c896fe29 | bellard | /* XXX: could be nicer */
|
624 | c896fe29 | bellard | if (r0 == data_reg) {
|
625 | c896fe29 | bellard | r1 = TCG_REG_EDX; |
626 | c896fe29 | bellard | if (r1 == data_reg)
|
627 | c896fe29 | bellard | r1 = TCG_REG_EAX; |
628 | c896fe29 | bellard | tcg_out_mov(s, r1, r0); |
629 | c896fe29 | bellard | r0 = r1; |
630 | c896fe29 | bellard | } |
631 | c896fe29 | bellard | if (!bswap) {
|
632 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, GUEST_BASE);
|
633 | adea8197 | Juan Quintela | tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, GUEST_BASE + 4); |
634 | c896fe29 | bellard | } else {
|
635 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, GUEST_BASE + 4); |
636 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + data_reg) | P_EXT);
|
637 | c896fe29 | bellard | |
638 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, GUEST_BASE);
|
639 | c896fe29 | bellard | /* bswap */
|
640 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + data_reg2) | P_EXT);
|
641 | c896fe29 | bellard | } |
642 | c896fe29 | bellard | break;
|
643 | c896fe29 | bellard | default:
|
644 | c896fe29 | bellard | tcg_abort(); |
645 | c896fe29 | bellard | } |
646 | c896fe29 | bellard | |
647 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
648 | c896fe29 | bellard | /* label2: */
|
649 | c896fe29 | bellard | *label2_ptr = s->code_ptr - label2_ptr - 1;
|
650 | c896fe29 | bellard | #endif
|
651 | c896fe29 | bellard | } |
652 | c896fe29 | bellard | |
653 | c896fe29 | bellard | |
654 | c896fe29 | bellard | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
655 | c896fe29 | bellard | int opc)
|
656 | c896fe29 | bellard | { |
657 | c896fe29 | bellard | int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
|
658 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
659 | c896fe29 | bellard | uint8_t *label1_ptr, *label2_ptr; |
660 | c896fe29 | bellard | #endif
|
661 | c896fe29 | bellard | #if TARGET_LONG_BITS == 64 |
662 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
663 | c896fe29 | bellard | uint8_t *label3_ptr; |
664 | c896fe29 | bellard | #endif
|
665 | c896fe29 | bellard | int addr_reg2;
|
666 | c896fe29 | bellard | #endif
|
667 | c896fe29 | bellard | |
668 | c896fe29 | bellard | data_reg = *args++; |
669 | c896fe29 | bellard | if (opc == 3) |
670 | c896fe29 | bellard | data_reg2 = *args++; |
671 | c896fe29 | bellard | else
|
672 | c896fe29 | bellard | data_reg2 = 0;
|
673 | c896fe29 | bellard | addr_reg = *args++; |
674 | c896fe29 | bellard | #if TARGET_LONG_BITS == 64 |
675 | c896fe29 | bellard | addr_reg2 = *args++; |
676 | c896fe29 | bellard | #endif
|
677 | c896fe29 | bellard | mem_index = *args; |
678 | c896fe29 | bellard | |
679 | c896fe29 | bellard | s_bits = opc; |
680 | c896fe29 | bellard | |
681 | c896fe29 | bellard | r0 = TCG_REG_EAX; |
682 | c896fe29 | bellard | r1 = TCG_REG_EDX; |
683 | c896fe29 | bellard | |
684 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
685 | c896fe29 | bellard | tcg_out_mov(s, r1, addr_reg); |
686 | c896fe29 | bellard | |
687 | c896fe29 | bellard | tcg_out_mov(s, r0, addr_reg); |
688 | c896fe29 | bellard | |
689 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */ |
690 | c896fe29 | bellard | tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
691 | c896fe29 | bellard | |
692 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */ |
693 | c896fe29 | bellard | tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
694 | c896fe29 | bellard | |
695 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
696 | c896fe29 | bellard | tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
697 | c896fe29 | bellard | |
698 | c896fe29 | bellard | tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */ |
699 | c896fe29 | bellard | tcg_out8(s, 0x80 | (r1 << 3) | 0x04); |
700 | c896fe29 | bellard | tcg_out8(s, (5 << 3) | r1); |
701 | c896fe29 | bellard | tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
|
702 | c896fe29 | bellard | |
703 | c896fe29 | bellard | /* cmp 0(r1), r0 */
|
704 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x3b, r0, r1, 0); |
705 | c896fe29 | bellard | |
706 | c896fe29 | bellard | tcg_out_mov(s, r0, addr_reg); |
707 | c896fe29 | bellard | |
708 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
709 | c896fe29 | bellard | /* je label1 */
|
710 | c896fe29 | bellard | tcg_out8(s, 0x70 + JCC_JE);
|
711 | c896fe29 | bellard | label1_ptr = s->code_ptr; |
712 | c896fe29 | bellard | s->code_ptr++; |
713 | c896fe29 | bellard | #else
|
714 | c896fe29 | bellard | /* jne label3 */
|
715 | c896fe29 | bellard | tcg_out8(s, 0x70 + JCC_JNE);
|
716 | c896fe29 | bellard | label3_ptr = s->code_ptr; |
717 | c896fe29 | bellard | s->code_ptr++; |
718 | c896fe29 | bellard | |
719 | c896fe29 | bellard | /* cmp 4(r1), addr_reg2 */
|
720 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4); |
721 | c896fe29 | bellard | |
722 | c896fe29 | bellard | /* je label1 */
|
723 | c896fe29 | bellard | tcg_out8(s, 0x70 + JCC_JE);
|
724 | c896fe29 | bellard | label1_ptr = s->code_ptr; |
725 | c896fe29 | bellard | s->code_ptr++; |
726 | c896fe29 | bellard | |
727 | c896fe29 | bellard | /* label3: */
|
728 | c896fe29 | bellard | *label3_ptr = s->code_ptr - label3_ptr - 1;
|
729 | c896fe29 | bellard | #endif
|
730 | c896fe29 | bellard | |
731 | c896fe29 | bellard | /* XXX: move that code at the end of the TB */
|
732 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
733 | c896fe29 | bellard | if (opc == 3) { |
734 | c896fe29 | bellard | tcg_out_mov(s, TCG_REG_EDX, data_reg); |
735 | c896fe29 | bellard | tcg_out_mov(s, TCG_REG_ECX, data_reg2); |
736 | c896fe29 | bellard | tcg_out8(s, 0x6a); /* push Ib */ |
737 | c896fe29 | bellard | tcg_out8(s, mem_index); |
738 | c896fe29 | bellard | tcg_out8(s, 0xe8);
|
739 | c896fe29 | bellard | tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - |
740 | c896fe29 | bellard | (tcg_target_long)s->code_ptr - 4);
|
741 | c896fe29 | bellard | tcg_out_addi(s, TCG_REG_ESP, 4);
|
742 | c896fe29 | bellard | } else {
|
743 | c896fe29 | bellard | switch(opc) {
|
744 | c896fe29 | bellard | case 0: |
745 | c896fe29 | bellard | /* movzbl */
|
746 | c896fe29 | bellard | tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_EDX, data_reg);
|
747 | c896fe29 | bellard | break;
|
748 | c896fe29 | bellard | case 1: |
749 | c896fe29 | bellard | /* movzwl */
|
750 | c896fe29 | bellard | tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_EDX, data_reg);
|
751 | c896fe29 | bellard | break;
|
752 | c896fe29 | bellard | case 2: |
753 | c896fe29 | bellard | tcg_out_mov(s, TCG_REG_EDX, data_reg); |
754 | c896fe29 | bellard | break;
|
755 | c896fe29 | bellard | } |
756 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index); |
757 | c896fe29 | bellard | tcg_out8(s, 0xe8);
|
758 | c896fe29 | bellard | tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - |
759 | c896fe29 | bellard | (tcg_target_long)s->code_ptr - 4);
|
760 | c896fe29 | bellard | } |
761 | c896fe29 | bellard | #else
|
762 | c896fe29 | bellard | if (opc == 3) { |
763 | c896fe29 | bellard | tcg_out_mov(s, TCG_REG_EDX, addr_reg2); |
764 | c896fe29 | bellard | tcg_out8(s, 0x6a); /* push Ib */ |
765 | c896fe29 | bellard | tcg_out8(s, mem_index); |
766 | c896fe29 | bellard | tcg_out_opc(s, 0x50 + data_reg2); /* push */ |
767 | c896fe29 | bellard | tcg_out_opc(s, 0x50 + data_reg); /* push */ |
768 | c896fe29 | bellard | tcg_out8(s, 0xe8);
|
769 | c896fe29 | bellard | tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - |
770 | c896fe29 | bellard | (tcg_target_long)s->code_ptr - 4);
|
771 | c896fe29 | bellard | tcg_out_addi(s, TCG_REG_ESP, 12);
|
772 | c896fe29 | bellard | } else {
|
773 | c896fe29 | bellard | tcg_out_mov(s, TCG_REG_EDX, addr_reg2); |
774 | c896fe29 | bellard | switch(opc) {
|
775 | c896fe29 | bellard | case 0: |
776 | c896fe29 | bellard | /* movzbl */
|
777 | c896fe29 | bellard | tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_ECX, data_reg);
|
778 | c896fe29 | bellard | break;
|
779 | c896fe29 | bellard | case 1: |
780 | c896fe29 | bellard | /* movzwl */
|
781 | c896fe29 | bellard | tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_ECX, data_reg);
|
782 | c896fe29 | bellard | break;
|
783 | c896fe29 | bellard | case 2: |
784 | c896fe29 | bellard | tcg_out_mov(s, TCG_REG_ECX, data_reg); |
785 | c896fe29 | bellard | break;
|
786 | c896fe29 | bellard | } |
787 | c896fe29 | bellard | tcg_out8(s, 0x6a); /* push Ib */ |
788 | c896fe29 | bellard | tcg_out8(s, mem_index); |
789 | c896fe29 | bellard | tcg_out8(s, 0xe8);
|
790 | c896fe29 | bellard | tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - |
791 | c896fe29 | bellard | (tcg_target_long)s->code_ptr - 4);
|
792 | c896fe29 | bellard | tcg_out_addi(s, TCG_REG_ESP, 4);
|
793 | c896fe29 | bellard | } |
794 | c896fe29 | bellard | #endif
|
795 | c896fe29 | bellard | |
796 | c896fe29 | bellard | /* jmp label2 */
|
797 | c896fe29 | bellard | tcg_out8(s, 0xeb);
|
798 | c896fe29 | bellard | label2_ptr = s->code_ptr; |
799 | c896fe29 | bellard | s->code_ptr++; |
800 | c896fe29 | bellard | |
801 | c896fe29 | bellard | /* label1: */
|
802 | c896fe29 | bellard | *label1_ptr = s->code_ptr - label1_ptr - 1;
|
803 | c896fe29 | bellard | |
804 | c896fe29 | bellard | /* add x(r1), r0 */
|
805 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
|
806 | c896fe29 | bellard | offsetof(CPUTLBEntry, addr_write)); |
807 | c896fe29 | bellard | #else
|
808 | c896fe29 | bellard | r0 = addr_reg; |
809 | c896fe29 | bellard | #endif
|
810 | c896fe29 | bellard | |
811 | c896fe29 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
812 | c896fe29 | bellard | bswap = 1;
|
813 | c896fe29 | bellard | #else
|
814 | c896fe29 | bellard | bswap = 0;
|
815 | c896fe29 | bellard | #endif
|
816 | c896fe29 | bellard | switch(opc) {
|
817 | c896fe29 | bellard | case 0: |
818 | c896fe29 | bellard | /* movb */
|
819 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x88, data_reg, r0, GUEST_BASE);
|
820 | c896fe29 | bellard | break;
|
821 | c896fe29 | bellard | case 1: |
822 | c896fe29 | bellard | if (bswap) {
|
823 | c896fe29 | bellard | tcg_out_mov(s, r1, data_reg); |
824 | c896fe29 | bellard | tcg_out8(s, 0x66); /* rolw $8, %ecx */ |
825 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 0, r1); |
826 | c896fe29 | bellard | tcg_out8(s, 8);
|
827 | c896fe29 | bellard | data_reg = r1; |
828 | c896fe29 | bellard | } |
829 | c896fe29 | bellard | /* movw */
|
830 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
831 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x89, data_reg, r0, GUEST_BASE);
|
832 | c896fe29 | bellard | break;
|
833 | c896fe29 | bellard | case 2: |
834 | c896fe29 | bellard | if (bswap) {
|
835 | c896fe29 | bellard | tcg_out_mov(s, r1, data_reg); |
836 | c896fe29 | bellard | /* bswap data_reg */
|
837 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + r1) | P_EXT);
|
838 | c896fe29 | bellard | data_reg = r1; |
839 | c896fe29 | bellard | } |
840 | c896fe29 | bellard | /* movl */
|
841 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x89, data_reg, r0, GUEST_BASE);
|
842 | c896fe29 | bellard | break;
|
843 | c896fe29 | bellard | case 3: |
844 | c896fe29 | bellard | if (bswap) {
|
845 | c896fe29 | bellard | tcg_out_mov(s, r1, data_reg2); |
846 | c896fe29 | bellard | /* bswap data_reg */
|
847 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + r1) | P_EXT);
|
848 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x89, r1, r0, GUEST_BASE);
|
849 | c896fe29 | bellard | tcg_out_mov(s, r1, data_reg); |
850 | c896fe29 | bellard | /* bswap data_reg */
|
851 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + r1) | P_EXT);
|
852 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x89, r1, r0, GUEST_BASE + 4); |
853 | c896fe29 | bellard | } else {
|
854 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x89, data_reg, r0, GUEST_BASE);
|
855 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x89, data_reg2, r0, GUEST_BASE + 4); |
856 | c896fe29 | bellard | } |
857 | c896fe29 | bellard | break;
|
858 | c896fe29 | bellard | default:
|
859 | c896fe29 | bellard | tcg_abort(); |
860 | c896fe29 | bellard | } |
861 | c896fe29 | bellard | |
862 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
863 | c896fe29 | bellard | /* label2: */
|
864 | c896fe29 | bellard | *label2_ptr = s->code_ptr - label2_ptr - 1;
|
865 | c896fe29 | bellard | #endif
|
866 | c896fe29 | bellard | } |
867 | c896fe29 | bellard | |
868 | c896fe29 | bellard | static inline void tcg_out_op(TCGContext *s, int opc, |
869 | c896fe29 | bellard | const TCGArg *args, const int *const_args) |
870 | c896fe29 | bellard | { |
871 | c896fe29 | bellard | int c;
|
872 | c896fe29 | bellard | |
873 | c896fe29 | bellard | switch(opc) {
|
874 | c896fe29 | bellard | case INDEX_op_exit_tb:
|
875 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
|
876 | b03cce8e | bellard | tcg_out8(s, 0xe9); /* jmp tb_ret_addr */ |
877 | b03cce8e | bellard | tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
|
878 | c896fe29 | bellard | break;
|
879 | c896fe29 | bellard | case INDEX_op_goto_tb:
|
880 | c896fe29 | bellard | if (s->tb_jmp_offset) {
|
881 | c896fe29 | bellard | /* direct jump method */
|
882 | c896fe29 | bellard | tcg_out8(s, 0xe9); /* jmp im */ |
883 | c896fe29 | bellard | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
884 | c896fe29 | bellard | tcg_out32(s, 0);
|
885 | c896fe29 | bellard | } else {
|
886 | c896fe29 | bellard | /* indirect jump method */
|
887 | c896fe29 | bellard | /* jmp Ev */
|
888 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xff, 4, -1, |
889 | c896fe29 | bellard | (tcg_target_long)(s->tb_next + args[0]));
|
890 | c896fe29 | bellard | } |
891 | c896fe29 | bellard | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
892 | c896fe29 | bellard | break;
|
893 | c896fe29 | bellard | case INDEX_op_call:
|
894 | c896fe29 | bellard | if (const_args[0]) { |
895 | c896fe29 | bellard | tcg_out8(s, 0xe8);
|
896 | c896fe29 | bellard | tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4); |
897 | c896fe29 | bellard | } else {
|
898 | c896fe29 | bellard | tcg_out_modrm(s, 0xff, 2, args[0]); |
899 | c896fe29 | bellard | } |
900 | c896fe29 | bellard | break;
|
901 | c896fe29 | bellard | case INDEX_op_jmp:
|
902 | c896fe29 | bellard | if (const_args[0]) { |
903 | c896fe29 | bellard | tcg_out8(s, 0xe9);
|
904 | c896fe29 | bellard | tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4); |
905 | c896fe29 | bellard | } else {
|
906 | c896fe29 | bellard | tcg_out_modrm(s, 0xff, 4, args[0]); |
907 | c896fe29 | bellard | } |
908 | c896fe29 | bellard | break;
|
909 | c896fe29 | bellard | case INDEX_op_br:
|
910 | c896fe29 | bellard | tcg_out_jxx(s, JCC_JMP, args[0]);
|
911 | c896fe29 | bellard | break;
|
912 | c896fe29 | bellard | case INDEX_op_movi_i32:
|
913 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]); |
914 | c896fe29 | bellard | break;
|
915 | c896fe29 | bellard | case INDEX_op_ld8u_i32:
|
916 | c896fe29 | bellard | /* movzbl */
|
917 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]); |
918 | c896fe29 | bellard | break;
|
919 | c896fe29 | bellard | case INDEX_op_ld8s_i32:
|
920 | c896fe29 | bellard | /* movsbl */
|
921 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]); |
922 | c896fe29 | bellard | break;
|
923 | c896fe29 | bellard | case INDEX_op_ld16u_i32:
|
924 | c896fe29 | bellard | /* movzwl */
|
925 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]); |
926 | c896fe29 | bellard | break;
|
927 | c896fe29 | bellard | case INDEX_op_ld16s_i32:
|
928 | c896fe29 | bellard | /* movswl */
|
929 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]); |
930 | c896fe29 | bellard | break;
|
931 | c896fe29 | bellard | case INDEX_op_ld_i32:
|
932 | c896fe29 | bellard | /* movl */
|
933 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]); |
934 | c896fe29 | bellard | break;
|
935 | c896fe29 | bellard | case INDEX_op_st8_i32:
|
936 | c896fe29 | bellard | /* movb */
|
937 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x88, args[0], args[1], args[2]); |
938 | c896fe29 | bellard | break;
|
939 | c896fe29 | bellard | case INDEX_op_st16_i32:
|
940 | c896fe29 | bellard | /* movw */
|
941 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
942 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
943 | c896fe29 | bellard | break;
|
944 | c896fe29 | bellard | case INDEX_op_st_i32:
|
945 | c896fe29 | bellard | /* movl */
|
946 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
947 | c896fe29 | bellard | break;
|
948 | c896fe29 | bellard | case INDEX_op_sub_i32:
|
949 | c896fe29 | bellard | c = ARITH_SUB; |
950 | c896fe29 | bellard | goto gen_arith;
|
951 | c896fe29 | bellard | case INDEX_op_and_i32:
|
952 | c896fe29 | bellard | c = ARITH_AND; |
953 | c896fe29 | bellard | goto gen_arith;
|
954 | c896fe29 | bellard | case INDEX_op_or_i32:
|
955 | c896fe29 | bellard | c = ARITH_OR; |
956 | c896fe29 | bellard | goto gen_arith;
|
957 | c896fe29 | bellard | case INDEX_op_xor_i32:
|
958 | c896fe29 | bellard | c = ARITH_XOR; |
959 | c896fe29 | bellard | goto gen_arith;
|
960 | c896fe29 | bellard | case INDEX_op_add_i32:
|
961 | c896fe29 | bellard | c = ARITH_ADD; |
962 | c896fe29 | bellard | gen_arith:
|
963 | c896fe29 | bellard | if (const_args[2]) { |
964 | c896fe29 | bellard | tgen_arithi(s, c, args[0], args[2]); |
965 | c896fe29 | bellard | } else {
|
966 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]); |
967 | c896fe29 | bellard | } |
968 | c896fe29 | bellard | break;
|
969 | c896fe29 | bellard | case INDEX_op_mul_i32:
|
970 | c896fe29 | bellard | if (const_args[2]) { |
971 | c896fe29 | bellard | int32_t val; |
972 | c896fe29 | bellard | val = args[2];
|
973 | c896fe29 | bellard | if (val == (int8_t)val) {
|
974 | c896fe29 | bellard | tcg_out_modrm(s, 0x6b, args[0], args[0]); |
975 | c896fe29 | bellard | tcg_out8(s, val); |
976 | c896fe29 | bellard | } else {
|
977 | c896fe29 | bellard | tcg_out_modrm(s, 0x69, args[0], args[0]); |
978 | c896fe29 | bellard | tcg_out32(s, val); |
979 | c896fe29 | bellard | } |
980 | c896fe29 | bellard | } else {
|
981 | c896fe29 | bellard | tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]); |
982 | c896fe29 | bellard | } |
983 | c896fe29 | bellard | break;
|
984 | c896fe29 | bellard | case INDEX_op_mulu2_i32:
|
985 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7, 4, args[3]); |
986 | c896fe29 | bellard | break;
|
987 | c896fe29 | bellard | case INDEX_op_div2_i32:
|
988 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7, 7, args[4]); |
989 | c896fe29 | bellard | break;
|
990 | c896fe29 | bellard | case INDEX_op_divu2_i32:
|
991 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7, 6, args[4]); |
992 | c896fe29 | bellard | break;
|
993 | c896fe29 | bellard | case INDEX_op_shl_i32:
|
994 | c896fe29 | bellard | c = SHIFT_SHL; |
995 | c896fe29 | bellard | gen_shift32:
|
996 | c896fe29 | bellard | if (const_args[2]) { |
997 | c896fe29 | bellard | if (args[2] == 1) { |
998 | c896fe29 | bellard | tcg_out_modrm(s, 0xd1, c, args[0]); |
999 | c896fe29 | bellard | } else {
|
1000 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, c, args[0]); |
1001 | c896fe29 | bellard | tcg_out8(s, args[2]);
|
1002 | c896fe29 | bellard | } |
1003 | c896fe29 | bellard | } else {
|
1004 | c896fe29 | bellard | tcg_out_modrm(s, 0xd3, c, args[0]); |
1005 | c896fe29 | bellard | } |
1006 | c896fe29 | bellard | break;
|
1007 | c896fe29 | bellard | case INDEX_op_shr_i32:
|
1008 | c896fe29 | bellard | c = SHIFT_SHR; |
1009 | c896fe29 | bellard | goto gen_shift32;
|
1010 | c896fe29 | bellard | case INDEX_op_sar_i32:
|
1011 | c896fe29 | bellard | c = SHIFT_SAR; |
1012 | c896fe29 | bellard | goto gen_shift32;
|
1013 | 9619376c | aurel32 | case INDEX_op_rotl_i32:
|
1014 | 9619376c | aurel32 | c = SHIFT_ROL; |
1015 | 9619376c | aurel32 | goto gen_shift32;
|
1016 | 9619376c | aurel32 | case INDEX_op_rotr_i32:
|
1017 | 9619376c | aurel32 | c = SHIFT_ROR; |
1018 | 9619376c | aurel32 | goto gen_shift32;
|
1019 | 9619376c | aurel32 | |
1020 | c896fe29 | bellard | case INDEX_op_add2_i32:
|
1021 | c896fe29 | bellard | if (const_args[4]) |
1022 | c896fe29 | bellard | tgen_arithi(s, ARITH_ADD, args[0], args[4]); |
1023 | c896fe29 | bellard | else
|
1024 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (ARITH_ADD << 3), args[4], args[0]); |
1025 | c896fe29 | bellard | if (const_args[5]) |
1026 | c896fe29 | bellard | tgen_arithi(s, ARITH_ADC, args[1], args[5]); |
1027 | c896fe29 | bellard | else
|
1028 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (ARITH_ADC << 3), args[5], args[1]); |
1029 | c896fe29 | bellard | break;
|
1030 | c896fe29 | bellard | case INDEX_op_sub2_i32:
|
1031 | c896fe29 | bellard | if (const_args[4]) |
1032 | c896fe29 | bellard | tgen_arithi(s, ARITH_SUB, args[0], args[4]); |
1033 | c896fe29 | bellard | else
|
1034 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (ARITH_SUB << 3), args[4], args[0]); |
1035 | c896fe29 | bellard | if (const_args[5]) |
1036 | c896fe29 | bellard | tgen_arithi(s, ARITH_SBB, args[1], args[5]); |
1037 | c896fe29 | bellard | else
|
1038 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (ARITH_SBB << 3), args[5], args[1]); |
1039 | c896fe29 | bellard | break;
|
1040 | c896fe29 | bellard | case INDEX_op_brcond_i32:
|
1041 | c896fe29 | bellard | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]); |
1042 | c896fe29 | bellard | break;
|
1043 | c896fe29 | bellard | case INDEX_op_brcond2_i32:
|
1044 | c896fe29 | bellard | tcg_out_brcond2(s, args, const_args); |
1045 | c896fe29 | bellard | break;
|
1046 | c896fe29 | bellard | |
1047 | 5d40cd63 | aurel32 | case INDEX_op_bswap16_i32:
|
1048 | 5d40cd63 | aurel32 | tcg_out8(s, 0x66);
|
1049 | 5d40cd63 | aurel32 | tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]); |
1050 | 5d40cd63 | aurel32 | tcg_out8(s, 8);
|
1051 | 5d40cd63 | aurel32 | break;
|
1052 | 66896cb8 | aurel32 | case INDEX_op_bswap32_i32:
|
1053 | 9619376c | aurel32 | tcg_out_opc(s, (0xc8 + args[0]) | P_EXT); |
1054 | 9619376c | aurel32 | break;
|
1055 | 9619376c | aurel32 | |
1056 | 9619376c | aurel32 | case INDEX_op_neg_i32:
|
1057 | 9619376c | aurel32 | tcg_out_modrm(s, 0xf7, 3, args[0]); |
1058 | 9619376c | aurel32 | break;
|
1059 | 9619376c | aurel32 | |
1060 | 9619376c | aurel32 | case INDEX_op_not_i32:
|
1061 | 9619376c | aurel32 | tcg_out_modrm(s, 0xf7, 2, args[0]); |
1062 | 9619376c | aurel32 | break;
|
1063 | 9619376c | aurel32 | |
1064 | 9619376c | aurel32 | case INDEX_op_ext8s_i32:
|
1065 | 9619376c | aurel32 | tcg_out_modrm(s, 0xbe | P_EXT, args[0], args[1]); |
1066 | 9619376c | aurel32 | break;
|
1067 | 9619376c | aurel32 | case INDEX_op_ext16s_i32:
|
1068 | 9619376c | aurel32 | tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]); |
1069 | 9619376c | aurel32 | break;
|
1070 | 9619376c | aurel32 | |
1071 | c896fe29 | bellard | case INDEX_op_qemu_ld8u:
|
1072 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 0);
|
1073 | c896fe29 | bellard | break;
|
1074 | c896fe29 | bellard | case INDEX_op_qemu_ld8s:
|
1075 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 0 | 4); |
1076 | c896fe29 | bellard | break;
|
1077 | c896fe29 | bellard | case INDEX_op_qemu_ld16u:
|
1078 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 1);
|
1079 | c896fe29 | bellard | break;
|
1080 | c896fe29 | bellard | case INDEX_op_qemu_ld16s:
|
1081 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 1 | 4); |
1082 | c896fe29 | bellard | break;
|
1083 | c896fe29 | bellard | case INDEX_op_qemu_ld32u:
|
1084 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 2);
|
1085 | c896fe29 | bellard | break;
|
1086 | c896fe29 | bellard | case INDEX_op_qemu_ld64:
|
1087 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 3);
|
1088 | c896fe29 | bellard | break;
|
1089 | c896fe29 | bellard | |
1090 | c896fe29 | bellard | case INDEX_op_qemu_st8:
|
1091 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 0);
|
1092 | c896fe29 | bellard | break;
|
1093 | c896fe29 | bellard | case INDEX_op_qemu_st16:
|
1094 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 1);
|
1095 | c896fe29 | bellard | break;
|
1096 | c896fe29 | bellard | case INDEX_op_qemu_st32:
|
1097 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 2);
|
1098 | c896fe29 | bellard | break;
|
1099 | c896fe29 | bellard | case INDEX_op_qemu_st64:
|
1100 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 3);
|
1101 | c896fe29 | bellard | break;
|
1102 | c896fe29 | bellard | |
1103 | c896fe29 | bellard | default:
|
1104 | c896fe29 | bellard | tcg_abort(); |
1105 | c896fe29 | bellard | } |
1106 | c896fe29 | bellard | } |
1107 | c896fe29 | bellard | |
1108 | c896fe29 | bellard | static const TCGTargetOpDef x86_op_defs[] = { |
1109 | c896fe29 | bellard | { INDEX_op_exit_tb, { } }, |
1110 | c896fe29 | bellard | { INDEX_op_goto_tb, { } }, |
1111 | c896fe29 | bellard | { INDEX_op_call, { "ri" } },
|
1112 | c896fe29 | bellard | { INDEX_op_jmp, { "ri" } },
|
1113 | c896fe29 | bellard | { INDEX_op_br, { } }, |
1114 | c896fe29 | bellard | { INDEX_op_mov_i32, { "r", "r" } }, |
1115 | c896fe29 | bellard | { INDEX_op_movi_i32, { "r" } },
|
1116 | c896fe29 | bellard | { INDEX_op_ld8u_i32, { "r", "r" } }, |
1117 | c896fe29 | bellard | { INDEX_op_ld8s_i32, { "r", "r" } }, |
1118 | c896fe29 | bellard | { INDEX_op_ld16u_i32, { "r", "r" } }, |
1119 | c896fe29 | bellard | { INDEX_op_ld16s_i32, { "r", "r" } }, |
1120 | c896fe29 | bellard | { INDEX_op_ld_i32, { "r", "r" } }, |
1121 | c896fe29 | bellard | { INDEX_op_st8_i32, { "q", "r" } }, |
1122 | c896fe29 | bellard | { INDEX_op_st16_i32, { "r", "r" } }, |
1123 | c896fe29 | bellard | { INDEX_op_st_i32, { "r", "r" } }, |
1124 | c896fe29 | bellard | |
1125 | c896fe29 | bellard | { INDEX_op_add_i32, { "r", "0", "ri" } }, |
1126 | c896fe29 | bellard | { INDEX_op_sub_i32, { "r", "0", "ri" } }, |
1127 | c896fe29 | bellard | { INDEX_op_mul_i32, { "r", "0", "ri" } }, |
1128 | c896fe29 | bellard | { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } }, |
1129 | c896fe29 | bellard | { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } }, |
1130 | c896fe29 | bellard | { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } }, |
1131 | c896fe29 | bellard | { INDEX_op_and_i32, { "r", "0", "ri" } }, |
1132 | c896fe29 | bellard | { INDEX_op_or_i32, { "r", "0", "ri" } }, |
1133 | c896fe29 | bellard | { INDEX_op_xor_i32, { "r", "0", "ri" } }, |
1134 | c896fe29 | bellard | |
1135 | c896fe29 | bellard | { INDEX_op_shl_i32, { "r", "0", "ci" } }, |
1136 | c896fe29 | bellard | { INDEX_op_shr_i32, { "r", "0", "ci" } }, |
1137 | c896fe29 | bellard | { INDEX_op_sar_i32, { "r", "0", "ci" } }, |
1138 | 9619376c | aurel32 | { INDEX_op_sar_i32, { "r", "0", "ci" } }, |
1139 | 9619376c | aurel32 | { INDEX_op_rotl_i32, { "r", "0", "ci" } }, |
1140 | 9619376c | aurel32 | { INDEX_op_rotr_i32, { "r", "0", "ci" } }, |
1141 | c896fe29 | bellard | |
1142 | c896fe29 | bellard | { INDEX_op_brcond_i32, { "r", "ri" } }, |
1143 | c896fe29 | bellard | |
1144 | c896fe29 | bellard | { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } }, |
1145 | c896fe29 | bellard | { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } }, |
1146 | c896fe29 | bellard | { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } }, |
1147 | c896fe29 | bellard | |
1148 | 5d40cd63 | aurel32 | { INDEX_op_bswap16_i32, { "r", "0" } }, |
1149 | 66896cb8 | aurel32 | { INDEX_op_bswap32_i32, { "r", "0" } }, |
1150 | 9619376c | aurel32 | |
1151 | 9619376c | aurel32 | { INDEX_op_neg_i32, { "r", "0" } }, |
1152 | 9619376c | aurel32 | |
1153 | 9619376c | aurel32 | { INDEX_op_not_i32, { "r", "0" } }, |
1154 | 9619376c | aurel32 | |
1155 | 9619376c | aurel32 | { INDEX_op_ext8s_i32, { "r", "q" } }, |
1156 | 9619376c | aurel32 | { INDEX_op_ext16s_i32, { "r", "r" } }, |
1157 | 9619376c | aurel32 | |
1158 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
1159 | c896fe29 | bellard | { INDEX_op_qemu_ld8u, { "r", "L" } }, |
1160 | c896fe29 | bellard | { INDEX_op_qemu_ld8s, { "r", "L" } }, |
1161 | c896fe29 | bellard | { INDEX_op_qemu_ld16u, { "r", "L" } }, |
1162 | c896fe29 | bellard | { INDEX_op_qemu_ld16s, { "r", "L" } }, |
1163 | c896fe29 | bellard | { INDEX_op_qemu_ld32u, { "r", "L" } }, |
1164 | c896fe29 | bellard | { INDEX_op_qemu_ld64, { "r", "r", "L" } }, |
1165 | c896fe29 | bellard | |
1166 | c896fe29 | bellard | { INDEX_op_qemu_st8, { "cb", "L" } }, |
1167 | c896fe29 | bellard | { INDEX_op_qemu_st16, { "L", "L" } }, |
1168 | c896fe29 | bellard | { INDEX_op_qemu_st32, { "L", "L" } }, |
1169 | c896fe29 | bellard | { INDEX_op_qemu_st64, { "L", "L", "L" } }, |
1170 | c896fe29 | bellard | #else
|
1171 | c896fe29 | bellard | { INDEX_op_qemu_ld8u, { "r", "L", "L" } }, |
1172 | c896fe29 | bellard | { INDEX_op_qemu_ld8s, { "r", "L", "L" } }, |
1173 | c896fe29 | bellard | { INDEX_op_qemu_ld16u, { "r", "L", "L" } }, |
1174 | c896fe29 | bellard | { INDEX_op_qemu_ld16s, { "r", "L", "L" } }, |
1175 | c896fe29 | bellard | { INDEX_op_qemu_ld32u, { "r", "L", "L" } }, |
1176 | c896fe29 | bellard | { INDEX_op_qemu_ld64, { "r", "r", "L", "L" } }, |
1177 | c896fe29 | bellard | |
1178 | c896fe29 | bellard | { INDEX_op_qemu_st8, { "cb", "L", "L" } }, |
1179 | c896fe29 | bellard | { INDEX_op_qemu_st16, { "L", "L", "L" } }, |
1180 | c896fe29 | bellard | { INDEX_op_qemu_st32, { "L", "L", "L" } }, |
1181 | c896fe29 | bellard | { INDEX_op_qemu_st64, { "L", "L", "L", "L" } }, |
1182 | c896fe29 | bellard | #endif
|
1183 | c896fe29 | bellard | { -1 },
|
1184 | c896fe29 | bellard | }; |
1185 | c896fe29 | bellard | |
1186 | b03cce8e | bellard | static int tcg_target_callee_save_regs[] = { |
1187 | b03cce8e | bellard | /* TCG_REG_EBP, */ /* currently used for the global env, so no |
1188 | b03cce8e | bellard | need to save */
|
1189 | b03cce8e | bellard | TCG_REG_EBX, |
1190 | b03cce8e | bellard | TCG_REG_ESI, |
1191 | b03cce8e | bellard | TCG_REG_EDI, |
1192 | b03cce8e | bellard | }; |
1193 | b03cce8e | bellard | |
1194 | b03cce8e | bellard | static inline void tcg_out_push(TCGContext *s, int reg) |
1195 | b03cce8e | bellard | { |
1196 | b03cce8e | bellard | tcg_out_opc(s, 0x50 + reg);
|
1197 | b03cce8e | bellard | } |
1198 | b03cce8e | bellard | |
1199 | b03cce8e | bellard | static inline void tcg_out_pop(TCGContext *s, int reg) |
1200 | b03cce8e | bellard | { |
1201 | b03cce8e | bellard | tcg_out_opc(s, 0x58 + reg);
|
1202 | b03cce8e | bellard | } |
1203 | b03cce8e | bellard | |
1204 | b03cce8e | bellard | /* Generate global QEMU prologue and epilogue code */
|
1205 | b03cce8e | bellard | void tcg_target_qemu_prologue(TCGContext *s)
|
1206 | b03cce8e | bellard | { |
1207 | b03cce8e | bellard | int i, frame_size, push_size, stack_addend;
|
1208 | b03cce8e | bellard | |
1209 | b03cce8e | bellard | /* TB prologue */
|
1210 | b03cce8e | bellard | /* save all callee saved registers */
|
1211 | b03cce8e | bellard | for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { |
1212 | b03cce8e | bellard | tcg_out_push(s, tcg_target_callee_save_regs[i]); |
1213 | b03cce8e | bellard | } |
1214 | b03cce8e | bellard | /* reserve some stack space */
|
1215 | b03cce8e | bellard | push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4; |
1216 | b03cce8e | bellard | frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE; |
1217 | b03cce8e | bellard | frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
|
1218 | b03cce8e | bellard | ~(TCG_TARGET_STACK_ALIGN - 1);
|
1219 | b03cce8e | bellard | stack_addend = frame_size - push_size; |
1220 | b03cce8e | bellard | tcg_out_addi(s, TCG_REG_ESP, -stack_addend); |
1221 | b03cce8e | bellard | |
1222 | b03cce8e | bellard | tcg_out_modrm(s, 0xff, 4, TCG_REG_EAX); /* jmp *%eax */ |
1223 | b03cce8e | bellard | |
1224 | b03cce8e | bellard | /* TB epilogue */
|
1225 | b03cce8e | bellard | tb_ret_addr = s->code_ptr; |
1226 | b03cce8e | bellard | tcg_out_addi(s, TCG_REG_ESP, stack_addend); |
1227 | b03cce8e | bellard | for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { |
1228 | b03cce8e | bellard | tcg_out_pop(s, tcg_target_callee_save_regs[i]); |
1229 | b03cce8e | bellard | } |
1230 | b03cce8e | bellard | tcg_out8(s, 0xc3); /* ret */ |
1231 | b03cce8e | bellard | } |
1232 | b03cce8e | bellard | |
1233 | c896fe29 | bellard | void tcg_target_init(TCGContext *s)
|
1234 | c896fe29 | bellard | { |
1235 | c896fe29 | bellard | /* fail safe */
|
1236 | c896fe29 | bellard | if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) |
1237 | c896fe29 | bellard | tcg_abort(); |
1238 | c896fe29 | bellard | |
1239 | c896fe29 | bellard | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff); |
1240 | c896fe29 | bellard | tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
1241 | c896fe29 | bellard | (1 << TCG_REG_EAX) |
|
1242 | c896fe29 | bellard | (1 << TCG_REG_EDX) |
|
1243 | c896fe29 | bellard | (1 << TCG_REG_ECX));
|
1244 | c896fe29 | bellard | |
1245 | c896fe29 | bellard | tcg_regset_clear(s->reserved_regs); |
1246 | c896fe29 | bellard | tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP); |
1247 | c896fe29 | bellard | |
1248 | c896fe29 | bellard | tcg_add_target_add_op_defs(x86_op_defs); |
1249 | c896fe29 | bellard | } |