Revision b7578eaa
| b/hw/misc/ivshmem.c | ||
|---|---|---|
| 63 | 63 |
} EventfdEntry; |
| 64 | 64 |
|
| 65 | 65 |
typedef struct IVShmemState {
|
| 66 |
PCIDevice dev; |
|
| 66 |
/*< private >*/ |
|
| 67 |
PCIDevice parent_obj; |
|
| 68 |
/*< public >*/ |
|
| 69 |
|
|
| 67 | 70 |
uint32_t intrmask; |
| 68 | 71 |
uint32_t intrstatus; |
| 69 | 72 |
uint32_t doorbell; |
| ... | ... | |
| 120 | 123 |
/* accessing registers - based on rtl8139 */ |
| 121 | 124 |
static void ivshmem_update_irq(IVShmemState *s, int val) |
| 122 | 125 |
{
|
| 126 |
PCIDevice *d = PCI_DEVICE(s); |
|
| 123 | 127 |
int isr; |
| 124 | 128 |
isr = (s->intrstatus & s->intrmask) & 0xffffffff; |
| 125 | 129 |
|
| ... | ... | |
| 129 | 133 |
isr ? 1 : 0, s->intrstatus, s->intrmask); |
| 130 | 134 |
} |
| 131 | 135 |
|
| 132 |
qemu_set_irq(s->dev.irq[0], (isr != 0));
|
|
| 136 |
qemu_set_irq(d->irq[0], (isr != 0));
|
|
| 133 | 137 |
} |
| 134 | 138 |
|
| 135 | 139 |
static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val) |
| ... | ... | |
| 300 | 304 |
|
| 301 | 305 |
/* if MSI is supported we need multiple interrupts */ |
| 302 | 306 |
if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
|
| 303 |
s->eventfd_table[vector].pdev = &s->dev;
|
|
| 307 |
s->eventfd_table[vector].pdev = PCI_DEVICE(s);
|
|
| 304 | 308 |
s->eventfd_table[vector].vector = vector; |
| 305 | 309 |
|
| 306 | 310 |
qemu_chr_add_handlers(chr, ivshmem_can_receive, fake_irqfd, |
| ... | ... | |
| 349 | 353 |
memory_region_add_subregion(&s->bar, 0, &s->ivshmem); |
| 350 | 354 |
|
| 351 | 355 |
/* region for shared memory */ |
| 352 |
pci_register_bar(&s->dev, 2, s->ivshmem_attr, &s->bar);
|
|
| 356 |
pci_register_bar(PCI_DEVICE(s), 2, s->ivshmem_attr, &s->bar);
|
|
| 353 | 357 |
} |
| 354 | 358 |
|
| 355 | 359 |
static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i) |
| ... | ... | |
| 525 | 529 |
* we just enable all vectors on init and after reset. */ |
| 526 | 530 |
static void ivshmem_use_msix(IVShmemState * s) |
| 527 | 531 |
{
|
| 532 |
PCIDevice *d = PCI_DEVICE(s); |
|
| 528 | 533 |
int i; |
| 529 | 534 |
|
| 530 |
if (!msix_present(&s->dev)) {
|
|
| 535 |
if (!msix_present(d)) {
|
|
| 531 | 536 |
return; |
| 532 | 537 |
} |
| 533 | 538 |
|
| 534 | 539 |
for (i = 0; i < s->vectors; i++) {
|
| 535 |
msix_vector_use(&s->dev, i);
|
|
| 540 |
msix_vector_use(d, i);
|
|
| 536 | 541 |
} |
| 537 | 542 |
} |
| 538 | 543 |
|
| ... | ... | |
| 573 | 578 |
|
| 574 | 579 |
static void ivshmem_setup_msi(IVShmemState * s) |
| 575 | 580 |
{
|
| 576 |
if (msix_init_exclusive_bar(&s->dev, s->vectors, 1)) {
|
|
| 581 |
if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1)) {
|
|
| 577 | 582 |
IVSHMEM_DPRINTF("msix initialization failed\n");
|
| 578 | 583 |
exit(1); |
| 579 | 584 |
} |
| ... | ... | |
| 589 | 594 |
static void ivshmem_save(QEMUFile* f, void *opaque) |
| 590 | 595 |
{
|
| 591 | 596 |
IVShmemState *proxy = opaque; |
| 597 |
PCIDevice *pci_dev = PCI_DEVICE(proxy); |
|
| 592 | 598 |
|
| 593 | 599 |
IVSHMEM_DPRINTF("ivshmem_save\n");
|
| 594 |
pci_device_save(&proxy->dev, f);
|
|
| 600 |
pci_device_save(pci_dev, f);
|
|
| 595 | 601 |
|
| 596 | 602 |
if (ivshmem_has_feature(proxy, IVSHMEM_MSI)) {
|
| 597 |
msix_save(&proxy->dev, f);
|
|
| 603 |
msix_save(pci_dev, f);
|
|
| 598 | 604 |
} else {
|
| 599 | 605 |
qemu_put_be32(f, proxy->intrstatus); |
| 600 | 606 |
qemu_put_be32(f, proxy->intrmask); |
| ... | ... | |
| 607 | 613 |
IVSHMEM_DPRINTF("ivshmem_load\n");
|
| 608 | 614 |
|
| 609 | 615 |
IVShmemState *proxy = opaque; |
| 616 |
PCIDevice *pci_dev = PCI_DEVICE(proxy); |
|
| 610 | 617 |
int ret; |
| 611 | 618 |
|
| 612 | 619 |
if (version_id > 0) {
|
| ... | ... | |
| 618 | 625 |
return -EINVAL; |
| 619 | 626 |
} |
| 620 | 627 |
|
| 621 |
ret = pci_device_load(&proxy->dev, f);
|
|
| 628 |
ret = pci_device_load(pci_dev, f);
|
|
| 622 | 629 |
if (ret) {
|
| 623 | 630 |
return ret; |
| 624 | 631 |
} |
| 625 | 632 |
|
| 626 | 633 |
if (ivshmem_has_feature(proxy, IVSHMEM_MSI)) {
|
| 627 |
msix_load(&proxy->dev, f);
|
|
| 634 |
msix_load(pci_dev, f);
|
|
| 628 | 635 |
ivshmem_use_msix(proxy); |
| 629 | 636 |
} else {
|
| 630 | 637 |
proxy->intrstatus = qemu_get_be32(f); |
| ... | ... | |
| 682 | 689 |
migrate_add_blocker(s->migration_blocker); |
| 683 | 690 |
} |
| 684 | 691 |
|
| 685 |
pci_conf = s->dev.config;
|
|
| 692 |
pci_conf = dev->config;
|
|
| 686 | 693 |
pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
| 687 | 694 |
|
| 688 | 695 |
pci_config_set_interrupt_pin(pci_conf, 1); |
| ... | ... | |
| 693 | 700 |
"ivshmem-mmio", IVSHMEM_REG_BAR_SIZE); |
| 694 | 701 |
|
| 695 | 702 |
/* region for registers*/ |
| 696 |
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
|
|
| 703 |
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, |
|
| 697 | 704 |
&s->ivshmem_mmio); |
| 698 | 705 |
|
| 699 | 706 |
memory_region_init(&s->bar, OBJECT(s), "ivshmem-bar2-container", s->ivshmem_size); |
| ... | ... | |
| 727 | 734 |
/* allocate/initialize space for interrupt handling */ |
| 728 | 735 |
s->peers = g_malloc0(s->nb_peers * sizeof(Peer)); |
| 729 | 736 |
|
| 730 |
pci_register_bar(&s->dev, 2, s->ivshmem_attr, &s->bar);
|
|
| 737 |
pci_register_bar(dev, 2, s->ivshmem_attr, &s->bar); |
|
| 731 | 738 |
|
| 732 | 739 |
s->eventfd_chr = g_malloc0(s->vectors * sizeof(CharDriverState *)); |
| 733 | 740 |
|
| ... | ... | |
| 768 | 775 |
|
| 769 | 776 |
} |
| 770 | 777 |
|
| 771 |
s->dev.config_write = ivshmem_write_config;
|
|
| 778 |
dev->config_write = ivshmem_write_config;
|
|
| 772 | 779 |
|
| 773 | 780 |
return 0; |
| 774 | 781 |
} |
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