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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 translation
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3 | 5fafdf24 | ths | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
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18 | fdf9b3e8 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | fdf9b3e8 | bellard | */
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20 | fdf9b3e8 | bellard | #include <stdarg.h> |
21 | fdf9b3e8 | bellard | #include <stdlib.h> |
22 | fdf9b3e8 | bellard | #include <stdio.h> |
23 | fdf9b3e8 | bellard | #include <string.h> |
24 | fdf9b3e8 | bellard | #include <inttypes.h> |
25 | fdf9b3e8 | bellard | #include <assert.h> |
26 | fdf9b3e8 | bellard | |
27 | fdf9b3e8 | bellard | #define DEBUG_DISAS
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28 | fdf9b3e8 | bellard | #define SH4_DEBUG_DISAS
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29 | fdf9b3e8 | bellard | //#define SH4_SINGLE_STEP
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30 | fdf9b3e8 | bellard | |
31 | fdf9b3e8 | bellard | #include "cpu.h" |
32 | fdf9b3e8 | bellard | #include "exec-all.h" |
33 | fdf9b3e8 | bellard | #include "disas.h" |
34 | 57fec1fe | bellard | #include "tcg-op.h" |
35 | ca10f867 | aurel32 | #include "qemu-common.h" |
36 | fdf9b3e8 | bellard | |
37 | a7812ae4 | pbrook | #include "helper.h" |
38 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
39 | a7812ae4 | pbrook | #include "helper.h" |
40 | a7812ae4 | pbrook | |
41 | fdf9b3e8 | bellard | typedef struct DisasContext { |
42 | fdf9b3e8 | bellard | struct TranslationBlock *tb;
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43 | fdf9b3e8 | bellard | target_ulong pc; |
44 | fdf9b3e8 | bellard | uint32_t sr; |
45 | eda9b09b | bellard | uint32_t fpscr; |
46 | fdf9b3e8 | bellard | uint16_t opcode; |
47 | fdf9b3e8 | bellard | uint32_t flags; |
48 | 823029f9 | ths | int bstate;
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49 | fdf9b3e8 | bellard | int memidx;
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50 | fdf9b3e8 | bellard | uint32_t delayed_pc; |
51 | fdf9b3e8 | bellard | int singlestep_enabled;
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52 | fdf9b3e8 | bellard | } DisasContext; |
53 | fdf9b3e8 | bellard | |
54 | fe25591e | aurel32 | #if defined(CONFIG_USER_ONLY)
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55 | fe25591e | aurel32 | #define IS_USER(ctx) 1 |
56 | fe25591e | aurel32 | #else
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57 | fe25591e | aurel32 | #define IS_USER(ctx) (!(ctx->sr & SR_MD))
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58 | fe25591e | aurel32 | #endif
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59 | fe25591e | aurel32 | |
60 | 823029f9 | ths | enum {
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61 | 823029f9 | ths | BS_NONE = 0, /* We go out of the TB without reaching a branch or an |
62 | 823029f9 | ths | * exception condition
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63 | 823029f9 | ths | */
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64 | 823029f9 | ths | BS_STOP = 1, /* We want to stop translation for any reason */ |
65 | 823029f9 | ths | BS_BRANCH = 2, /* We reached a branch condition */ |
66 | 823029f9 | ths | BS_EXCP = 3, /* We reached an exception condition */ |
67 | 823029f9 | ths | }; |
68 | 823029f9 | ths | |
69 | 1e8864f7 | aurel32 | /* global register indexes */
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70 | a7812ae4 | pbrook | static TCGv_ptr cpu_env;
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71 | 1e8864f7 | aurel32 | static TCGv cpu_gregs[24]; |
72 | 3a8a44c4 | aurel32 | static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
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73 | 3a8a44c4 | aurel32 | static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
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74 | b79e1752 | aurel32 | static TCGv cpu_pr, cpu_fpscr, cpu_fpul;
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75 | 66ba317c | aurel32 | static TCGv cpu_fregs[32]; |
76 | 1000822b | aurel32 | |
77 | 1000822b | aurel32 | /* internal register indexes */
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78 | 1000822b | aurel32 | static TCGv cpu_flags, cpu_delayed_pc;
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79 | 1e8864f7 | aurel32 | |
80 | 2e70f6ef | pbrook | #include "gen-icount.h" |
81 | 2e70f6ef | pbrook | |
82 | a5f1b965 | blueswir1 | static void sh4_translate_init(void) |
83 | 2e70f6ef | pbrook | { |
84 | 1e8864f7 | aurel32 | int i;
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85 | 2e70f6ef | pbrook | static int done_init = 0; |
86 | 559dd74d | aurel32 | static const char * const gregnames[24] = { |
87 | 1e8864f7 | aurel32 | "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0", |
88 | 1e8864f7 | aurel32 | "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0", |
89 | 1e8864f7 | aurel32 | "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", |
90 | 1e8864f7 | aurel32 | "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1", |
91 | 1e8864f7 | aurel32 | "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1" |
92 | 1e8864f7 | aurel32 | }; |
93 | 66ba317c | aurel32 | static const char * const fregnames[32] = { |
94 | 66ba317c | aurel32 | "FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0", |
95 | 66ba317c | aurel32 | "FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0", |
96 | 66ba317c | aurel32 | "FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0", |
97 | 66ba317c | aurel32 | "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0", |
98 | 66ba317c | aurel32 | "FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1", |
99 | 66ba317c | aurel32 | "FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1", |
100 | 66ba317c | aurel32 | "FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1", |
101 | 66ba317c | aurel32 | "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1", |
102 | 66ba317c | aurel32 | }; |
103 | 1e8864f7 | aurel32 | |
104 | 2e70f6ef | pbrook | if (done_init)
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105 | 2e70f6ef | pbrook | return;
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106 | 1e8864f7 | aurel32 | |
107 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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108 | 1e8864f7 | aurel32 | |
109 | 1e8864f7 | aurel32 | for (i = 0; i < 24; i++) |
110 | a7812ae4 | pbrook | cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0, |
111 | 66ba317c | aurel32 | offsetof(CPUState, gregs[i]), |
112 | 66ba317c | aurel32 | gregnames[i]); |
113 | 988d7eaa | aurel32 | |
114 | a7812ae4 | pbrook | cpu_pc = tcg_global_mem_new_i32(TCG_AREG0, |
115 | a7812ae4 | pbrook | offsetof(CPUState, pc), "PC");
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116 | a7812ae4 | pbrook | cpu_sr = tcg_global_mem_new_i32(TCG_AREG0, |
117 | a7812ae4 | pbrook | offsetof(CPUState, sr), "SR");
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118 | a7812ae4 | pbrook | cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0, |
119 | a7812ae4 | pbrook | offsetof(CPUState, ssr), "SSR");
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120 | a7812ae4 | pbrook | cpu_spc = tcg_global_mem_new_i32(TCG_AREG0, |
121 | a7812ae4 | pbrook | offsetof(CPUState, spc), "SPC");
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122 | a7812ae4 | pbrook | cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0, |
123 | a7812ae4 | pbrook | offsetof(CPUState, gbr), "GBR");
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124 | a7812ae4 | pbrook | cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0, |
125 | a7812ae4 | pbrook | offsetof(CPUState, vbr), "VBR");
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126 | a7812ae4 | pbrook | cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0, |
127 | a7812ae4 | pbrook | offsetof(CPUState, sgr), "SGR");
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128 | a7812ae4 | pbrook | cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0, |
129 | a7812ae4 | pbrook | offsetof(CPUState, dbr), "DBR");
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130 | a7812ae4 | pbrook | cpu_mach = tcg_global_mem_new_i32(TCG_AREG0, |
131 | a7812ae4 | pbrook | offsetof(CPUState, mach), "MACH");
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132 | a7812ae4 | pbrook | cpu_macl = tcg_global_mem_new_i32(TCG_AREG0, |
133 | a7812ae4 | pbrook | offsetof(CPUState, macl), "MACL");
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134 | a7812ae4 | pbrook | cpu_pr = tcg_global_mem_new_i32(TCG_AREG0, |
135 | a7812ae4 | pbrook | offsetof(CPUState, pr), "PR");
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136 | a7812ae4 | pbrook | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, |
137 | a7812ae4 | pbrook | offsetof(CPUState, fpscr), "FPSCR");
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138 | a7812ae4 | pbrook | cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0, |
139 | a7812ae4 | pbrook | offsetof(CPUState, fpul), "FPUL");
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140 | a7812ae4 | pbrook | |
141 | a7812ae4 | pbrook | cpu_flags = tcg_global_mem_new_i32(TCG_AREG0, |
142 | a7812ae4 | pbrook | offsetof(CPUState, flags), "_flags_");
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143 | a7812ae4 | pbrook | cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0, |
144 | a7812ae4 | pbrook | offsetof(CPUState, delayed_pc), |
145 | a7812ae4 | pbrook | "_delayed_pc_");
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146 | 1000822b | aurel32 | |
147 | 66ba317c | aurel32 | for (i = 0; i < 32; i++) |
148 | 66ba317c | aurel32 | cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0, |
149 | 66ba317c | aurel32 | offsetof(CPUState, fregs[i]), |
150 | 66ba317c | aurel32 | fregnames[i]); |
151 | 66ba317c | aurel32 | |
152 | 988d7eaa | aurel32 | /* register helpers */
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153 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
154 | 988d7eaa | aurel32 | #include "helper.h" |
155 | 988d7eaa | aurel32 | |
156 | 2e70f6ef | pbrook | done_init = 1;
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157 | 2e70f6ef | pbrook | } |
158 | 2e70f6ef | pbrook | |
159 | fdf9b3e8 | bellard | void cpu_dump_state(CPUState * env, FILE * f,
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160 | fdf9b3e8 | bellard | int (*cpu_fprintf) (FILE * f, const char *fmt, ...), |
161 | fdf9b3e8 | bellard | int flags)
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162 | fdf9b3e8 | bellard | { |
163 | fdf9b3e8 | bellard | int i;
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164 | eda9b09b | bellard | cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
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165 | eda9b09b | bellard | env->pc, env->sr, env->pr, env->fpscr); |
166 | 274a9e70 | aurel32 | cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
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167 | 274a9e70 | aurel32 | env->spc, env->ssr, env->gbr, env->vbr); |
168 | 274a9e70 | aurel32 | cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
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169 | 274a9e70 | aurel32 | env->sgr, env->dbr, env->delayed_pc, env->fpul); |
170 | fdf9b3e8 | bellard | for (i = 0; i < 24; i += 4) { |
171 | fdf9b3e8 | bellard | cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
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172 | fdf9b3e8 | bellard | i, env->gregs[i], i + 1, env->gregs[i + 1], |
173 | fdf9b3e8 | bellard | i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); |
174 | fdf9b3e8 | bellard | } |
175 | fdf9b3e8 | bellard | if (env->flags & DELAY_SLOT) {
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176 | fdf9b3e8 | bellard | cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
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177 | fdf9b3e8 | bellard | env->delayed_pc); |
178 | fdf9b3e8 | bellard | } else if (env->flags & DELAY_SLOT_CONDITIONAL) { |
179 | fdf9b3e8 | bellard | cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
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180 | fdf9b3e8 | bellard | env->delayed_pc); |
181 | fdf9b3e8 | bellard | } |
182 | fdf9b3e8 | bellard | } |
183 | fdf9b3e8 | bellard | |
184 | b79e1752 | aurel32 | static void cpu_sh4_reset(CPUSH4State * env) |
185 | fdf9b3e8 | bellard | { |
186 | 9c2a9ea1 | pbrook | #if defined(CONFIG_USER_ONLY)
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187 | 4c909d14 | ths | env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */
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188 | 9c2a9ea1 | pbrook | #else
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189 | fdf9b3e8 | bellard | env->sr = 0x700000F0; /* MD, RB, BL, I3-I0 */ |
190 | 9c2a9ea1 | pbrook | #endif
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191 | fdf9b3e8 | bellard | env->vbr = 0;
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192 | fdf9b3e8 | bellard | env->pc = 0xA0000000;
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193 | ea6cf6be | ths | #if defined(CONFIG_USER_ONLY)
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194 | ea6cf6be | ths | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
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195 | b0b3de89 | bellard | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
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196 | ea6cf6be | ths | #else
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197 | ea6cf6be | ths | env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */ |
198 | b0b3de89 | bellard | set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
199 | ea6cf6be | ths | #endif
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200 | fdf9b3e8 | bellard | env->mmucr = 0;
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201 | fdf9b3e8 | bellard | } |
202 | fdf9b3e8 | bellard | |
203 | 0fd3ca30 | aurel32 | typedef struct { |
204 | b55266b5 | blueswir1 | const char *name; |
205 | 0fd3ca30 | aurel32 | int id;
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206 | 0fd3ca30 | aurel32 | uint32_t pvr; |
207 | 0fd3ca30 | aurel32 | uint32_t prr; |
208 | 0fd3ca30 | aurel32 | uint32_t cvr; |
209 | 0fd3ca30 | aurel32 | } sh4_def_t; |
210 | 0fd3ca30 | aurel32 | |
211 | 0fd3ca30 | aurel32 | static sh4_def_t sh4_defs[] = {
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212 | 0fd3ca30 | aurel32 | { |
213 | 0fd3ca30 | aurel32 | .name = "SH7750R",
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214 | 0fd3ca30 | aurel32 | .id = SH_CPU_SH7750R, |
215 | 0fd3ca30 | aurel32 | .pvr = 0x00050000,
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216 | 0fd3ca30 | aurel32 | .prr = 0x00000100,
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217 | 0fd3ca30 | aurel32 | .cvr = 0x00110000,
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218 | 0fd3ca30 | aurel32 | }, { |
219 | 0fd3ca30 | aurel32 | .name = "SH7751R",
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220 | 0fd3ca30 | aurel32 | .id = SH_CPU_SH7751R, |
221 | 0fd3ca30 | aurel32 | .pvr = 0x04050005,
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222 | 0fd3ca30 | aurel32 | .prr = 0x00000113,
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223 | 0fd3ca30 | aurel32 | .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */ |
224 | 0fd3ca30 | aurel32 | }, |
225 | 0fd3ca30 | aurel32 | }; |
226 | 0fd3ca30 | aurel32 | |
227 | b55266b5 | blueswir1 | static const sh4_def_t *cpu_sh4_find_by_name(const char *name) |
228 | 0fd3ca30 | aurel32 | { |
229 | 0fd3ca30 | aurel32 | int i;
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230 | 0fd3ca30 | aurel32 | |
231 | 0fd3ca30 | aurel32 | if (strcasecmp(name, "any") == 0) |
232 | 0fd3ca30 | aurel32 | return &sh4_defs[0]; |
233 | 0fd3ca30 | aurel32 | |
234 | 0fd3ca30 | aurel32 | for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++) |
235 | 0fd3ca30 | aurel32 | if (strcasecmp(name, sh4_defs[i].name) == 0) |
236 | 0fd3ca30 | aurel32 | return &sh4_defs[i];
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237 | 0fd3ca30 | aurel32 | |
238 | 0fd3ca30 | aurel32 | return NULL; |
239 | 0fd3ca30 | aurel32 | } |
240 | 0fd3ca30 | aurel32 | |
241 | 0fd3ca30 | aurel32 | void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
242 | 0fd3ca30 | aurel32 | { |
243 | 0fd3ca30 | aurel32 | int i;
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244 | 0fd3ca30 | aurel32 | |
245 | 0fd3ca30 | aurel32 | for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++) |
246 | 0fd3ca30 | aurel32 | (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
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247 | 0fd3ca30 | aurel32 | } |
248 | 0fd3ca30 | aurel32 | |
249 | 1ed1a787 | blueswir1 | static void cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def) |
250 | 0fd3ca30 | aurel32 | { |
251 | 0fd3ca30 | aurel32 | env->pvr = def->pvr; |
252 | 0fd3ca30 | aurel32 | env->prr = def->prr; |
253 | 0fd3ca30 | aurel32 | env->cvr = def->cvr; |
254 | 0fd3ca30 | aurel32 | env->id = def->id; |
255 | 0fd3ca30 | aurel32 | } |
256 | 0fd3ca30 | aurel32 | |
257 | aaed909a | bellard | CPUSH4State *cpu_sh4_init(const char *cpu_model) |
258 | fdf9b3e8 | bellard | { |
259 | fdf9b3e8 | bellard | CPUSH4State *env; |
260 | 0fd3ca30 | aurel32 | const sh4_def_t *def;
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261 | fdf9b3e8 | bellard | |
262 | 0fd3ca30 | aurel32 | def = cpu_sh4_find_by_name(cpu_model); |
263 | 0fd3ca30 | aurel32 | if (!def)
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264 | 0fd3ca30 | aurel32 | return NULL; |
265 | fdf9b3e8 | bellard | env = qemu_mallocz(sizeof(CPUSH4State));
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266 | fdf9b3e8 | bellard | if (!env)
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267 | fdf9b3e8 | bellard | return NULL; |
268 | fdf9b3e8 | bellard | cpu_exec_init(env); |
269 | 2e70f6ef | pbrook | sh4_translate_init(); |
270 | 7478757e | aurel32 | env->cpu_model_str = cpu_model; |
271 | fdf9b3e8 | bellard | cpu_sh4_reset(env); |
272 | 0fd3ca30 | aurel32 | cpu_sh4_register(env, def); |
273 | fdf9b3e8 | bellard | tlb_flush(env, 1);
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274 | fdf9b3e8 | bellard | return env;
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275 | fdf9b3e8 | bellard | } |
276 | fdf9b3e8 | bellard | |
277 | fdf9b3e8 | bellard | static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) |
278 | fdf9b3e8 | bellard | { |
279 | fdf9b3e8 | bellard | TranslationBlock *tb; |
280 | fdf9b3e8 | bellard | tb = ctx->tb; |
281 | fdf9b3e8 | bellard | |
282 | fdf9b3e8 | bellard | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
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283 | fdf9b3e8 | bellard | !ctx->singlestep_enabled) { |
284 | fdf9b3e8 | bellard | /* Use a direct jump if in same page and singlestep not enabled */
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285 | 57fec1fe | bellard | tcg_gen_goto_tb(n); |
286 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_pc, dest); |
287 | 57fec1fe | bellard | tcg_gen_exit_tb((long) tb + n);
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288 | fdf9b3e8 | bellard | } else {
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289 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_pc, dest); |
290 | 57fec1fe | bellard | if (ctx->singlestep_enabled)
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291 | a7812ae4 | pbrook | gen_helper_debug(); |
292 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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293 | fdf9b3e8 | bellard | } |
294 | fdf9b3e8 | bellard | } |
295 | fdf9b3e8 | bellard | |
296 | fdf9b3e8 | bellard | static void gen_jump(DisasContext * ctx) |
297 | fdf9b3e8 | bellard | { |
298 | fdf9b3e8 | bellard | if (ctx->delayed_pc == (uint32_t) - 1) { |
299 | fdf9b3e8 | bellard | /* Target is not statically known, it comes necessarily from a
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300 | fdf9b3e8 | bellard | delayed jump as immediate jump are conditinal jumps */
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301 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); |
302 | fdf9b3e8 | bellard | if (ctx->singlestep_enabled)
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303 | a7812ae4 | pbrook | gen_helper_debug(); |
304 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
305 | fdf9b3e8 | bellard | } else {
|
306 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 0, ctx->delayed_pc);
|
307 | fdf9b3e8 | bellard | } |
308 | fdf9b3e8 | bellard | } |
309 | fdf9b3e8 | bellard | |
310 | 1000822b | aurel32 | static inline void gen_branch_slot(uint32_t delayed_pc, int t) |
311 | 1000822b | aurel32 | { |
312 | c55497ec | aurel32 | TCGv sr; |
313 | 1000822b | aurel32 | int label = gen_new_label();
|
314 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc); |
315 | a7812ae4 | pbrook | sr = tcg_temp_new(); |
316 | c55497ec | aurel32 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
317 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label);
|
318 | 1000822b | aurel32 | tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
319 | 1000822b | aurel32 | gen_set_label(label); |
320 | 1000822b | aurel32 | } |
321 | 1000822b | aurel32 | |
322 | fdf9b3e8 | bellard | /* Immediate conditional jump (bt or bf) */
|
323 | fdf9b3e8 | bellard | static void gen_conditional_jump(DisasContext * ctx, |
324 | fdf9b3e8 | bellard | target_ulong ift, target_ulong ifnott) |
325 | fdf9b3e8 | bellard | { |
326 | fdf9b3e8 | bellard | int l1;
|
327 | c55497ec | aurel32 | TCGv sr; |
328 | fdf9b3e8 | bellard | |
329 | fdf9b3e8 | bellard | l1 = gen_new_label(); |
330 | a7812ae4 | pbrook | sr = tcg_temp_new(); |
331 | c55497ec | aurel32 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
332 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1); |
333 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 0, ifnott);
|
334 | fdf9b3e8 | bellard | gen_set_label(l1); |
335 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 1, ift);
|
336 | fdf9b3e8 | bellard | } |
337 | fdf9b3e8 | bellard | |
338 | fdf9b3e8 | bellard | /* Delayed conditional jump (bt or bf) */
|
339 | fdf9b3e8 | bellard | static void gen_delayed_conditional_jump(DisasContext * ctx) |
340 | fdf9b3e8 | bellard | { |
341 | fdf9b3e8 | bellard | int l1;
|
342 | c55497ec | aurel32 | TCGv ds; |
343 | fdf9b3e8 | bellard | |
344 | fdf9b3e8 | bellard | l1 = gen_new_label(); |
345 | a7812ae4 | pbrook | ds = tcg_temp_new(); |
346 | c55497ec | aurel32 | tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE); |
347 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1); |
348 | 823029f9 | ths | gen_goto_tb(ctx, 1, ctx->pc + 2); |
349 | fdf9b3e8 | bellard | gen_set_label(l1); |
350 | 1000822b | aurel32 | tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE); |
351 | 9c2a9ea1 | pbrook | gen_jump(ctx); |
352 | fdf9b3e8 | bellard | } |
353 | fdf9b3e8 | bellard | |
354 | a4625612 | aurel32 | static inline void gen_set_t(void) |
355 | a4625612 | aurel32 | { |
356 | a4625612 | aurel32 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); |
357 | a4625612 | aurel32 | } |
358 | a4625612 | aurel32 | |
359 | a4625612 | aurel32 | static inline void gen_clr_t(void) |
360 | a4625612 | aurel32 | { |
361 | a4625612 | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
362 | a4625612 | aurel32 | } |
363 | a4625612 | aurel32 | |
364 | a4625612 | aurel32 | static inline void gen_cmp(int cond, TCGv t0, TCGv t1) |
365 | a4625612 | aurel32 | { |
366 | a4625612 | aurel32 | int label1 = gen_new_label();
|
367 | a4625612 | aurel32 | int label2 = gen_new_label();
|
368 | a4625612 | aurel32 | tcg_gen_brcond_i32(cond, t1, t0, label1); |
369 | a4625612 | aurel32 | gen_clr_t(); |
370 | a4625612 | aurel32 | tcg_gen_br(label2); |
371 | a4625612 | aurel32 | gen_set_label(label1); |
372 | a4625612 | aurel32 | gen_set_t(); |
373 | a4625612 | aurel32 | gen_set_label(label2); |
374 | a4625612 | aurel32 | } |
375 | a4625612 | aurel32 | |
376 | a4625612 | aurel32 | static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm) |
377 | a4625612 | aurel32 | { |
378 | a4625612 | aurel32 | int label1 = gen_new_label();
|
379 | a4625612 | aurel32 | int label2 = gen_new_label();
|
380 | a4625612 | aurel32 | tcg_gen_brcondi_i32(cond, t0, imm, label1); |
381 | a4625612 | aurel32 | gen_clr_t(); |
382 | a4625612 | aurel32 | tcg_gen_br(label2); |
383 | a4625612 | aurel32 | gen_set_label(label1); |
384 | a4625612 | aurel32 | gen_set_t(); |
385 | a4625612 | aurel32 | gen_set_label(label2); |
386 | a4625612 | aurel32 | } |
387 | a4625612 | aurel32 | |
388 | 1000822b | aurel32 | static inline void gen_store_flags(uint32_t flags) |
389 | 1000822b | aurel32 | { |
390 | 1000822b | aurel32 | tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
391 | 1000822b | aurel32 | tcg_gen_ori_i32(cpu_flags, cpu_flags, flags); |
392 | 1000822b | aurel32 | } |
393 | 1000822b | aurel32 | |
394 | 69d6275b | aurel32 | static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1) |
395 | 69d6275b | aurel32 | { |
396 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
397 | 69d6275b | aurel32 | |
398 | 69d6275b | aurel32 | p0 &= 0x1f;
|
399 | 69d6275b | aurel32 | p1 &= 0x1f;
|
400 | 69d6275b | aurel32 | |
401 | 69d6275b | aurel32 | tcg_gen_andi_i32(tmp, t1, (1 << p1));
|
402 | 69d6275b | aurel32 | tcg_gen_andi_i32(t0, t0, ~(1 << p0));
|
403 | 69d6275b | aurel32 | if (p0 < p1)
|
404 | 69d6275b | aurel32 | tcg_gen_shri_i32(tmp, tmp, p1 - p0); |
405 | 69d6275b | aurel32 | else if (p0 > p1) |
406 | 69d6275b | aurel32 | tcg_gen_shli_i32(tmp, tmp, p0 - p1); |
407 | 69d6275b | aurel32 | tcg_gen_or_i32(t0, t0, tmp); |
408 | 69d6275b | aurel32 | |
409 | 69d6275b | aurel32 | tcg_temp_free(tmp); |
410 | 69d6275b | aurel32 | } |
411 | 69d6275b | aurel32 | |
412 | a7812ae4 | pbrook | static inline void gen_load_fpr64(TCGv_i64 t, int reg) |
413 | cc4ba6a9 | aurel32 | { |
414 | 66ba317c | aurel32 | tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
|
415 | cc4ba6a9 | aurel32 | } |
416 | cc4ba6a9 | aurel32 | |
417 | a7812ae4 | pbrook | static inline void gen_store_fpr64 (TCGv_i64 t, int reg) |
418 | cc4ba6a9 | aurel32 | { |
419 | a7812ae4 | pbrook | TCGv_i32 tmp = tcg_temp_new_i32(); |
420 | cc4ba6a9 | aurel32 | tcg_gen_trunc_i64_i32(tmp, t); |
421 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
|
422 | cc4ba6a9 | aurel32 | tcg_gen_shri_i64(t, t, 32);
|
423 | cc4ba6a9 | aurel32 | tcg_gen_trunc_i64_i32(tmp, t); |
424 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fregs[reg], tmp); |
425 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp); |
426 | cc4ba6a9 | aurel32 | } |
427 | cc4ba6a9 | aurel32 | |
428 | fdf9b3e8 | bellard | #define B3_0 (ctx->opcode & 0xf) |
429 | fdf9b3e8 | bellard | #define B6_4 ((ctx->opcode >> 4) & 0x7) |
430 | fdf9b3e8 | bellard | #define B7_4 ((ctx->opcode >> 4) & 0xf) |
431 | fdf9b3e8 | bellard | #define B7_0 (ctx->opcode & 0xff) |
432 | fdf9b3e8 | bellard | #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff)) |
433 | fdf9b3e8 | bellard | #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \ |
434 | fdf9b3e8 | bellard | (ctx->opcode & 0xfff))
|
435 | fdf9b3e8 | bellard | #define B11_8 ((ctx->opcode >> 8) & 0xf) |
436 | fdf9b3e8 | bellard | #define B15_12 ((ctx->opcode >> 12) & 0xf) |
437 | fdf9b3e8 | bellard | |
438 | fdf9b3e8 | bellard | #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \ |
439 | 7efbe241 | aurel32 | (cpu_gregs[x + 16]) : (cpu_gregs[x]))
|
440 | fdf9b3e8 | bellard | |
441 | fdf9b3e8 | bellard | #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \ |
442 | 7efbe241 | aurel32 | ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
|
443 | fdf9b3e8 | bellard | |
444 | eda9b09b | bellard | #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
445 | f09111e0 | ths | #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
446 | eda9b09b | bellard | #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) |
447 | ea6cf6be | ths | #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ |
448 | eda9b09b | bellard | |
449 | fdf9b3e8 | bellard | #define CHECK_NOT_DELAY_SLOT \
|
450 | d8299bcc | aurel32 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
|
451 | d8299bcc | aurel32 | { \ |
452 | d8299bcc | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx->pc-2); \
|
453 | d8299bcc | aurel32 | gen_helper_raise_slot_illegal_instruction(); \ |
454 | d8299bcc | aurel32 | ctx->bstate = BS_EXCP; \ |
455 | d8299bcc | aurel32 | return; \
|
456 | d8299bcc | aurel32 | } |
457 | fdf9b3e8 | bellard | |
458 | fe25591e | aurel32 | #define CHECK_PRIVILEGED \
|
459 | fe25591e | aurel32 | if (IS_USER(ctx)) { \
|
460 | d8299bcc | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx->pc); \ |
461 | a7812ae4 | pbrook | gen_helper_raise_illegal_instruction(); \ |
462 | fe25591e | aurel32 | ctx->bstate = BS_EXCP; \ |
463 | fe25591e | aurel32 | return; \
|
464 | fe25591e | aurel32 | } |
465 | fe25591e | aurel32 | |
466 | d8299bcc | aurel32 | #define CHECK_FPU_ENABLED \
|
467 | d8299bcc | aurel32 | if (ctx->flags & SR_FD) { \
|
468 | d8299bcc | aurel32 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
|
469 | d8299bcc | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx->pc-2); \
|
470 | d8299bcc | aurel32 | gen_helper_raise_slot_fpu_disable(); \ |
471 | d8299bcc | aurel32 | } else { \
|
472 | d8299bcc | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx->pc); \ |
473 | d8299bcc | aurel32 | gen_helper_raise_fpu_disable(); \ |
474 | d8299bcc | aurel32 | } \ |
475 | d8299bcc | aurel32 | ctx->bstate = BS_EXCP; \ |
476 | d8299bcc | aurel32 | return; \
|
477 | d8299bcc | aurel32 | } |
478 | d8299bcc | aurel32 | |
479 | b1d8e52e | blueswir1 | static void _decode_opc(DisasContext * ctx) |
480 | fdf9b3e8 | bellard | { |
481 | fdf9b3e8 | bellard | #if 0
|
482 | fdf9b3e8 | bellard | fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
|
483 | fdf9b3e8 | bellard | #endif
|
484 | fdf9b3e8 | bellard | switch (ctx->opcode) {
|
485 | fdf9b3e8 | bellard | case 0x0019: /* div0u */ |
486 | 3a8a44c4 | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T)); |
487 | fdf9b3e8 | bellard | return;
|
488 | fdf9b3e8 | bellard | case 0x000b: /* rts */ |
489 | 1000822b | aurel32 | CHECK_NOT_DELAY_SLOT |
490 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr); |
491 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
492 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
493 | fdf9b3e8 | bellard | return;
|
494 | fdf9b3e8 | bellard | case 0x0028: /* clrmac */ |
495 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_mach, 0);
|
496 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_macl, 0);
|
497 | fdf9b3e8 | bellard | return;
|
498 | fdf9b3e8 | bellard | case 0x0048: /* clrs */ |
499 | 3a8a44c4 | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S); |
500 | fdf9b3e8 | bellard | return;
|
501 | fdf9b3e8 | bellard | case 0x0008: /* clrt */ |
502 | a4625612 | aurel32 | gen_clr_t(); |
503 | fdf9b3e8 | bellard | return;
|
504 | fdf9b3e8 | bellard | case 0x0038: /* ldtlb */ |
505 | fe25591e | aurel32 | CHECK_PRIVILEGED |
506 | a7812ae4 | pbrook | gen_helper_ldtlb(); |
507 | fdf9b3e8 | bellard | return;
|
508 | c5e814b2 | ths | case 0x002b: /* rte */ |
509 | fe25591e | aurel32 | CHECK_PRIVILEGED |
510 | 1000822b | aurel32 | CHECK_NOT_DELAY_SLOT |
511 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_sr, cpu_ssr); |
512 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); |
513 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
514 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
515 | fdf9b3e8 | bellard | return;
|
516 | fdf9b3e8 | bellard | case 0x0058: /* sets */ |
517 | 3a8a44c4 | aurel32 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S); |
518 | fdf9b3e8 | bellard | return;
|
519 | fdf9b3e8 | bellard | case 0x0018: /* sett */ |
520 | a4625612 | aurel32 | gen_set_t(); |
521 | fdf9b3e8 | bellard | return;
|
522 | 24988dc2 | aurel32 | case 0xfbfd: /* frchg */ |
523 | 6f06939b | aurel32 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); |
524 | 823029f9 | ths | ctx->bstate = BS_STOP; |
525 | fdf9b3e8 | bellard | return;
|
526 | 24988dc2 | aurel32 | case 0xf3fd: /* fschg */ |
527 | 6f06939b | aurel32 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ); |
528 | 823029f9 | ths | ctx->bstate = BS_STOP; |
529 | fdf9b3e8 | bellard | return;
|
530 | fdf9b3e8 | bellard | case 0x0009: /* nop */ |
531 | fdf9b3e8 | bellard | return;
|
532 | fdf9b3e8 | bellard | case 0x001b: /* sleep */ |
533 | fe25591e | aurel32 | CHECK_PRIVILEGED |
534 | a7812ae4 | pbrook | gen_helper_sleep(tcg_const_i32(ctx->pc + 2));
|
535 | fdf9b3e8 | bellard | return;
|
536 | fdf9b3e8 | bellard | } |
537 | fdf9b3e8 | bellard | |
538 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf000) { |
539 | fdf9b3e8 | bellard | case 0x1000: /* mov.l Rm,@(disp,Rn) */ |
540 | c55497ec | aurel32 | { |
541 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
542 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
|
543 | c55497ec | aurel32 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
544 | c55497ec | aurel32 | tcg_temp_free(addr); |
545 | c55497ec | aurel32 | } |
546 | fdf9b3e8 | bellard | return;
|
547 | fdf9b3e8 | bellard | case 0x5000: /* mov.l @(disp,Rm),Rn */ |
548 | c55497ec | aurel32 | { |
549 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
550 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
|
551 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); |
552 | c55497ec | aurel32 | tcg_temp_free(addr); |
553 | c55497ec | aurel32 | } |
554 | fdf9b3e8 | bellard | return;
|
555 | 24988dc2 | aurel32 | case 0xe000: /* mov #imm,Rn */ |
556 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(B11_8), B7_0s); |
557 | fdf9b3e8 | bellard | return;
|
558 | fdf9b3e8 | bellard | case 0x9000: /* mov.w @(disp,PC),Rn */ |
559 | c55497ec | aurel32 | { |
560 | c55497ec | aurel32 | TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2); |
561 | c55497ec | aurel32 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); |
562 | c55497ec | aurel32 | tcg_temp_free(addr); |
563 | c55497ec | aurel32 | } |
564 | fdf9b3e8 | bellard | return;
|
565 | fdf9b3e8 | bellard | case 0xd000: /* mov.l @(disp,PC),Rn */ |
566 | c55497ec | aurel32 | { |
567 | c55497ec | aurel32 | TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3); |
568 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); |
569 | c55497ec | aurel32 | tcg_temp_free(addr); |
570 | c55497ec | aurel32 | } |
571 | fdf9b3e8 | bellard | return;
|
572 | 24988dc2 | aurel32 | case 0x7000: /* add #imm,Rn */ |
573 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s); |
574 | fdf9b3e8 | bellard | return;
|
575 | fdf9b3e8 | bellard | case 0xa000: /* bra disp */ |
576 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
577 | 1000822b | aurel32 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; |
578 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); |
579 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
580 | fdf9b3e8 | bellard | return;
|
581 | fdf9b3e8 | bellard | case 0xb000: /* bsr disp */ |
582 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
583 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
|
584 | 1000822b | aurel32 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; |
585 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); |
586 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
587 | fdf9b3e8 | bellard | return;
|
588 | fdf9b3e8 | bellard | } |
589 | fdf9b3e8 | bellard | |
590 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf00f) { |
591 | fdf9b3e8 | bellard | case 0x6003: /* mov Rm,Rn */ |
592 | 7efbe241 | aurel32 | tcg_gen_mov_i32(REG(B11_8), REG(B7_4)); |
593 | fdf9b3e8 | bellard | return;
|
594 | fdf9b3e8 | bellard | case 0x2000: /* mov.b Rm,@Rn */ |
595 | 7efbe241 | aurel32 | tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx); |
596 | fdf9b3e8 | bellard | return;
|
597 | fdf9b3e8 | bellard | case 0x2001: /* mov.w Rm,@Rn */ |
598 | 7efbe241 | aurel32 | tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx); |
599 | fdf9b3e8 | bellard | return;
|
600 | fdf9b3e8 | bellard | case 0x2002: /* mov.l Rm,@Rn */ |
601 | 7efbe241 | aurel32 | tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx); |
602 | fdf9b3e8 | bellard | return;
|
603 | fdf9b3e8 | bellard | case 0x6000: /* mov.b @Rm,Rn */ |
604 | 7efbe241 | aurel32 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
605 | fdf9b3e8 | bellard | return;
|
606 | fdf9b3e8 | bellard | case 0x6001: /* mov.w @Rm,Rn */ |
607 | 7efbe241 | aurel32 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
608 | fdf9b3e8 | bellard | return;
|
609 | fdf9b3e8 | bellard | case 0x6002: /* mov.l @Rm,Rn */ |
610 | 7efbe241 | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
611 | fdf9b3e8 | bellard | return;
|
612 | fdf9b3e8 | bellard | case 0x2004: /* mov.b Rm,@-Rn */ |
613 | c55497ec | aurel32 | { |
614 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
615 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 1);
|
616 | c55497ec | aurel32 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */
|
617 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */ |
618 | c55497ec | aurel32 | tcg_temp_free(addr); |
619 | c55497ec | aurel32 | } |
620 | fdf9b3e8 | bellard | return;
|
621 | fdf9b3e8 | bellard | case 0x2005: /* mov.w Rm,@-Rn */ |
622 | c55497ec | aurel32 | { |
623 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
624 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 2);
|
625 | c55497ec | aurel32 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); |
626 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);
|
627 | c55497ec | aurel32 | tcg_temp_free(addr); |
628 | c55497ec | aurel32 | } |
629 | fdf9b3e8 | bellard | return;
|
630 | fdf9b3e8 | bellard | case 0x2006: /* mov.l Rm,@-Rn */ |
631 | c55497ec | aurel32 | { |
632 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
633 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
634 | c55497ec | aurel32 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
635 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
636 | c55497ec | aurel32 | } |
637 | fdf9b3e8 | bellard | return;
|
638 | eda9b09b | bellard | case 0x6004: /* mov.b @Rm+,Rn */ |
639 | 7efbe241 | aurel32 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
640 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
641 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
|
642 | fdf9b3e8 | bellard | return;
|
643 | fdf9b3e8 | bellard | case 0x6005: /* mov.w @Rm+,Rn */ |
644 | 7efbe241 | aurel32 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
645 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
646 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
|
647 | fdf9b3e8 | bellard | return;
|
648 | fdf9b3e8 | bellard | case 0x6006: /* mov.l @Rm+,Rn */ |
649 | 7efbe241 | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
650 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
651 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
|
652 | fdf9b3e8 | bellard | return;
|
653 | fdf9b3e8 | bellard | case 0x0004: /* mov.b Rm,@(R0,Rn) */ |
654 | c55497ec | aurel32 | { |
655 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
656 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B11_8), REG(0));
|
657 | c55497ec | aurel32 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); |
658 | c55497ec | aurel32 | tcg_temp_free(addr); |
659 | c55497ec | aurel32 | } |
660 | fdf9b3e8 | bellard | return;
|
661 | fdf9b3e8 | bellard | case 0x0005: /* mov.w Rm,@(R0,Rn) */ |
662 | c55497ec | aurel32 | { |
663 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
664 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B11_8), REG(0));
|
665 | c55497ec | aurel32 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); |
666 | c55497ec | aurel32 | tcg_temp_free(addr); |
667 | c55497ec | aurel32 | } |
668 | fdf9b3e8 | bellard | return;
|
669 | fdf9b3e8 | bellard | case 0x0006: /* mov.l Rm,@(R0,Rn) */ |
670 | c55497ec | aurel32 | { |
671 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
672 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B11_8), REG(0));
|
673 | c55497ec | aurel32 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
674 | c55497ec | aurel32 | tcg_temp_free(addr); |
675 | c55497ec | aurel32 | } |
676 | fdf9b3e8 | bellard | return;
|
677 | fdf9b3e8 | bellard | case 0x000c: /* mov.b @(R0,Rm),Rn */ |
678 | c55497ec | aurel32 | { |
679 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
680 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B7_4), REG(0));
|
681 | c55497ec | aurel32 | tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx); |
682 | c55497ec | aurel32 | tcg_temp_free(addr); |
683 | c55497ec | aurel32 | } |
684 | fdf9b3e8 | bellard | return;
|
685 | fdf9b3e8 | bellard | case 0x000d: /* mov.w @(R0,Rm),Rn */ |
686 | c55497ec | aurel32 | { |
687 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
688 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B7_4), REG(0));
|
689 | c55497ec | aurel32 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); |
690 | c55497ec | aurel32 | tcg_temp_free(addr); |
691 | c55497ec | aurel32 | } |
692 | fdf9b3e8 | bellard | return;
|
693 | fdf9b3e8 | bellard | case 0x000e: /* mov.l @(R0,Rm),Rn */ |
694 | c55497ec | aurel32 | { |
695 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
696 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B7_4), REG(0));
|
697 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); |
698 | c55497ec | aurel32 | tcg_temp_free(addr); |
699 | c55497ec | aurel32 | } |
700 | fdf9b3e8 | bellard | return;
|
701 | fdf9b3e8 | bellard | case 0x6008: /* swap.b Rm,Rn */ |
702 | c55497ec | aurel32 | { |
703 | c69e3264 | aurel32 | TCGv highw, high, low; |
704 | a7812ae4 | pbrook | highw = tcg_temp_new(); |
705 | c69e3264 | aurel32 | tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000);
|
706 | a7812ae4 | pbrook | high = tcg_temp_new(); |
707 | c55497ec | aurel32 | tcg_gen_ext8u_i32(high, REG(B7_4)); |
708 | c55497ec | aurel32 | tcg_gen_shli_i32(high, high, 8);
|
709 | a7812ae4 | pbrook | low = tcg_temp_new(); |
710 | c55497ec | aurel32 | tcg_gen_shri_i32(low, REG(B7_4), 8);
|
711 | c55497ec | aurel32 | tcg_gen_ext8u_i32(low, low); |
712 | c55497ec | aurel32 | tcg_gen_or_i32(REG(B11_8), high, low); |
713 | c69e3264 | aurel32 | tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw); |
714 | c55497ec | aurel32 | tcg_temp_free(low); |
715 | c55497ec | aurel32 | tcg_temp_free(high); |
716 | c55497ec | aurel32 | } |
717 | fdf9b3e8 | bellard | return;
|
718 | fdf9b3e8 | bellard | case 0x6009: /* swap.w Rm,Rn */ |
719 | c55497ec | aurel32 | { |
720 | c55497ec | aurel32 | TCGv high, low; |
721 | a7812ae4 | pbrook | high = tcg_temp_new(); |
722 | c55497ec | aurel32 | tcg_gen_ext16u_i32(high, REG(B7_4)); |
723 | c55497ec | aurel32 | tcg_gen_shli_i32(high, high, 16);
|
724 | a7812ae4 | pbrook | low = tcg_temp_new(); |
725 | c55497ec | aurel32 | tcg_gen_shri_i32(low, REG(B7_4), 16);
|
726 | c55497ec | aurel32 | tcg_gen_ext16u_i32(low, low); |
727 | c55497ec | aurel32 | tcg_gen_or_i32(REG(B11_8), high, low); |
728 | c55497ec | aurel32 | tcg_temp_free(low); |
729 | c55497ec | aurel32 | tcg_temp_free(high); |
730 | c55497ec | aurel32 | } |
731 | fdf9b3e8 | bellard | return;
|
732 | fdf9b3e8 | bellard | case 0x200d: /* xtrct Rm,Rn */ |
733 | c55497ec | aurel32 | { |
734 | c55497ec | aurel32 | TCGv high, low; |
735 | a7812ae4 | pbrook | high = tcg_temp_new(); |
736 | c55497ec | aurel32 | tcg_gen_ext16u_i32(high, REG(B7_4)); |
737 | c55497ec | aurel32 | tcg_gen_shli_i32(high, high, 16);
|
738 | a7812ae4 | pbrook | low = tcg_temp_new(); |
739 | c55497ec | aurel32 | tcg_gen_shri_i32(low, REG(B11_8), 16);
|
740 | c55497ec | aurel32 | tcg_gen_ext16u_i32(low, low); |
741 | c55497ec | aurel32 | tcg_gen_or_i32(REG(B11_8), high, low); |
742 | c55497ec | aurel32 | tcg_temp_free(low); |
743 | c55497ec | aurel32 | tcg_temp_free(high); |
744 | c55497ec | aurel32 | } |
745 | fdf9b3e8 | bellard | return;
|
746 | fdf9b3e8 | bellard | case 0x300c: /* add Rm,Rn */ |
747 | 7efbe241 | aurel32 | tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
748 | fdf9b3e8 | bellard | return;
|
749 | fdf9b3e8 | bellard | case 0x300e: /* addc Rm,Rn */ |
750 | a7812ae4 | pbrook | gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8)); |
751 | fdf9b3e8 | bellard | return;
|
752 | fdf9b3e8 | bellard | case 0x300f: /* addv Rm,Rn */ |
753 | a7812ae4 | pbrook | gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8)); |
754 | fdf9b3e8 | bellard | return;
|
755 | fdf9b3e8 | bellard | case 0x2009: /* and Rm,Rn */ |
756 | 7efbe241 | aurel32 | tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
757 | fdf9b3e8 | bellard | return;
|
758 | fdf9b3e8 | bellard | case 0x3000: /* cmp/eq Rm,Rn */ |
759 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8)); |
760 | fdf9b3e8 | bellard | return;
|
761 | fdf9b3e8 | bellard | case 0x3003: /* cmp/ge Rm,Rn */ |
762 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8)); |
763 | fdf9b3e8 | bellard | return;
|
764 | fdf9b3e8 | bellard | case 0x3007: /* cmp/gt Rm,Rn */ |
765 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8)); |
766 | fdf9b3e8 | bellard | return;
|
767 | fdf9b3e8 | bellard | case 0x3006: /* cmp/hi Rm,Rn */ |
768 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8)); |
769 | fdf9b3e8 | bellard | return;
|
770 | fdf9b3e8 | bellard | case 0x3002: /* cmp/hs Rm,Rn */ |
771 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8)); |
772 | fdf9b3e8 | bellard | return;
|
773 | fdf9b3e8 | bellard | case 0x200c: /* cmp/str Rm,Rn */ |
774 | 69d6275b | aurel32 | { |
775 | 69d6275b | aurel32 | int label1 = gen_new_label();
|
776 | 69d6275b | aurel32 | int label2 = gen_new_label();
|
777 | c55497ec | aurel32 | TCGv cmp1 = tcg_temp_local_new(TCG_TYPE_I32); |
778 | c55497ec | aurel32 | TCGv cmp2 = tcg_temp_local_new(TCG_TYPE_I32); |
779 | c55497ec | aurel32 | tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8)); |
780 | c55497ec | aurel32 | tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
|
781 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
|
782 | c55497ec | aurel32 | tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
|
783 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
|
784 | c55497ec | aurel32 | tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
|
785 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
|
786 | c55497ec | aurel32 | tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
|
787 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
|
788 | 69d6275b | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
789 | 69d6275b | aurel32 | tcg_gen_br(label2); |
790 | 69d6275b | aurel32 | gen_set_label(label1); |
791 | 69d6275b | aurel32 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); |
792 | 69d6275b | aurel32 | gen_set_label(label2); |
793 | c55497ec | aurel32 | tcg_temp_free(cmp2); |
794 | c55497ec | aurel32 | tcg_temp_free(cmp1); |
795 | 69d6275b | aurel32 | } |
796 | fdf9b3e8 | bellard | return;
|
797 | fdf9b3e8 | bellard | case 0x2007: /* div0s Rm,Rn */ |
798 | c55497ec | aurel32 | { |
799 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */ |
800 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */ |
801 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
802 | c55497ec | aurel32 | tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8)); |
803 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */ |
804 | c55497ec | aurel32 | tcg_temp_free(val); |
805 | c55497ec | aurel32 | } |
806 | fdf9b3e8 | bellard | return;
|
807 | fdf9b3e8 | bellard | case 0x3004: /* div1 Rm,Rn */ |
808 | a7812ae4 | pbrook | gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8)); |
809 | fdf9b3e8 | bellard | return;
|
810 | fdf9b3e8 | bellard | case 0x300d: /* dmuls.l Rm,Rn */ |
811 | 6f06939b | aurel32 | { |
812 | a7812ae4 | pbrook | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
813 | a7812ae4 | pbrook | TCGv_i64 tmp2 = tcg_temp_new_i64(); |
814 | 6f06939b | aurel32 | |
815 | 7efbe241 | aurel32 | tcg_gen_ext_i32_i64(tmp1, REG(B7_4)); |
816 | 7efbe241 | aurel32 | tcg_gen_ext_i32_i64(tmp2, REG(B11_8)); |
817 | 6f06939b | aurel32 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
818 | 6f06939b | aurel32 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); |
819 | 6f06939b | aurel32 | tcg_gen_shri_i64(tmp1, tmp1, 32);
|
820 | 6f06939b | aurel32 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); |
821 | 6f06939b | aurel32 | |
822 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp2); |
823 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp1); |
824 | 6f06939b | aurel32 | } |
825 | fdf9b3e8 | bellard | return;
|
826 | fdf9b3e8 | bellard | case 0x3005: /* dmulu.l Rm,Rn */ |
827 | 6f06939b | aurel32 | { |
828 | a7812ae4 | pbrook | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
829 | a7812ae4 | pbrook | TCGv_i64 tmp2 = tcg_temp_new_i64(); |
830 | 6f06939b | aurel32 | |
831 | 7efbe241 | aurel32 | tcg_gen_extu_i32_i64(tmp1, REG(B7_4)); |
832 | 7efbe241 | aurel32 | tcg_gen_extu_i32_i64(tmp2, REG(B11_8)); |
833 | 6f06939b | aurel32 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
834 | 6f06939b | aurel32 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); |
835 | 6f06939b | aurel32 | tcg_gen_shri_i64(tmp1, tmp1, 32);
|
836 | 6f06939b | aurel32 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); |
837 | 6f06939b | aurel32 | |
838 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp2); |
839 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp1); |
840 | 6f06939b | aurel32 | } |
841 | fdf9b3e8 | bellard | return;
|
842 | fdf9b3e8 | bellard | case 0x600e: /* exts.b Rm,Rn */ |
843 | 7efbe241 | aurel32 | tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4)); |
844 | fdf9b3e8 | bellard | return;
|
845 | fdf9b3e8 | bellard | case 0x600f: /* exts.w Rm,Rn */ |
846 | 7efbe241 | aurel32 | tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4)); |
847 | fdf9b3e8 | bellard | return;
|
848 | fdf9b3e8 | bellard | case 0x600c: /* extu.b Rm,Rn */ |
849 | 7efbe241 | aurel32 | tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4)); |
850 | fdf9b3e8 | bellard | return;
|
851 | fdf9b3e8 | bellard | case 0x600d: /* extu.w Rm,Rn */ |
852 | 7efbe241 | aurel32 | tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4)); |
853 | fdf9b3e8 | bellard | return;
|
854 | 24988dc2 | aurel32 | case 0x000f: /* mac.l @Rm+,@Rn+ */ |
855 | c55497ec | aurel32 | { |
856 | c55497ec | aurel32 | TCGv arg0, arg1; |
857 | a7812ae4 | pbrook | arg0 = tcg_temp_new(); |
858 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
859 | a7812ae4 | pbrook | arg1 = tcg_temp_new(); |
860 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
861 | a7812ae4 | pbrook | gen_helper_macl(arg0, arg1); |
862 | c55497ec | aurel32 | tcg_temp_free(arg1); |
863 | c55497ec | aurel32 | tcg_temp_free(arg0); |
864 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
|
865 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
866 | c55497ec | aurel32 | } |
867 | fdf9b3e8 | bellard | return;
|
868 | fdf9b3e8 | bellard | case 0x400f: /* mac.w @Rm+,@Rn+ */ |
869 | c55497ec | aurel32 | { |
870 | c55497ec | aurel32 | TCGv arg0, arg1; |
871 | a7812ae4 | pbrook | arg0 = tcg_temp_new(); |
872 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
873 | a7812ae4 | pbrook | arg1 = tcg_temp_new(); |
874 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
875 | a7812ae4 | pbrook | gen_helper_macw(arg0, arg1); |
876 | c55497ec | aurel32 | tcg_temp_free(arg1); |
877 | c55497ec | aurel32 | tcg_temp_free(arg0); |
878 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
|
879 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
|
880 | c55497ec | aurel32 | } |
881 | fdf9b3e8 | bellard | return;
|
882 | fdf9b3e8 | bellard | case 0x0007: /* mul.l Rm,Rn */ |
883 | 7efbe241 | aurel32 | tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8)); |
884 | fdf9b3e8 | bellard | return;
|
885 | fdf9b3e8 | bellard | case 0x200f: /* muls.w Rm,Rn */ |
886 | c55497ec | aurel32 | { |
887 | c55497ec | aurel32 | TCGv arg0, arg1; |
888 | a7812ae4 | pbrook | arg0 = tcg_temp_new(); |
889 | c55497ec | aurel32 | tcg_gen_ext16s_i32(arg0, REG(B7_4)); |
890 | a7812ae4 | pbrook | arg1 = tcg_temp_new(); |
891 | c55497ec | aurel32 | tcg_gen_ext16s_i32(arg1, REG(B11_8)); |
892 | c55497ec | aurel32 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); |
893 | c55497ec | aurel32 | tcg_temp_free(arg1); |
894 | c55497ec | aurel32 | tcg_temp_free(arg0); |
895 | c55497ec | aurel32 | } |
896 | fdf9b3e8 | bellard | return;
|
897 | fdf9b3e8 | bellard | case 0x200e: /* mulu.w Rm,Rn */ |
898 | c55497ec | aurel32 | { |
899 | c55497ec | aurel32 | TCGv arg0, arg1; |
900 | a7812ae4 | pbrook | arg0 = tcg_temp_new(); |
901 | c55497ec | aurel32 | tcg_gen_ext16u_i32(arg0, REG(B7_4)); |
902 | a7812ae4 | pbrook | arg1 = tcg_temp_new(); |
903 | c55497ec | aurel32 | tcg_gen_ext16u_i32(arg1, REG(B11_8)); |
904 | c55497ec | aurel32 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); |
905 | c55497ec | aurel32 | tcg_temp_free(arg1); |
906 | c55497ec | aurel32 | tcg_temp_free(arg0); |
907 | c55497ec | aurel32 | } |
908 | fdf9b3e8 | bellard | return;
|
909 | fdf9b3e8 | bellard | case 0x600b: /* neg Rm,Rn */ |
910 | 7efbe241 | aurel32 | tcg_gen_neg_i32(REG(B11_8), REG(B7_4)); |
911 | fdf9b3e8 | bellard | return;
|
912 | fdf9b3e8 | bellard | case 0x600a: /* negc Rm,Rn */ |
913 | a7812ae4 | pbrook | gen_helper_negc(REG(B11_8), REG(B7_4)); |
914 | fdf9b3e8 | bellard | return;
|
915 | fdf9b3e8 | bellard | case 0x6007: /* not Rm,Rn */ |
916 | 7efbe241 | aurel32 | tcg_gen_not_i32(REG(B11_8), REG(B7_4)); |
917 | fdf9b3e8 | bellard | return;
|
918 | fdf9b3e8 | bellard | case 0x200b: /* or Rm,Rn */ |
919 | 7efbe241 | aurel32 | tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
920 | fdf9b3e8 | bellard | return;
|
921 | fdf9b3e8 | bellard | case 0x400c: /* shad Rm,Rn */ |
922 | 69d6275b | aurel32 | { |
923 | 69d6275b | aurel32 | int label1 = gen_new_label();
|
924 | 69d6275b | aurel32 | int label2 = gen_new_label();
|
925 | 69d6275b | aurel32 | int label3 = gen_new_label();
|
926 | 69d6275b | aurel32 | int label4 = gen_new_label();
|
927 | c55497ec | aurel32 | TCGv shift = tcg_temp_local_new(TCG_TYPE_I32); |
928 | 7efbe241 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
|
929 | 69d6275b | aurel32 | /* Rm positive, shift to the left */
|
930 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
|
931 | c55497ec | aurel32 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); |
932 | 69d6275b | aurel32 | tcg_gen_br(label4); |
933 | 69d6275b | aurel32 | /* Rm negative, shift to the right */
|
934 | 69d6275b | aurel32 | gen_set_label(label1); |
935 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
|
936 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
|
937 | c55497ec | aurel32 | tcg_gen_not_i32(shift, REG(B7_4)); |
938 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, shift, 0x1f);
|
939 | c55497ec | aurel32 | tcg_gen_addi_i32(shift, shift, 1);
|
940 | c55497ec | aurel32 | tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift); |
941 | 69d6275b | aurel32 | tcg_gen_br(label4); |
942 | 69d6275b | aurel32 | /* Rm = -32 */
|
943 | 69d6275b | aurel32 | gen_set_label(label2); |
944 | 7efbe241 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3);
|
945 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(B11_8), 0);
|
946 | 69d6275b | aurel32 | tcg_gen_br(label4); |
947 | 69d6275b | aurel32 | gen_set_label(label3); |
948 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
|
949 | 69d6275b | aurel32 | gen_set_label(label4); |
950 | c55497ec | aurel32 | tcg_temp_free(shift); |
951 | 69d6275b | aurel32 | } |
952 | fdf9b3e8 | bellard | return;
|
953 | fdf9b3e8 | bellard | case 0x400d: /* shld Rm,Rn */ |
954 | 69d6275b | aurel32 | { |
955 | 69d6275b | aurel32 | int label1 = gen_new_label();
|
956 | 69d6275b | aurel32 | int label2 = gen_new_label();
|
957 | 69d6275b | aurel32 | int label3 = gen_new_label();
|
958 | c55497ec | aurel32 | TCGv shift = tcg_temp_local_new(TCG_TYPE_I32); |
959 | 7efbe241 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
|
960 | 69d6275b | aurel32 | /* Rm positive, shift to the left */
|
961 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
|
962 | c55497ec | aurel32 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); |
963 | 69d6275b | aurel32 | tcg_gen_br(label3); |
964 | 69d6275b | aurel32 | /* Rm negative, shift to the right */
|
965 | 69d6275b | aurel32 | gen_set_label(label1); |
966 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
|
967 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
|
968 | c55497ec | aurel32 | tcg_gen_not_i32(shift, REG(B7_4)); |
969 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, shift, 0x1f);
|
970 | c55497ec | aurel32 | tcg_gen_addi_i32(shift, shift, 1);
|
971 | c55497ec | aurel32 | tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift); |
972 | 69d6275b | aurel32 | tcg_gen_br(label3); |
973 | 69d6275b | aurel32 | /* Rm = -32 */
|
974 | 69d6275b | aurel32 | gen_set_label(label2); |
975 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(B11_8), 0);
|
976 | 69d6275b | aurel32 | gen_set_label(label3); |
977 | c55497ec | aurel32 | tcg_temp_free(shift); |
978 | 69d6275b | aurel32 | } |
979 | fdf9b3e8 | bellard | return;
|
980 | fdf9b3e8 | bellard | case 0x3008: /* sub Rm,Rn */ |
981 | 7efbe241 | aurel32 | tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
982 | fdf9b3e8 | bellard | return;
|
983 | fdf9b3e8 | bellard | case 0x300a: /* subc Rm,Rn */ |
984 | a7812ae4 | pbrook | gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8)); |
985 | fdf9b3e8 | bellard | return;
|
986 | fdf9b3e8 | bellard | case 0x300b: /* subv Rm,Rn */ |
987 | a7812ae4 | pbrook | gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8)); |
988 | fdf9b3e8 | bellard | return;
|
989 | fdf9b3e8 | bellard | case 0x2008: /* tst Rm,Rn */ |
990 | c55497ec | aurel32 | { |
991 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
992 | c55497ec | aurel32 | tcg_gen_and_i32(val, REG(B7_4), REG(B11_8)); |
993 | c55497ec | aurel32 | gen_cmp_imm(TCG_COND_EQ, val, 0);
|
994 | c55497ec | aurel32 | tcg_temp_free(val); |
995 | c55497ec | aurel32 | } |
996 | fdf9b3e8 | bellard | return;
|
997 | fdf9b3e8 | bellard | case 0x200a: /* xor Rm,Rn */ |
998 | 7efbe241 | aurel32 | tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
999 | fdf9b3e8 | bellard | return;
|
1000 | e67888a7 | ths | case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ |
1001 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1002 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1003 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, XREG(B7_4)); |
1004 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, XREG(B11_8)); |
1005 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1006 | eda9b09b | bellard | } else {
|
1007 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1008 | eda9b09b | bellard | } |
1009 | eda9b09b | bellard | return;
|
1010 | e67888a7 | ths | case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ |
1011 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1012 | 11bb09f1 | aurel32 | TCGv addr_hi = tcg_temp_new(); |
1013 | 11bb09f1 | aurel32 | int fr = XREG(B7_4);
|
1014 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
|
1015 | 11bb09f1 | aurel32 | tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx); |
1016 | 11bb09f1 | aurel32 | tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
|
1017 | 11bb09f1 | aurel32 | tcg_temp_free(addr_hi); |
1018 | eda9b09b | bellard | } else {
|
1019 | 66ba317c | aurel32 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx); |
1020 | eda9b09b | bellard | } |
1021 | eda9b09b | bellard | return;
|
1022 | e67888a7 | ths | case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ |
1023 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1024 | 11bb09f1 | aurel32 | TCGv addr_hi = tcg_temp_new(); |
1025 | 11bb09f1 | aurel32 | int fr = XREG(B11_8);
|
1026 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
|
1027 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); |
1028 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
|
1029 | 11bb09f1 | aurel32 | tcg_temp_free(addr_hi); |
1030 | eda9b09b | bellard | } else {
|
1031 | 66ba317c | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); |
1032 | eda9b09b | bellard | } |
1033 | eda9b09b | bellard | return;
|
1034 | e67888a7 | ths | case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ |
1035 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1036 | 11bb09f1 | aurel32 | TCGv addr_hi = tcg_temp_new(); |
1037 | 11bb09f1 | aurel32 | int fr = XREG(B11_8);
|
1038 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
|
1039 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); |
1040 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
|
1041 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
|
1042 | 11bb09f1 | aurel32 | tcg_temp_free(addr_hi); |
1043 | eda9b09b | bellard | } else {
|
1044 | 66ba317c | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); |
1045 | cc4ba6a9 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
|
1046 | eda9b09b | bellard | } |
1047 | eda9b09b | bellard | return;
|
1048 | e67888a7 | ths | case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ |
1049 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1050 | 11bb09f1 | aurel32 | TCGv addr = tcg_temp_new_i32(); |
1051 | 11bb09f1 | aurel32 | int fr = XREG(B7_4);
|
1052 | 11bb09f1 | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1053 | 11bb09f1 | aurel32 | tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
|
1054 | cc4ba6a9 | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 8);
|
1055 | 11bb09f1 | aurel32 | tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx); |
1056 | 11bb09f1 | aurel32 | tcg_gen_mov_i32(REG(B11_8), addr); |
1057 | cc4ba6a9 | aurel32 | tcg_temp_free(addr); |
1058 | eda9b09b | bellard | } else {
|
1059 | a7812ae4 | pbrook | TCGv addr; |
1060 | a7812ae4 | pbrook | addr = tcg_temp_new_i32(); |
1061 | cc4ba6a9 | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1062 | 66ba317c | aurel32 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
1063 | cc4ba6a9 | aurel32 | tcg_temp_free(addr); |
1064 | 7efbe241 | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
1065 | eda9b09b | bellard | } |
1066 | eda9b09b | bellard | return;
|
1067 | e67888a7 | ths | case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ |
1068 | cc4ba6a9 | aurel32 | { |
1069 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new_i32(); |
1070 | cc4ba6a9 | aurel32 | tcg_gen_add_i32(addr, REG(B7_4), REG(0));
|
1071 | cc4ba6a9 | aurel32 | if (ctx->fpscr & FPSCR_SZ) {
|
1072 | 11bb09f1 | aurel32 | int fr = XREG(B11_8);
|
1073 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); |
1074 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr, addr, 4);
|
1075 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
|
1076 | cc4ba6a9 | aurel32 | } else {
|
1077 | 66ba317c | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx); |
1078 | cc4ba6a9 | aurel32 | } |
1079 | cc4ba6a9 | aurel32 | tcg_temp_free(addr); |
1080 | eda9b09b | bellard | } |
1081 | eda9b09b | bellard | return;
|
1082 | e67888a7 | ths | case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ |
1083 | cc4ba6a9 | aurel32 | { |
1084 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1085 | cc4ba6a9 | aurel32 | tcg_gen_add_i32(addr, REG(B11_8), REG(0));
|
1086 | cc4ba6a9 | aurel32 | if (ctx->fpscr & FPSCR_SZ) {
|
1087 | 11bb09f1 | aurel32 | int fr = XREG(B7_4);
|
1088 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); |
1089 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr, addr, 4);
|
1090 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
|
1091 | cc4ba6a9 | aurel32 | } else {
|
1092 | 66ba317c | aurel32 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
1093 | cc4ba6a9 | aurel32 | } |
1094 | cc4ba6a9 | aurel32 | tcg_temp_free(addr); |
1095 | eda9b09b | bellard | } |
1096 | eda9b09b | bellard | return;
|
1097 | e67888a7 | ths | case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1098 | e67888a7 | ths | case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1099 | e67888a7 | ths | case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1100 | e67888a7 | ths | case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1101 | e67888a7 | ths | case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
1102 | e67888a7 | ths | case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
1103 | cc4ba6a9 | aurel32 | { |
1104 | cc4ba6a9 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1105 | a7812ae4 | pbrook | TCGv_i64 fp0, fp1; |
1106 | a7812ae4 | pbrook | |
1107 | cc4ba6a9 | aurel32 | if (ctx->opcode & 0x0110) |
1108 | cc4ba6a9 | aurel32 | break; /* illegal instruction */ |
1109 | a7812ae4 | pbrook | fp0 = tcg_temp_new_i64(); |
1110 | a7812ae4 | pbrook | fp1 = tcg_temp_new_i64(); |
1111 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp0, DREG(B11_8)); |
1112 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp1, DREG(B7_4)); |
1113 | a7812ae4 | pbrook | switch (ctx->opcode & 0xf00f) { |
1114 | a7812ae4 | pbrook | case 0xf000: /* fadd Rm,Rn */ |
1115 | a7812ae4 | pbrook | gen_helper_fadd_DT(fp0, fp0, fp1); |
1116 | a7812ae4 | pbrook | break;
|
1117 | a7812ae4 | pbrook | case 0xf001: /* fsub Rm,Rn */ |
1118 | a7812ae4 | pbrook | gen_helper_fsub_DT(fp0, fp0, fp1); |
1119 | a7812ae4 | pbrook | break;
|
1120 | a7812ae4 | pbrook | case 0xf002: /* fmul Rm,Rn */ |
1121 | a7812ae4 | pbrook | gen_helper_fmul_DT(fp0, fp0, fp1); |
1122 | a7812ae4 | pbrook | break;
|
1123 | a7812ae4 | pbrook | case 0xf003: /* fdiv Rm,Rn */ |
1124 | a7812ae4 | pbrook | gen_helper_fdiv_DT(fp0, fp0, fp1); |
1125 | a7812ae4 | pbrook | break;
|
1126 | a7812ae4 | pbrook | case 0xf004: /* fcmp/eq Rm,Rn */ |
1127 | a7812ae4 | pbrook | gen_helper_fcmp_eq_DT(fp0, fp1); |
1128 | a7812ae4 | pbrook | return;
|
1129 | a7812ae4 | pbrook | case 0xf005: /* fcmp/gt Rm,Rn */ |
1130 | a7812ae4 | pbrook | gen_helper_fcmp_gt_DT(fp0, fp1); |
1131 | a7812ae4 | pbrook | return;
|
1132 | a7812ae4 | pbrook | } |
1133 | a7812ae4 | pbrook | gen_store_fpr64(fp0, DREG(B11_8)); |
1134 | a7812ae4 | pbrook | tcg_temp_free_i64(fp0); |
1135 | a7812ae4 | pbrook | tcg_temp_free_i64(fp1); |
1136 | a7812ae4 | pbrook | } else {
|
1137 | a7812ae4 | pbrook | switch (ctx->opcode & 0xf00f) { |
1138 | a7812ae4 | pbrook | case 0xf000: /* fadd Rm,Rn */ |
1139 | 66ba317c | aurel32 | gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1140 | a7812ae4 | pbrook | break;
|
1141 | a7812ae4 | pbrook | case 0xf001: /* fsub Rm,Rn */ |
1142 | 66ba317c | aurel32 | gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1143 | a7812ae4 | pbrook | break;
|
1144 | a7812ae4 | pbrook | case 0xf002: /* fmul Rm,Rn */ |
1145 | 66ba317c | aurel32 | gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1146 | a7812ae4 | pbrook | break;
|
1147 | a7812ae4 | pbrook | case 0xf003: /* fdiv Rm,Rn */ |
1148 | 66ba317c | aurel32 | gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1149 | a7812ae4 | pbrook | break;
|
1150 | a7812ae4 | pbrook | case 0xf004: /* fcmp/eq Rm,Rn */ |
1151 | 66ba317c | aurel32 | gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1152 | a7812ae4 | pbrook | return;
|
1153 | a7812ae4 | pbrook | case 0xf005: /* fcmp/gt Rm,Rn */ |
1154 | 66ba317c | aurel32 | gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1155 | a7812ae4 | pbrook | return;
|
1156 | a7812ae4 | pbrook | } |
1157 | cc4ba6a9 | aurel32 | } |
1158 | ea6cf6be | ths | } |
1159 | ea6cf6be | ths | return;
|
1160 | fdf9b3e8 | bellard | } |
1161 | fdf9b3e8 | bellard | |
1162 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xff00) { |
1163 | fdf9b3e8 | bellard | case 0xc900: /* and #imm,R0 */ |
1164 | 7efbe241 | aurel32 | tcg_gen_andi_i32(REG(0), REG(0), B7_0); |
1165 | fdf9b3e8 | bellard | return;
|
1166 | 24988dc2 | aurel32 | case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
1167 | c55497ec | aurel32 | { |
1168 | c55497ec | aurel32 | TCGv addr, val; |
1169 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
1170 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(0), cpu_gbr);
|
1171 | a7812ae4 | pbrook | val = tcg_temp_new(); |
1172 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1173 | c55497ec | aurel32 | tcg_gen_andi_i32(val, val, B7_0); |
1174 | c55497ec | aurel32 | tcg_gen_qemu_st8(val, addr, ctx->memidx); |
1175 | c55497ec | aurel32 | tcg_temp_free(val); |
1176 | c55497ec | aurel32 | tcg_temp_free(addr); |
1177 | c55497ec | aurel32 | } |
1178 | fdf9b3e8 | bellard | return;
|
1179 | fdf9b3e8 | bellard | case 0x8b00: /* bf label */ |
1180 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
1181 | fdf9b3e8 | bellard | gen_conditional_jump(ctx, ctx->pc + 2,
|
1182 | fdf9b3e8 | bellard | ctx->pc + 4 + B7_0s * 2); |
1183 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1184 | fdf9b3e8 | bellard | return;
|
1185 | fdf9b3e8 | bellard | case 0x8f00: /* bf/s label */ |
1186 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
1187 | 1000822b | aurel32 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0); |
1188 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1189 | fdf9b3e8 | bellard | return;
|
1190 | fdf9b3e8 | bellard | case 0x8900: /* bt label */ |
1191 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
1192 | fdf9b3e8 | bellard | gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, |
1193 | fdf9b3e8 | bellard | ctx->pc + 2);
|
1194 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1195 | fdf9b3e8 | bellard | return;
|
1196 | fdf9b3e8 | bellard | case 0x8d00: /* bt/s label */ |
1197 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
1198 | 1000822b | aurel32 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1); |
1199 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1200 | fdf9b3e8 | bellard | return;
|
1201 | fdf9b3e8 | bellard | case 0x8800: /* cmp/eq #imm,R0 */ |
1202 | 7efbe241 | aurel32 | gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s);
|
1203 | fdf9b3e8 | bellard | return;
|
1204 | fdf9b3e8 | bellard | case 0xc400: /* mov.b @(disp,GBR),R0 */ |
1205 | c55497ec | aurel32 | { |
1206 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1207 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
1208 | c55497ec | aurel32 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
|
1209 | c55497ec | aurel32 | tcg_temp_free(addr); |
1210 | c55497ec | aurel32 | } |
1211 | fdf9b3e8 | bellard | return;
|
1212 | fdf9b3e8 | bellard | case 0xc500: /* mov.w @(disp,GBR),R0 */ |
1213 | c55497ec | aurel32 | { |
1214 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1215 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
|
1216 | c55497ec | aurel32 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
|
1217 | c55497ec | aurel32 | tcg_temp_free(addr); |
1218 | c55497ec | aurel32 | } |
1219 | fdf9b3e8 | bellard | return;
|
1220 | fdf9b3e8 | bellard | case 0xc600: /* mov.l @(disp,GBR),R0 */ |
1221 | c55497ec | aurel32 | { |
1222 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1223 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
|
1224 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);
|
1225 | c55497ec | aurel32 | tcg_temp_free(addr); |
1226 | c55497ec | aurel32 | } |
1227 | fdf9b3e8 | bellard | return;
|
1228 | fdf9b3e8 | bellard | case 0xc000: /* mov.b R0,@(disp,GBR) */ |
1229 | c55497ec | aurel32 | { |
1230 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1231 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
1232 | c55497ec | aurel32 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
|
1233 | c55497ec | aurel32 | tcg_temp_free(addr); |
1234 | c55497ec | aurel32 | } |
1235 | fdf9b3e8 | bellard | return;
|
1236 | fdf9b3e8 | bellard | case 0xc100: /* mov.w R0,@(disp,GBR) */ |
1237 | c55497ec | aurel32 | { |
1238 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1239 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
|
1240 | c55497ec | aurel32 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
|
1241 | c55497ec | aurel32 | tcg_temp_free(addr); |
1242 | c55497ec | aurel32 | } |
1243 | fdf9b3e8 | bellard | return;
|
1244 | fdf9b3e8 | bellard | case 0xc200: /* mov.l R0,@(disp,GBR) */ |
1245 | c55497ec | aurel32 | { |
1246 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1247 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
|
1248 | c55497ec | aurel32 | tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);
|
1249 | c55497ec | aurel32 | tcg_temp_free(addr); |
1250 | c55497ec | aurel32 | } |
1251 | fdf9b3e8 | bellard | return;
|
1252 | fdf9b3e8 | bellard | case 0x8000: /* mov.b R0,@(disp,Rn) */ |
1253 | c55497ec | aurel32 | { |
1254 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1255 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
1256 | c55497ec | aurel32 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
|
1257 | c55497ec | aurel32 | tcg_temp_free(addr); |
1258 | c55497ec | aurel32 | } |
1259 | fdf9b3e8 | bellard | return;
|
1260 | fdf9b3e8 | bellard | case 0x8100: /* mov.w R0,@(disp,Rn) */ |
1261 | c55497ec | aurel32 | { |
1262 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1263 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
|
1264 | c55497ec | aurel32 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
|
1265 | c55497ec | aurel32 | tcg_temp_free(addr); |
1266 | c55497ec | aurel32 | } |
1267 | fdf9b3e8 | bellard | return;
|
1268 | fdf9b3e8 | bellard | case 0x8400: /* mov.b @(disp,Rn),R0 */ |
1269 | c55497ec | aurel32 | { |
1270 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1271 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
1272 | c55497ec | aurel32 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
|
1273 | c55497ec | aurel32 | tcg_temp_free(addr); |
1274 | c55497ec | aurel32 | } |
1275 | fdf9b3e8 | bellard | return;
|
1276 | fdf9b3e8 | bellard | case 0x8500: /* mov.w @(disp,Rn),R0 */ |
1277 | c55497ec | aurel32 | { |
1278 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1279 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
|
1280 | c55497ec | aurel32 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
|
1281 | c55497ec | aurel32 | tcg_temp_free(addr); |
1282 | c55497ec | aurel32 | } |
1283 | fdf9b3e8 | bellard | return;
|
1284 | fdf9b3e8 | bellard | case 0xc700: /* mova @(disp,PC),R0 */ |
1285 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); |
1286 | fdf9b3e8 | bellard | return;
|
1287 | fdf9b3e8 | bellard | case 0xcb00: /* or #imm,R0 */ |
1288 | 7efbe241 | aurel32 | tcg_gen_ori_i32(REG(0), REG(0), B7_0); |
1289 | fdf9b3e8 | bellard | return;
|
1290 | 24988dc2 | aurel32 | case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
1291 | c55497ec | aurel32 | { |
1292 | c55497ec | aurel32 | TCGv addr, val; |
1293 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
1294 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(0), cpu_gbr);
|
1295 | a7812ae4 | pbrook | val = tcg_temp_new(); |
1296 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1297 | c55497ec | aurel32 | tcg_gen_ori_i32(val, val, B7_0); |
1298 | c55497ec | aurel32 | tcg_gen_qemu_st8(val, addr, ctx->memidx); |
1299 | c55497ec | aurel32 | tcg_temp_free(val); |
1300 | c55497ec | aurel32 | tcg_temp_free(addr); |
1301 | c55497ec | aurel32 | } |
1302 | fdf9b3e8 | bellard | return;
|
1303 | fdf9b3e8 | bellard | case 0xc300: /* trapa #imm */ |
1304 | c55497ec | aurel32 | { |
1305 | c55497ec | aurel32 | TCGv imm; |
1306 | c55497ec | aurel32 | CHECK_NOT_DELAY_SLOT |
1307 | c55497ec | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx->pc); |
1308 | c55497ec | aurel32 | imm = tcg_const_i32(B7_0); |
1309 | a7812ae4 | pbrook | gen_helper_trapa(imm); |
1310 | c55497ec | aurel32 | tcg_temp_free(imm); |
1311 | c55497ec | aurel32 | ctx->bstate = BS_BRANCH; |
1312 | c55497ec | aurel32 | } |
1313 | fdf9b3e8 | bellard | return;
|
1314 | fdf9b3e8 | bellard | case 0xc800: /* tst #imm,R0 */ |
1315 | c55497ec | aurel32 | { |
1316 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
1317 | c55497ec | aurel32 | tcg_gen_andi_i32(val, REG(0), B7_0);
|
1318 | c55497ec | aurel32 | gen_cmp_imm(TCG_COND_EQ, val, 0);
|
1319 | c55497ec | aurel32 | tcg_temp_free(val); |
1320 | c55497ec | aurel32 | } |
1321 | fdf9b3e8 | bellard | return;
|
1322 | 24988dc2 | aurel32 | case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
1323 | c55497ec | aurel32 | { |
1324 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
1325 | c55497ec | aurel32 | tcg_gen_add_i32(val, REG(0), cpu_gbr);
|
1326 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, val, ctx->memidx); |
1327 | c55497ec | aurel32 | tcg_gen_andi_i32(val, val, B7_0); |
1328 | c55497ec | aurel32 | gen_cmp_imm(TCG_COND_EQ, val, 0);
|
1329 | c55497ec | aurel32 | tcg_temp_free(val); |
1330 | c55497ec | aurel32 | } |
1331 | fdf9b3e8 | bellard | return;
|
1332 | fdf9b3e8 | bellard | case 0xca00: /* xor #imm,R0 */ |
1333 | 7efbe241 | aurel32 | tcg_gen_xori_i32(REG(0), REG(0), B7_0); |
1334 | fdf9b3e8 | bellard | return;
|
1335 | 24988dc2 | aurel32 | case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
1336 | c55497ec | aurel32 | { |
1337 | c55497ec | aurel32 | TCGv addr, val; |
1338 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
1339 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(0), cpu_gbr);
|
1340 | a7812ae4 | pbrook | val = tcg_temp_new(); |
1341 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1342 | c55497ec | aurel32 | tcg_gen_xori_i32(val, val, B7_0); |
1343 | c55497ec | aurel32 | tcg_gen_qemu_st8(val, addr, ctx->memidx); |
1344 | c55497ec | aurel32 | tcg_temp_free(val); |
1345 | c55497ec | aurel32 | tcg_temp_free(addr); |
1346 | c55497ec | aurel32 | } |
1347 | fdf9b3e8 | bellard | return;
|
1348 | fdf9b3e8 | bellard | } |
1349 | fdf9b3e8 | bellard | |
1350 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf08f) { |
1351 | fdf9b3e8 | bellard | case 0x408e: /* ldc Rm,Rn_BANK */ |
1352 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1353 | 7efbe241 | aurel32 | tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8)); |
1354 | fdf9b3e8 | bellard | return;
|
1355 | fdf9b3e8 | bellard | case 0x4087: /* ldc.l @Rm+,Rn_BANK */ |
1356 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1357 | 7efbe241 | aurel32 | tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx); |
1358 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
1359 | fdf9b3e8 | bellard | return;
|
1360 | fdf9b3e8 | bellard | case 0x0082: /* stc Rm_BANK,Rn */ |
1361 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1362 | 7efbe241 | aurel32 | tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4)); |
1363 | fdf9b3e8 | bellard | return;
|
1364 | fdf9b3e8 | bellard | case 0x4083: /* stc.l Rm_BANK,@-Rn */ |
1365 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1366 | c55497ec | aurel32 | { |
1367 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1368 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1369 | c55497ec | aurel32 | tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx); |
1370 | c55497ec | aurel32 | tcg_temp_free(addr); |
1371 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
1372 | c55497ec | aurel32 | } |
1373 | fdf9b3e8 | bellard | return;
|
1374 | fdf9b3e8 | bellard | } |
1375 | fdf9b3e8 | bellard | |
1376 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf0ff) { |
1377 | fdf9b3e8 | bellard | case 0x0023: /* braf Rn */ |
1378 | 7efbe241 | aurel32 | CHECK_NOT_DELAY_SLOT |
1379 | 7efbe241 | aurel32 | tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);
|
1380 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1381 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1382 | fdf9b3e8 | bellard | return;
|
1383 | fdf9b3e8 | bellard | case 0x0003: /* bsrf Rn */ |
1384 | 7efbe241 | aurel32 | CHECK_NOT_DELAY_SLOT |
1385 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
|
1386 | 7efbe241 | aurel32 | tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr); |
1387 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1388 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1389 | fdf9b3e8 | bellard | return;
|
1390 | fdf9b3e8 | bellard | case 0x4015: /* cmp/pl Rn */ |
1391 | 7efbe241 | aurel32 | gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0);
|
1392 | fdf9b3e8 | bellard | return;
|
1393 | fdf9b3e8 | bellard | case 0x4011: /* cmp/pz Rn */ |
1394 | 7efbe241 | aurel32 | gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0);
|
1395 | fdf9b3e8 | bellard | return;
|
1396 | fdf9b3e8 | bellard | case 0x4010: /* dt Rn */ |
1397 | 7efbe241 | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);
|
1398 | 7efbe241 | aurel32 | gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);
|
1399 | fdf9b3e8 | bellard | return;
|
1400 | fdf9b3e8 | bellard | case 0x402b: /* jmp @Rn */ |
1401 | 7efbe241 | aurel32 | CHECK_NOT_DELAY_SLOT |
1402 | 7efbe241 | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); |
1403 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1404 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1405 | fdf9b3e8 | bellard | return;
|
1406 | fdf9b3e8 | bellard | case 0x400b: /* jsr @Rn */ |
1407 | 7efbe241 | aurel32 | CHECK_NOT_DELAY_SLOT |
1408 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
|
1409 | 7efbe241 | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); |
1410 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1411 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1412 | fdf9b3e8 | bellard | return;
|
1413 | fe25591e | aurel32 | case 0x400e: /* ldc Rm,SR */ |
1414 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1415 | 7efbe241 | aurel32 | tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);
|
1416 | 390af821 | aurel32 | ctx->bstate = BS_STOP; |
1417 | 390af821 | aurel32 | return;
|
1418 | fe25591e | aurel32 | case 0x4007: /* ldc.l @Rm+,SR */ |
1419 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1420 | c55497ec | aurel32 | { |
1421 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
1422 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx); |
1423 | c55497ec | aurel32 | tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);
|
1424 | c55497ec | aurel32 | tcg_temp_free(val); |
1425 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
1426 | c55497ec | aurel32 | ctx->bstate = BS_STOP; |
1427 | c55497ec | aurel32 | } |
1428 | 390af821 | aurel32 | return;
|
1429 | fe25591e | aurel32 | case 0x0002: /* stc SR,Rn */ |
1430 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1431 | 7efbe241 | aurel32 | tcg_gen_mov_i32(REG(B11_8), cpu_sr); |
1432 | 390af821 | aurel32 | return;
|
1433 | fe25591e | aurel32 | case 0x4003: /* stc SR,@-Rn */ |
1434 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1435 | c55497ec | aurel32 | { |
1436 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1437 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1438 | c55497ec | aurel32 | tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx); |
1439 | c55497ec | aurel32 | tcg_temp_free(addr); |
1440 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
1441 | c55497ec | aurel32 | } |
1442 | 390af821 | aurel32 | return;
|
1443 | fe25591e | aurel32 | #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \
|
1444 | fdf9b3e8 | bellard | case ldnum: \
|
1445 | fe25591e | aurel32 | prechk \ |
1446 | 7efbe241 | aurel32 | tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \ |
1447 | fdf9b3e8 | bellard | return; \
|
1448 | fdf9b3e8 | bellard | case ldpnum: \
|
1449 | fe25591e | aurel32 | prechk \ |
1450 | 7efbe241 | aurel32 | tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \ |
1451 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \
|
1452 | fdf9b3e8 | bellard | return; \
|
1453 | fdf9b3e8 | bellard | case stnum: \
|
1454 | fe25591e | aurel32 | prechk \ |
1455 | 7efbe241 | aurel32 | tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \ |
1456 | fdf9b3e8 | bellard | return; \
|
1457 | fdf9b3e8 | bellard | case stpnum: \
|
1458 | fe25591e | aurel32 | prechk \ |
1459 | c55497ec | aurel32 | { \ |
1460 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); \ |
1461 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4); \
|
1462 | c55497ec | aurel32 | tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \ |
1463 | c55497ec | aurel32 | tcg_temp_free(addr); \ |
1464 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \
|
1465 | 86e0abc7 | aurel32 | } \ |
1466 | fdf9b3e8 | bellard | return;
|
1467 | fe25591e | aurel32 | LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) |
1468 | fe25591e | aurel32 | LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED) |
1469 | fe25591e | aurel32 | LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED) |
1470 | fe25591e | aurel32 | LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED) |
1471 | fe25591e | aurel32 | LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED) |
1472 | fe25591e | aurel32 | LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {}) |
1473 | fe25591e | aurel32 | LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {}) |
1474 | fe25591e | aurel32 | LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {}) |
1475 | d8299bcc | aurel32 | LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED}) |
1476 | 390af821 | aurel32 | case 0x406a: /* lds Rm,FPSCR */ |
1477 | d8299bcc | aurel32 | CHECK_FPU_ENABLED |
1478 | a7812ae4 | pbrook | gen_helper_ld_fpscr(REG(B11_8)); |
1479 | 390af821 | aurel32 | ctx->bstate = BS_STOP; |
1480 | 390af821 | aurel32 | return;
|
1481 | 390af821 | aurel32 | case 0x4066: /* lds.l @Rm+,FPSCR */ |
1482 | d8299bcc | aurel32 | CHECK_FPU_ENABLED |
1483 | c55497ec | aurel32 | { |
1484 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1485 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx); |
1486 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
1487 | a7812ae4 | pbrook | gen_helper_ld_fpscr(addr); |
1488 | c55497ec | aurel32 | tcg_temp_free(addr); |
1489 | c55497ec | aurel32 | ctx->bstate = BS_STOP; |
1490 | c55497ec | aurel32 | } |
1491 | 390af821 | aurel32 | return;
|
1492 | 390af821 | aurel32 | case 0x006a: /* sts FPSCR,Rn */ |
1493 | d8299bcc | aurel32 | CHECK_FPU_ENABLED |
1494 | c55497ec | aurel32 | tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff);
|
1495 | 390af821 | aurel32 | return;
|
1496 | 390af821 | aurel32 | case 0x4062: /* sts FPSCR,@-Rn */ |
1497 | d8299bcc | aurel32 | CHECK_FPU_ENABLED |
1498 | c55497ec | aurel32 | { |
1499 | c55497ec | aurel32 | TCGv addr, val; |
1500 | a7812ae4 | pbrook | val = tcg_temp_new(); |
1501 | c55497ec | aurel32 | tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff);
|
1502 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
1503 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1504 | c55497ec | aurel32 | tcg_gen_qemu_st32(val, addr, ctx->memidx); |
1505 | c55497ec | aurel32 | tcg_temp_free(addr); |
1506 | c55497ec | aurel32 | tcg_temp_free(val); |
1507 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
1508 | c55497ec | aurel32 | } |
1509 | 390af821 | aurel32 | return;
|
1510 | fdf9b3e8 | bellard | case 0x00c3: /* movca.l R0,@Rm */ |
1511 | 7efbe241 | aurel32 | tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
|
1512 | fdf9b3e8 | bellard | return;
|
1513 | 7526aa2d | aurel32 | case 0x40a9: |
1514 | 7526aa2d | aurel32 | /* MOVUA.L @Rm,R0 (Rm) -> R0
|
1515 | 7526aa2d | aurel32 | Load non-boundary-aligned data */
|
1516 | 7526aa2d | aurel32 | tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
|
1517 | 7526aa2d | aurel32 | return;
|
1518 | 7526aa2d | aurel32 | case 0x40e9: |
1519 | 7526aa2d | aurel32 | /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm
|
1520 | 7526aa2d | aurel32 | Load non-boundary-aligned data */
|
1521 | 7526aa2d | aurel32 | tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
|
1522 | 7526aa2d | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
1523 | 7526aa2d | aurel32 | return;
|
1524 | fdf9b3e8 | bellard | case 0x0029: /* movt Rn */ |
1525 | 7efbe241 | aurel32 | tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T); |
1526 | fdf9b3e8 | bellard | return;
|
1527 | fdf9b3e8 | bellard | case 0x0093: /* ocbi @Rn */ |
1528 | c55497ec | aurel32 | { |
1529 | a7812ae4 | pbrook | TCGv dummy = tcg_temp_new(); |
1530 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1531 | c55497ec | aurel32 | tcg_temp_free(dummy); |
1532 | c55497ec | aurel32 | } |
1533 | fdf9b3e8 | bellard | return;
|
1534 | 24988dc2 | aurel32 | case 0x00a3: /* ocbp @Rn */ |
1535 | c55497ec | aurel32 | { |
1536 | a7812ae4 | pbrook | TCGv dummy = tcg_temp_new(); |
1537 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1538 | c55497ec | aurel32 | tcg_temp_free(dummy); |
1539 | c55497ec | aurel32 | } |
1540 | fdf9b3e8 | bellard | return;
|
1541 | fdf9b3e8 | bellard | case 0x00b3: /* ocbwb @Rn */ |
1542 | c55497ec | aurel32 | { |
1543 | a7812ae4 | pbrook | TCGv dummy = tcg_temp_new(); |
1544 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1545 | c55497ec | aurel32 | tcg_temp_free(dummy); |
1546 | c55497ec | aurel32 | } |
1547 | fdf9b3e8 | bellard | return;
|
1548 | fdf9b3e8 | bellard | case 0x0083: /* pref @Rn */ |
1549 | fdf9b3e8 | bellard | return;
|
1550 | fdf9b3e8 | bellard | case 0x4024: /* rotcl Rn */ |
1551 | c55497ec | aurel32 | { |
1552 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1553 | c55497ec | aurel32 | tcg_gen_mov_i32(tmp, cpu_sr); |
1554 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1555 | c55497ec | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
1556 | c55497ec | aurel32 | gen_copy_bit_i32(REG(B11_8), 0, tmp, 0); |
1557 | c55497ec | aurel32 | tcg_temp_free(tmp); |
1558 | c55497ec | aurel32 | } |
1559 | fdf9b3e8 | bellard | return;
|
1560 | fdf9b3e8 | bellard | case 0x4025: /* rotcr Rn */ |
1561 | c55497ec | aurel32 | { |
1562 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1563 | c55497ec | aurel32 | tcg_gen_mov_i32(tmp, cpu_sr); |
1564 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1565 | c55497ec | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
1566 | c55497ec | aurel32 | gen_copy_bit_i32(REG(B11_8), 31, tmp, 0); |
1567 | c55497ec | aurel32 | tcg_temp_free(tmp); |
1568 | c55497ec | aurel32 | } |
1569 | fdf9b3e8 | bellard | return;
|
1570 | fdf9b3e8 | bellard | case 0x4004: /* rotl Rn */ |
1571 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1572 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
1573 | 7efbe241 | aurel32 | gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0); |
1574 | fdf9b3e8 | bellard | return;
|
1575 | fdf9b3e8 | bellard | case 0x4005: /* rotr Rn */ |
1576 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1577 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
1578 | 7efbe241 | aurel32 | gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0); |
1579 | fdf9b3e8 | bellard | return;
|
1580 | fdf9b3e8 | bellard | case 0x4000: /* shll Rn */ |
1581 | fdf9b3e8 | bellard | case 0x4020: /* shal Rn */ |
1582 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1583 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
1584 | fdf9b3e8 | bellard | return;
|
1585 | fdf9b3e8 | bellard | case 0x4021: /* shar Rn */ |
1586 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1587 | 7efbe241 | aurel32 | tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);
|
1588 | fdf9b3e8 | bellard | return;
|
1589 | fdf9b3e8 | bellard | case 0x4001: /* shlr Rn */ |
1590 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1591 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
1592 | fdf9b3e8 | bellard | return;
|
1593 | fdf9b3e8 | bellard | case 0x4008: /* shll2 Rn */ |
1594 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2);
|
1595 | fdf9b3e8 | bellard | return;
|
1596 | fdf9b3e8 | bellard | case 0x4018: /* shll8 Rn */ |
1597 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8);
|
1598 | fdf9b3e8 | bellard | return;
|
1599 | fdf9b3e8 | bellard | case 0x4028: /* shll16 Rn */ |
1600 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16);
|
1601 | fdf9b3e8 | bellard | return;
|
1602 | fdf9b3e8 | bellard | case 0x4009: /* shlr2 Rn */ |
1603 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2);
|
1604 | fdf9b3e8 | bellard | return;
|
1605 | fdf9b3e8 | bellard | case 0x4019: /* shlr8 Rn */ |
1606 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8);
|
1607 | fdf9b3e8 | bellard | return;
|
1608 | fdf9b3e8 | bellard | case 0x4029: /* shlr16 Rn */ |
1609 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
|
1610 | fdf9b3e8 | bellard | return;
|
1611 | fdf9b3e8 | bellard | case 0x401b: /* tas.b @Rn */ |
1612 | c55497ec | aurel32 | { |
1613 | c55497ec | aurel32 | TCGv addr, val; |
1614 | c55497ec | aurel32 | addr = tcg_temp_local_new(TCG_TYPE_I32); |
1615 | c55497ec | aurel32 | tcg_gen_mov_i32(addr, REG(B11_8)); |
1616 | c55497ec | aurel32 | val = tcg_temp_local_new(TCG_TYPE_I32); |
1617 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1618 | c55497ec | aurel32 | gen_cmp_imm(TCG_COND_EQ, val, 0);
|
1619 | c55497ec | aurel32 | tcg_gen_ori_i32(val, val, 0x80);
|
1620 | c55497ec | aurel32 | tcg_gen_qemu_st8(val, addr, ctx->memidx); |
1621 | c55497ec | aurel32 | tcg_temp_free(val); |
1622 | c55497ec | aurel32 | tcg_temp_free(addr); |
1623 | c55497ec | aurel32 | } |
1624 | fdf9b3e8 | bellard | return;
|
1625 | e67888a7 | ths | case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ |
1626 | cc4ba6a9 | aurel32 | { |
1627 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul); |
1628 | cc4ba6a9 | aurel32 | } |
1629 | eda9b09b | bellard | return;
|
1630 | e67888a7 | ths | case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ |
1631 | cc4ba6a9 | aurel32 | { |
1632 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]); |
1633 | cc4ba6a9 | aurel32 | } |
1634 | eda9b09b | bellard | return;
|
1635 | e67888a7 | ths | case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ |
1636 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
1637 | a7812ae4 | pbrook | TCGv_i64 fp; |
1638 | ea6cf6be | ths | if (ctx->opcode & 0x0100) |
1639 | ea6cf6be | ths | break; /* illegal instruction */ |
1640 | a7812ae4 | pbrook | fp = tcg_temp_new_i64(); |
1641 | a7812ae4 | pbrook | gen_helper_float_DT(fp, cpu_fpul); |
1642 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, DREG(B11_8)); |
1643 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1644 | ea6cf6be | ths | } |
1645 | ea6cf6be | ths | else {
|
1646 | 66ba317c | aurel32 | gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul); |
1647 | ea6cf6be | ths | } |
1648 | ea6cf6be | ths | return;
|
1649 | e67888a7 | ths | case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
1650 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
1651 | a7812ae4 | pbrook | TCGv_i64 fp; |
1652 | ea6cf6be | ths | if (ctx->opcode & 0x0100) |
1653 | ea6cf6be | ths | break; /* illegal instruction */ |
1654 | a7812ae4 | pbrook | fp = tcg_temp_new_i64(); |
1655 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, DREG(B11_8)); |
1656 | a7812ae4 | pbrook | gen_helper_ftrc_DT(cpu_fpul, fp); |
1657 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1658 | ea6cf6be | ths | } |
1659 | ea6cf6be | ths | else {
|
1660 | 66ba317c | aurel32 | gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]); |
1661 | ea6cf6be | ths | } |
1662 | ea6cf6be | ths | return;
|
1663 | 24988dc2 | aurel32 | case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ |
1664 | 7fdf924f | aurel32 | { |
1665 | 66ba317c | aurel32 | gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
1666 | 7fdf924f | aurel32 | } |
1667 | 24988dc2 | aurel32 | return;
|
1668 | 24988dc2 | aurel32 | case 0xf05d: /* fabs FRn/DRn */ |
1669 | 24988dc2 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1670 | 24988dc2 | aurel32 | if (ctx->opcode & 0x0100) |
1671 | 24988dc2 | aurel32 | break; /* illegal instruction */ |
1672 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1673 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, DREG(B11_8)); |
1674 | a7812ae4 | pbrook | gen_helper_fabs_DT(fp, fp); |
1675 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, DREG(B11_8)); |
1676 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1677 | 24988dc2 | aurel32 | } else {
|
1678 | 66ba317c | aurel32 | gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
1679 | 24988dc2 | aurel32 | } |
1680 | 24988dc2 | aurel32 | return;
|
1681 | 24988dc2 | aurel32 | case 0xf06d: /* fsqrt FRn */ |
1682 | 24988dc2 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1683 | 24988dc2 | aurel32 | if (ctx->opcode & 0x0100) |
1684 | 24988dc2 | aurel32 | break; /* illegal instruction */ |
1685 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1686 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, DREG(B11_8)); |
1687 | a7812ae4 | pbrook | gen_helper_fsqrt_DT(fp, fp); |
1688 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, DREG(B11_8)); |
1689 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1690 | 24988dc2 | aurel32 | } else {
|
1691 | 66ba317c | aurel32 | gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
1692 | 24988dc2 | aurel32 | } |
1693 | 24988dc2 | aurel32 | return;
|
1694 | 24988dc2 | aurel32 | case 0xf07d: /* fsrra FRn */ |
1695 | 24988dc2 | aurel32 | break;
|
1696 | e67888a7 | ths | case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
1697 | ea6cf6be | ths | if (!(ctx->fpscr & FPSCR_PR)) {
|
1698 | 66ba317c | aurel32 | tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
|
1699 | ea6cf6be | ths | } |
1700 | 12d96138 | aurel32 | return;
|
1701 | e67888a7 | ths | case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
1702 | ea6cf6be | ths | if (!(ctx->fpscr & FPSCR_PR)) {
|
1703 | 66ba317c | aurel32 | tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
|
1704 | ea6cf6be | ths | } |
1705 | 12d96138 | aurel32 | return;
|
1706 | 24988dc2 | aurel32 | case 0xf0ad: /* fcnvsd FPUL,DRn */ |
1707 | cc4ba6a9 | aurel32 | { |
1708 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1709 | a7812ae4 | pbrook | gen_helper_fcnvsd_FT_DT(fp, cpu_fpul); |
1710 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, DREG(B11_8)); |
1711 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1712 | cc4ba6a9 | aurel32 | } |
1713 | 24988dc2 | aurel32 | return;
|
1714 | 24988dc2 | aurel32 | case 0xf0bd: /* fcnvds DRn,FPUL */ |
1715 | cc4ba6a9 | aurel32 | { |
1716 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1717 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, DREG(B11_8)); |
1718 | a7812ae4 | pbrook | gen_helper_fcnvds_DT_FT(cpu_fpul, fp); |
1719 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1720 | cc4ba6a9 | aurel32 | } |
1721 | 24988dc2 | aurel32 | return;
|
1722 | fdf9b3e8 | bellard | } |
1723 | fdf9b3e8 | bellard | |
1724 | fdf9b3e8 | bellard | fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
|
1725 | fdf9b3e8 | bellard | ctx->opcode, ctx->pc); |
1726 | a7812ae4 | pbrook | gen_helper_raise_illegal_instruction(); |
1727 | 823029f9 | ths | ctx->bstate = BS_EXCP; |
1728 | 823029f9 | ths | } |
1729 | 823029f9 | ths | |
1730 | b1d8e52e | blueswir1 | static void decode_opc(DisasContext * ctx) |
1731 | 823029f9 | ths | { |
1732 | 823029f9 | ths | uint32_t old_flags = ctx->flags; |
1733 | 823029f9 | ths | |
1734 | 823029f9 | ths | _decode_opc(ctx); |
1735 | 823029f9 | ths | |
1736 | 823029f9 | ths | if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
|
1737 | 823029f9 | ths | if (ctx->flags & DELAY_SLOT_CLEARME) {
|
1738 | 1000822b | aurel32 | gen_store_flags(0);
|
1739 | 274a9e70 | aurel32 | } else {
|
1740 | 274a9e70 | aurel32 | /* go out of the delay slot */
|
1741 | 274a9e70 | aurel32 | uint32_t new_flags = ctx->flags; |
1742 | 274a9e70 | aurel32 | new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
1743 | 1000822b | aurel32 | gen_store_flags(new_flags); |
1744 | 823029f9 | ths | } |
1745 | 823029f9 | ths | ctx->flags = 0;
|
1746 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1747 | 823029f9 | ths | if (old_flags & DELAY_SLOT_CONDITIONAL) {
|
1748 | 823029f9 | ths | gen_delayed_conditional_jump(ctx); |
1749 | 823029f9 | ths | } else if (old_flags & DELAY_SLOT) { |
1750 | 823029f9 | ths | gen_jump(ctx); |
1751 | 823029f9 | ths | } |
1752 | 823029f9 | ths | |
1753 | 823029f9 | ths | } |
1754 | 274a9e70 | aurel32 | |
1755 | 274a9e70 | aurel32 | /* go into a delay slot */
|
1756 | 274a9e70 | aurel32 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
|
1757 | 1000822b | aurel32 | gen_store_flags(ctx->flags); |
1758 | fdf9b3e8 | bellard | } |
1759 | fdf9b3e8 | bellard | |
1760 | 2cfc5f17 | ths | static inline void |
1761 | 820e00f2 | ths | gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
1762 | 820e00f2 | ths | int search_pc)
|
1763 | fdf9b3e8 | bellard | { |
1764 | fdf9b3e8 | bellard | DisasContext ctx; |
1765 | fdf9b3e8 | bellard | target_ulong pc_start; |
1766 | fdf9b3e8 | bellard | static uint16_t *gen_opc_end;
|
1767 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
1768 | 355fb23d | pbrook | int i, ii;
|
1769 | 2e70f6ef | pbrook | int num_insns;
|
1770 | 2e70f6ef | pbrook | int max_insns;
|
1771 | fdf9b3e8 | bellard | |
1772 | fdf9b3e8 | bellard | pc_start = tb->pc; |
1773 | fdf9b3e8 | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
1774 | fdf9b3e8 | bellard | ctx.pc = pc_start; |
1775 | 823029f9 | ths | ctx.flags = (uint32_t)tb->flags; |
1776 | 823029f9 | ths | ctx.bstate = BS_NONE; |
1777 | fdf9b3e8 | bellard | ctx.sr = env->sr; |
1778 | eda9b09b | bellard | ctx.fpscr = env->fpscr; |
1779 | fdf9b3e8 | bellard | ctx.memidx = (env->sr & SR_MD) ? 1 : 0; |
1780 | 9854bc46 | pbrook | /* We don't know if the delayed pc came from a dynamic or static branch,
|
1781 | 9854bc46 | pbrook | so assume it is a dynamic branch. */
|
1782 | 823029f9 | ths | ctx.delayed_pc = -1; /* use delayed pc from env pointer */ |
1783 | fdf9b3e8 | bellard | ctx.tb = tb; |
1784 | fdf9b3e8 | bellard | ctx.singlestep_enabled = env->singlestep_enabled; |
1785 | fdf9b3e8 | bellard | |
1786 | fdf9b3e8 | bellard | #ifdef DEBUG_DISAS
|
1787 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_CPU) {
|
1788 | fdf9b3e8 | bellard | fprintf(logfile, |
1789 | fdf9b3e8 | bellard | "------------------------------------------------\n");
|
1790 | fdf9b3e8 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
1791 | fdf9b3e8 | bellard | } |
1792 | fdf9b3e8 | bellard | #endif
|
1793 | fdf9b3e8 | bellard | |
1794 | 355fb23d | pbrook | ii = -1;
|
1795 | 2e70f6ef | pbrook | num_insns = 0;
|
1796 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
1797 | 2e70f6ef | pbrook | if (max_insns == 0) |
1798 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
1799 | 2e70f6ef | pbrook | gen_icount_start(); |
1800 | 823029f9 | ths | while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
|
1801 | c0ce998e | aliguori | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
|
1802 | c0ce998e | aliguori | TAILQ_FOREACH(bp, &env->breakpoints, entry) { |
1803 | a1d1bb31 | aliguori | if (ctx.pc == bp->pc) {
|
1804 | fdf9b3e8 | bellard | /* We have hit a breakpoint - make sure PC is up-to-date */
|
1805 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
1806 | a7812ae4 | pbrook | gen_helper_debug(); |
1807 | 823029f9 | ths | ctx.bstate = BS_EXCP; |
1808 | fdf9b3e8 | bellard | break;
|
1809 | fdf9b3e8 | bellard | } |
1810 | fdf9b3e8 | bellard | } |
1811 | fdf9b3e8 | bellard | } |
1812 | 355fb23d | pbrook | if (search_pc) {
|
1813 | 355fb23d | pbrook | i = gen_opc_ptr - gen_opc_buf; |
1814 | 355fb23d | pbrook | if (ii < i) {
|
1815 | 355fb23d | pbrook | ii++; |
1816 | 355fb23d | pbrook | while (ii < i)
|
1817 | 355fb23d | pbrook | gen_opc_instr_start[ii++] = 0;
|
1818 | 355fb23d | pbrook | } |
1819 | 355fb23d | pbrook | gen_opc_pc[ii] = ctx.pc; |
1820 | 823029f9 | ths | gen_opc_hflags[ii] = ctx.flags; |
1821 | 355fb23d | pbrook | gen_opc_instr_start[ii] = 1;
|
1822 | 2e70f6ef | pbrook | gen_opc_icount[ii] = num_insns; |
1823 | 355fb23d | pbrook | } |
1824 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
1825 | 2e70f6ef | pbrook | gen_io_start(); |
1826 | fdf9b3e8 | bellard | #if 0
|
1827 | fdf9b3e8 | bellard | fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
|
1828 | fdf9b3e8 | bellard | fflush(stderr);
|
1829 | fdf9b3e8 | bellard | #endif
|
1830 | fdf9b3e8 | bellard | ctx.opcode = lduw_code(ctx.pc); |
1831 | fdf9b3e8 | bellard | decode_opc(&ctx); |
1832 | 2e70f6ef | pbrook | num_insns++; |
1833 | fdf9b3e8 | bellard | ctx.pc += 2;
|
1834 | fdf9b3e8 | bellard | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) |
1835 | fdf9b3e8 | bellard | break;
|
1836 | fdf9b3e8 | bellard | if (env->singlestep_enabled)
|
1837 | fdf9b3e8 | bellard | break;
|
1838 | 2e70f6ef | pbrook | if (num_insns >= max_insns)
|
1839 | 2e70f6ef | pbrook | break;
|
1840 | fdf9b3e8 | bellard | #ifdef SH4_SINGLE_STEP
|
1841 | fdf9b3e8 | bellard | break;
|
1842 | fdf9b3e8 | bellard | #endif
|
1843 | fdf9b3e8 | bellard | } |
1844 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
1845 | 2e70f6ef | pbrook | gen_io_end(); |
1846 | fdf9b3e8 | bellard | if (env->singlestep_enabled) {
|
1847 | bdbf22e6 | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
1848 | a7812ae4 | pbrook | gen_helper_debug(); |
1849 | 823029f9 | ths | } else {
|
1850 | 823029f9 | ths | switch (ctx.bstate) {
|
1851 | 823029f9 | ths | case BS_STOP:
|
1852 | 823029f9 | ths | /* gen_op_interrupt_restart(); */
|
1853 | 823029f9 | ths | /* fall through */
|
1854 | 823029f9 | ths | case BS_NONE:
|
1855 | 823029f9 | ths | if (ctx.flags) {
|
1856 | 1000822b | aurel32 | gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME); |
1857 | 823029f9 | ths | } |
1858 | 823029f9 | ths | gen_goto_tb(&ctx, 0, ctx.pc);
|
1859 | 823029f9 | ths | break;
|
1860 | 823029f9 | ths | case BS_EXCP:
|
1861 | 823029f9 | ths | /* gen_op_interrupt_restart(); */
|
1862 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
1863 | 823029f9 | ths | break;
|
1864 | 823029f9 | ths | case BS_BRANCH:
|
1865 | 823029f9 | ths | default:
|
1866 | 823029f9 | ths | break;
|
1867 | 823029f9 | ths | } |
1868 | fdf9b3e8 | bellard | } |
1869 | 823029f9 | ths | |
1870 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
1871 | fdf9b3e8 | bellard | *gen_opc_ptr = INDEX_op_end; |
1872 | 355fb23d | pbrook | if (search_pc) {
|
1873 | 355fb23d | pbrook | i = gen_opc_ptr - gen_opc_buf; |
1874 | 355fb23d | pbrook | ii++; |
1875 | 355fb23d | pbrook | while (ii <= i)
|
1876 | 355fb23d | pbrook | gen_opc_instr_start[ii++] = 0;
|
1877 | 355fb23d | pbrook | } else {
|
1878 | 355fb23d | pbrook | tb->size = ctx.pc - pc_start; |
1879 | 2e70f6ef | pbrook | tb->icount = num_insns; |
1880 | 355fb23d | pbrook | } |
1881 | fdf9b3e8 | bellard | |
1882 | fdf9b3e8 | bellard | #ifdef DEBUG_DISAS
|
1883 | fdf9b3e8 | bellard | #ifdef SH4_DEBUG_DISAS
|
1884 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM)
|
1885 | fdf9b3e8 | bellard | fprintf(logfile, "\n");
|
1886 | fdf9b3e8 | bellard | #endif
|
1887 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
1888 | fdf9b3e8 | bellard | fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */ |
1889 | fdf9b3e8 | bellard | target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
|
1890 | fdf9b3e8 | bellard | fprintf(logfile, "\n");
|
1891 | fdf9b3e8 | bellard | } |
1892 | fdf9b3e8 | bellard | #endif
|
1893 | fdf9b3e8 | bellard | } |
1894 | fdf9b3e8 | bellard | |
1895 | 2cfc5f17 | ths | void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) |
1896 | fdf9b3e8 | bellard | { |
1897 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
1898 | fdf9b3e8 | bellard | } |
1899 | fdf9b3e8 | bellard | |
1900 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) |
1901 | fdf9b3e8 | bellard | { |
1902 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
1903 | fdf9b3e8 | bellard | } |
1904 | d2856f1a | aurel32 | |
1905 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
1906 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
1907 | d2856f1a | aurel32 | { |
1908 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
1909 | d2856f1a | aurel32 | env->flags = gen_opc_hflags[pc_pos]; |
1910 | d2856f1a | aurel32 | } |