Revision b79e1752
| b/hw/ide.c | ||
|---|---|---|
| 31 | 31 |
#include "qemu-timer.h" |
| 32 | 32 |
#include "sysemu.h" |
| 33 | 33 |
#include "ppc_mac.h" |
| 34 |
#include "sh.h" |
|
| 34 | 35 |
|
| 35 | 36 |
/* debug IDE devices */ |
| 36 | 37 |
//#define DEBUG_IDE |
| b/hw/pci.h | ||
|---|---|---|
| 139 | 139 |
PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base, |
| 140 | 140 |
qemu_irq *pic); |
| 141 | 141 |
|
| 142 |
/* sh_pci.c */ |
|
| 143 |
PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
|
| 144 |
qemu_irq *pic, int devfn_min, int nirq); |
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| 145 |
|
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| 142 | 146 |
#endif |
| b/hw/r2d.c | ||
|---|---|---|
| 240 | 240 |
/* initialization which should be done by firmware */ |
| 241 | 241 |
uint32_t bcr1 = 1 << 3; /* cs3 SDRAM */ |
| 242 | 242 |
uint16_t bcr2 = 3 << (3 * 2); /* cs3 32-bit */ |
| 243 |
cpu_physical_memory_write(SH7750_BCR1_A7, &bcr1, 4); |
|
| 244 |
cpu_physical_memory_write(SH7750_BCR2_A7, &bcr2, 2); |
|
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cpu_physical_memory_write(SH7750_BCR1_A7, (uint8_t *)&bcr1, 4);
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|
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cpu_physical_memory_write(SH7750_BCR2_A7, (uint8_t *)&bcr2, 2);
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|
| 245 | 245 |
|
| 246 | 246 |
kernel_size = load_image(kernel_filename, phys_ram_base); |
| 247 | 247 |
|
| b/hw/sh_intc.c | ||
|---|---|---|
| 73 | 73 |
} |
| 74 | 74 |
} |
| 75 | 75 |
|
| 76 |
void sh_intc_set_irq (void *opaque, int n, int level) |
|
| 76 |
static void sh_intc_set_irq (void *opaque, int n, int level)
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|
| 77 | 77 |
{
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| 78 | 78 |
struct intc_desc *desc = opaque; |
| 79 | 79 |
struct intc_source *source = &(desc->sources[n]); |
| b/hw/sm501.c | ||
|---|---|---|
| 27 | 27 |
#include "hw.h" |
| 28 | 28 |
#include "pc.h" |
| 29 | 29 |
#include "console.h" |
| 30 |
#include "devices.h" |
|
| 30 | 31 |
|
| 31 | 32 |
/* |
| 32 | 33 |
* Status: 2008/11/02 |
| b/target-sh4/translate.c | ||
|---|---|---|
| 71 | 71 |
static TCGv cpu_gregs[24]; |
| 72 | 72 |
static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr; |
| 73 | 73 |
static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; |
| 74 |
static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags;
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|
| 74 |
static TCGv cpu_pr, cpu_fpscr, cpu_fpul; |
|
| 75 | 75 |
static TCGv cpu_fregs[32]; |
| 76 | 76 |
|
| 77 | 77 |
/* internal register indexes */ |
| ... | ... | |
| 181 | 181 |
} |
| 182 | 182 |
} |
| 183 | 183 |
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void cpu_sh4_reset(CPUSH4State * env) |
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static void cpu_sh4_reset(CPUSH4State * env)
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| 185 | 185 |
{
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| 186 | 186 |
#if defined(CONFIG_USER_ONLY) |
| 187 | 187 |
env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */ |
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