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/*
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* i386 emulator main execution loop
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "config.h" |
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#include "exec.h" |
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#include "disas.h" |
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#if !defined(CONFIG_SOFTMMU)
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#undef EAX
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#undef ECX
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#undef EDX
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#undef EBX
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#undef ESP
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#undef EBP
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#undef ESI
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#undef EDI
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#undef EIP
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#include <signal.h> |
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#include <sys/ucontext.h> |
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#endif
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int tb_invalidated_flag;
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//#define DEBUG_EXEC
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//#define DEBUG_SIGNAL
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#if defined(TARGET_ARM) || defined(TARGET_SPARC)
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/* XXX: unify with i386 target */
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void cpu_loop_exit(void) |
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{ |
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longjmp(env->jmp_env, 1);
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} |
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#endif
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/* exit the current TB from a signal handler. The host registers are
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restored in a state compatible with the CPU emulator
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*/
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void cpu_resume_from_signal(CPUState *env1, void *puc) |
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{ |
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#if !defined(CONFIG_SOFTMMU)
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struct ucontext *uc = puc;
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#endif
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env = env1; |
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/* XXX: restore cpu registers saved in host registers */
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#if !defined(CONFIG_SOFTMMU)
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if (puc) {
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/* XXX: use siglongjmp ? */
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sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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} |
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#endif
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longjmp(env->jmp_env, 1);
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} |
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/* main execution loop */
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int cpu_exec(CPUState *env1)
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{ |
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int saved_T0, saved_T1, saved_T2;
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CPUState *saved_env; |
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#ifdef reg_EAX
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int saved_EAX;
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#endif
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#ifdef reg_ECX
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int saved_ECX;
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#endif
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#ifdef reg_EDX
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int saved_EDX;
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#endif
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#ifdef reg_EBX
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int saved_EBX;
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#endif
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#ifdef reg_ESP
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int saved_ESP;
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#endif
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#ifdef reg_EBP
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int saved_EBP;
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#endif
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#ifdef reg_ESI
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int saved_ESI;
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#endif
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#ifdef reg_EDI
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int saved_EDI;
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#endif
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#ifdef __sparc__
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int saved_i7, tmp_T0;
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#endif
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int code_gen_size, ret, interrupt_request;
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void (*gen_func)(void); |
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TranslationBlock *tb, **ptb; |
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target_ulong cs_base, pc; |
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uint8_t *tc_ptr; |
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unsigned int flags; |
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/* first we save global registers */
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saved_env = env; |
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env = env1; |
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saved_T0 = T0; |
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saved_T1 = T1; |
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saved_T2 = T2; |
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#ifdef __sparc__
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/* we also save i7 because longjmp may not restore it */
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asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); |
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#endif
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#if defined(TARGET_I386)
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#ifdef reg_EAX
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saved_EAX = EAX; |
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#endif
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#ifdef reg_ECX
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saved_ECX = ECX; |
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#endif
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#ifdef reg_EDX
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saved_EDX = EDX; |
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#endif
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#ifdef reg_EBX
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saved_EBX = EBX; |
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#endif
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#ifdef reg_ESP
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saved_ESP = ESP; |
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#endif
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#ifdef reg_EBP
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saved_EBP = EBP; |
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#endif
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#ifdef reg_ESI
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saved_ESI = ESI; |
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#endif
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#ifdef reg_EDI
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saved_EDI = EDI; |
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#endif
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env_to_regs(); |
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
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DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
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CC_OP = CC_OP_EFLAGS; |
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
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#elif defined(TARGET_ARM)
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{ |
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unsigned int psr; |
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psr = env->cpsr; |
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env->CF = (psr >> 29) & 1; |
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env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
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env->VF = (psr << 3) & 0x80000000; |
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env->QF = (psr >> 27) & 1; |
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env->cpsr = psr & ~CACHED_CPSR_BITS; |
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} |
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#elif defined(TARGET_SPARC)
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#elif defined(TARGET_PPC)
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#else
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#error unsupported target CPU
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#endif
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env->exception_index = -1;
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/* prepare setjmp context for exception handling */
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for(;;) {
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if (setjmp(env->jmp_env) == 0) { |
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env->current_tb = NULL;
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/* if an exception is pending, we execute it here */
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if (env->exception_index >= 0) { |
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if (env->exception_index >= EXCP_INTERRUPT) {
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/* exit request from the cpu execution loop */
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ret = env->exception_index; |
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break;
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} else if (env->user_mode_only) { |
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/* if user mode only, we simulate a fake exception
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which will be hanlded outside the cpu execution
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loop */
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#if defined(TARGET_I386)
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do_interrupt_user(env->exception_index, |
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env->exception_is_int, |
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env->error_code, |
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env->exception_next_eip); |
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#endif
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ret = env->exception_index; |
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break;
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} else {
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#if defined(TARGET_I386)
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/* simulate a real cpu exception. On i386, it can
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trigger new exceptions, but we do not handle
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double or triple faults yet. */
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do_interrupt(env->exception_index, |
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env->exception_is_int, |
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env->error_code, |
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env->exception_next_eip, 0);
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#elif defined(TARGET_PPC)
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do_interrupt(env); |
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#elif defined(TARGET_SPARC)
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do_interrupt(env->exception_index); |
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#endif
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} |
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env->exception_index = -1;
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} |
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#ifdef USE_KQEMU
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if (kqemu_is_ok(env) && env->interrupt_request == 0) { |
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int ret;
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
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ret = kqemu_cpu_exec(env); |
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
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DF = 1 - (2 * ((env->eflags >> 10) & 1)); |
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CC_OP = CC_OP_EFLAGS; |
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
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if (ret == 1) { |
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/* exception */
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longjmp(env->jmp_env, 1);
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} else if (ret == 2) { |
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/* softmmu execution needed */
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} else {
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if (env->interrupt_request != 0) { |
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/* hardware interrupt will be executed just after */
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} else {
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/* otherwise, we restart */
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longjmp(env->jmp_env, 1);
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} |
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} |
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} |
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#endif
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T0 = 0; /* force lookup of first TB */ |
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for(;;) {
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#ifdef __sparc__
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/* g1 can be modified by some libc? functions */
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tmp_T0 = T0; |
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#endif
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interrupt_request = env->interrupt_request; |
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if (__builtin_expect(interrupt_request, 0)) { |
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#if defined(TARGET_I386)
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/* if hardware interrupt pending, we execute it */
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if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->eflags & IF_MASK) && |
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!(env->hflags & HF_INHIBIT_IRQ_MASK)) { |
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int intno;
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env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
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intno = cpu_get_pic_interrupt(env); |
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
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} |
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do_interrupt(intno, 0, 0, 0, 1); |
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/* ensure that no TB jump will be modified as
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the program flow was changed */
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#ifdef __sparc__
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tmp_T0 = 0;
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#else
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T0 = 0;
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#endif
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} |
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#elif defined(TARGET_PPC)
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#if 0
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if ((interrupt_request & CPU_INTERRUPT_RESET)) {
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cpu_ppc_reset(env);
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}
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#endif
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if (msr_ee != 0) { |
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if ((interrupt_request & CPU_INTERRUPT_HARD)) {
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/* Raise it */
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env->exception_index = EXCP_EXTERNAL; |
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env->error_code = 0;
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do_interrupt(env); |
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env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
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} else if ((interrupt_request & CPU_INTERRUPT_TIMER)) { |
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/* Raise it */
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env->exception_index = EXCP_DECR; |
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env->error_code = 0;
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do_interrupt(env); |
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env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
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} |
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} |
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#elif defined(TARGET_SPARC)
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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do_interrupt(env->interrupt_index); |
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env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
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} else if (interrupt_request & CPU_INTERRUPT_TIMER) { |
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//do_interrupt(0, 0, 0, 0, 0);
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env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
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} |
295 |
#endif
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if (interrupt_request & CPU_INTERRUPT_EXITTB) {
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env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; |
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/* ensure that no TB jump will be modified as
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the program flow was changed */
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#ifdef __sparc__
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tmp_T0 = 0;
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#else
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T0 = 0;
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#endif
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} |
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if (interrupt_request & CPU_INTERRUPT_EXIT) {
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env->interrupt_request &= ~CPU_INTERRUPT_EXIT; |
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env->exception_index = EXCP_INTERRUPT; |
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cpu_loop_exit(); |
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} |
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} |
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#ifdef DEBUG_EXEC
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if ((loglevel & CPU_LOG_EXEC)) {
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#if defined(TARGET_I386)
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/* restore flags in standard format */
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env->regs[R_EAX] = EAX; |
317 |
env->regs[R_EBX] = EBX; |
318 |
env->regs[R_ECX] = ECX; |
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env->regs[R_EDX] = EDX; |
320 |
env->regs[R_ESI] = ESI; |
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env->regs[R_EDI] = EDI; |
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env->regs[R_EBP] = EBP; |
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env->regs[R_ESP] = ESP; |
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env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
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cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); |
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
327 |
#elif defined(TARGET_ARM)
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env->cpsr = compute_cpsr(); |
329 |
cpu_dump_state(env, logfile, fprintf, 0);
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env->cpsr &= ~CACHED_CPSR_BITS; |
331 |
#elif defined(TARGET_SPARC)
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cpu_dump_state (env, logfile, fprintf, 0);
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#elif defined(TARGET_PPC)
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cpu_dump_state(env, logfile, fprintf, 0);
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#else
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#error unsupported target CPU
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#endif
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} |
339 |
#endif
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340 |
/* we record a subset of the CPU state. It will
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always be the same before a given translated block
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is executed. */
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#if defined(TARGET_I386)
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flags = env->hflags; |
345 |
flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
346 |
cs_base = env->segs[R_CS].base; |
347 |
pc = cs_base + env->eip; |
348 |
#elif defined(TARGET_ARM)
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flags = env->thumb | (env->vfp.vec_len << 1)
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| (env->vfp.vec_stride << 4);
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cs_base = 0;
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pc = env->regs[15];
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353 |
#elif defined(TARGET_SPARC)
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flags = 0;
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355 |
cs_base = env->npc; |
356 |
pc = env->pc; |
357 |
#elif defined(TARGET_PPC)
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358 |
flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | (msr_se << MSR_SE); |
359 |
cs_base = 0;
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360 |
pc = env->nip; |
361 |
#else
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362 |
#error unsupported CPU
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363 |
#endif
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364 |
tb = tb_find(&ptb, pc, cs_base, |
365 |
flags); |
366 |
if (!tb) {
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367 |
TranslationBlock **ptb1; |
368 |
unsigned int h; |
369 |
target_ulong phys_pc, phys_page1, phys_page2, virt_page2; |
370 |
|
371 |
|
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spin_lock(&tb_lock); |
373 |
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374 |
tb_invalidated_flag = 0;
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375 |
|
376 |
regs_to_env(); /* XXX: do it just before cpu_gen_code() */
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377 |
|
378 |
/* find translated block using physical mappings */
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379 |
phys_pc = get_phys_addr_code(env, pc); |
380 |
phys_page1 = phys_pc & TARGET_PAGE_MASK; |
381 |
phys_page2 = -1;
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382 |
h = tb_phys_hash_func(phys_pc); |
383 |
ptb1 = &tb_phys_hash[h]; |
384 |
for(;;) {
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385 |
tb = *ptb1; |
386 |
if (!tb)
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387 |
goto not_found;
|
388 |
if (tb->pc == pc &&
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389 |
tb->page_addr[0] == phys_page1 &&
|
390 |
tb->cs_base == cs_base && |
391 |
tb->flags == flags) { |
392 |
/* check next page if needed */
|
393 |
if (tb->page_addr[1] != -1) { |
394 |
virt_page2 = (pc & TARGET_PAGE_MASK) + |
395 |
TARGET_PAGE_SIZE; |
396 |
phys_page2 = get_phys_addr_code(env, virt_page2); |
397 |
if (tb->page_addr[1] == phys_page2) |
398 |
goto found;
|
399 |
} else {
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400 |
goto found;
|
401 |
} |
402 |
} |
403 |
ptb1 = &tb->phys_hash_next; |
404 |
} |
405 |
not_found:
|
406 |
/* if no translated code available, then translate it now */
|
407 |
tb = tb_alloc(pc); |
408 |
if (!tb) {
|
409 |
/* flush must be done */
|
410 |
tb_flush(env); |
411 |
/* cannot fail at this point */
|
412 |
tb = tb_alloc(pc); |
413 |
/* don't forget to invalidate previous TB info */
|
414 |
ptb = &tb_hash[tb_hash_func(pc)]; |
415 |
T0 = 0;
|
416 |
} |
417 |
tc_ptr = code_gen_ptr; |
418 |
tb->tc_ptr = tc_ptr; |
419 |
tb->cs_base = cs_base; |
420 |
tb->flags = flags; |
421 |
cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); |
422 |
code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); |
423 |
|
424 |
/* check next page if needed */
|
425 |
virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
|
426 |
phys_page2 = -1;
|
427 |
if ((pc & TARGET_PAGE_MASK) != virt_page2) {
|
428 |
phys_page2 = get_phys_addr_code(env, virt_page2); |
429 |
} |
430 |
tb_link_phys(tb, phys_pc, phys_page2); |
431 |
|
432 |
found:
|
433 |
if (tb_invalidated_flag) {
|
434 |
/* as some TB could have been invalidated because
|
435 |
of memory exceptions while generating the code, we
|
436 |
must recompute the hash index here */
|
437 |
ptb = &tb_hash[tb_hash_func(pc)]; |
438 |
while (*ptb != NULL) |
439 |
ptb = &(*ptb)->hash_next; |
440 |
T0 = 0;
|
441 |
} |
442 |
/* we add the TB in the virtual pc hash table */
|
443 |
*ptb = tb; |
444 |
tb->hash_next = NULL;
|
445 |
tb_link(tb); |
446 |
spin_unlock(&tb_lock); |
447 |
} |
448 |
#ifdef DEBUG_EXEC
|
449 |
if ((loglevel & CPU_LOG_EXEC)) {
|
450 |
fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", |
451 |
(long)tb->tc_ptr, tb->pc,
|
452 |
lookup_symbol(tb->pc)); |
453 |
} |
454 |
#endif
|
455 |
#ifdef __sparc__
|
456 |
T0 = tmp_T0; |
457 |
#endif
|
458 |
/* see if we can patch the calling TB. */
|
459 |
{ |
460 |
if (T0 != 0 |
461 |
#if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
462 |
&& (tb->cflags & CF_CODE_COPY) == |
463 |
(((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
|
464 |
#endif
|
465 |
) { |
466 |
spin_lock(&tb_lock); |
467 |
tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); |
468 |
#if defined(USE_CODE_COPY)
|
469 |
/* propagates the FP use info */
|
470 |
((TranslationBlock *)(T0 & ~3))->cflags |=
|
471 |
(tb->cflags & CF_FP_USED); |
472 |
#endif
|
473 |
spin_unlock(&tb_lock); |
474 |
} |
475 |
} |
476 |
tc_ptr = tb->tc_ptr; |
477 |
env->current_tb = tb; |
478 |
/* execute the generated code */
|
479 |
gen_func = (void *)tc_ptr;
|
480 |
#if defined(__sparc__)
|
481 |
__asm__ __volatile__("call %0\n\t"
|
482 |
"mov %%o7,%%i0"
|
483 |
: /* no outputs */
|
484 |
: "r" (gen_func)
|
485 |
: "i0", "i1", "i2", "i3", "i4", "i5"); |
486 |
#elif defined(__arm__)
|
487 |
asm volatile ("mov pc, %0\n\t" |
488 |
".global exec_loop\n\t"
|
489 |
"exec_loop:\n\t"
|
490 |
: /* no outputs */
|
491 |
: "r" (gen_func)
|
492 |
: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); |
493 |
#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
|
494 |
{ |
495 |
if (!(tb->cflags & CF_CODE_COPY)) {
|
496 |
if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
|
497 |
save_native_fp_state(env); |
498 |
} |
499 |
gen_func(); |
500 |
} else {
|
501 |
if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
|
502 |
restore_native_fp_state(env); |
503 |
} |
504 |
/* we work with native eflags */
|
505 |
CC_SRC = cc_table[CC_OP].compute_all(); |
506 |
CC_OP = CC_OP_EFLAGS; |
507 |
asm(".globl exec_loop\n" |
508 |
"\n"
|
509 |
"debug1:\n"
|
510 |
" pushl %%ebp\n"
|
511 |
" fs movl %10, %9\n"
|
512 |
" fs movl %11, %%eax\n"
|
513 |
" andl $0x400, %%eax\n"
|
514 |
" fs orl %8, %%eax\n"
|
515 |
" pushl %%eax\n"
|
516 |
" popf\n"
|
517 |
" fs movl %%esp, %12\n"
|
518 |
" fs movl %0, %%eax\n"
|
519 |
" fs movl %1, %%ecx\n"
|
520 |
" fs movl %2, %%edx\n"
|
521 |
" fs movl %3, %%ebx\n"
|
522 |
" fs movl %4, %%esp\n"
|
523 |
" fs movl %5, %%ebp\n"
|
524 |
" fs movl %6, %%esi\n"
|
525 |
" fs movl %7, %%edi\n"
|
526 |
" fs jmp *%9\n"
|
527 |
"exec_loop:\n"
|
528 |
" fs movl %%esp, %4\n"
|
529 |
" fs movl %12, %%esp\n"
|
530 |
" fs movl %%eax, %0\n"
|
531 |
" fs movl %%ecx, %1\n"
|
532 |
" fs movl %%edx, %2\n"
|
533 |
" fs movl %%ebx, %3\n"
|
534 |
" fs movl %%ebp, %5\n"
|
535 |
" fs movl %%esi, %6\n"
|
536 |
" fs movl %%edi, %7\n"
|
537 |
" pushf\n"
|
538 |
" popl %%eax\n"
|
539 |
" movl %%eax, %%ecx\n"
|
540 |
" andl $0x400, %%ecx\n"
|
541 |
" shrl $9, %%ecx\n"
|
542 |
" andl $0x8d5, %%eax\n"
|
543 |
" fs movl %%eax, %8\n"
|
544 |
" movl $1, %%eax\n"
|
545 |
" subl %%ecx, %%eax\n"
|
546 |
" fs movl %%eax, %11\n"
|
547 |
" fs movl %9, %%ebx\n" /* get T0 value */ |
548 |
" popl %%ebp\n"
|
549 |
: |
550 |
: "m" (*(uint8_t *)offsetof(CPUState, regs[0])), |
551 |
"m" (*(uint8_t *)offsetof(CPUState, regs[1])), |
552 |
"m" (*(uint8_t *)offsetof(CPUState, regs[2])), |
553 |
"m" (*(uint8_t *)offsetof(CPUState, regs[3])), |
554 |
"m" (*(uint8_t *)offsetof(CPUState, regs[4])), |
555 |
"m" (*(uint8_t *)offsetof(CPUState, regs[5])), |
556 |
"m" (*(uint8_t *)offsetof(CPUState, regs[6])), |
557 |
"m" (*(uint8_t *)offsetof(CPUState, regs[7])), |
558 |
"m" (*(uint8_t *)offsetof(CPUState, cc_src)),
|
559 |
"m" (*(uint8_t *)offsetof(CPUState, tmp0)),
|
560 |
"a" (gen_func),
|
561 |
"m" (*(uint8_t *)offsetof(CPUState, df)),
|
562 |
"m" (*(uint8_t *)offsetof(CPUState, saved_esp))
|
563 |
: "%ecx", "%edx" |
564 |
); |
565 |
} |
566 |
} |
567 |
#else
|
568 |
gen_func(); |
569 |
#endif
|
570 |
env->current_tb = NULL;
|
571 |
/* reset soft MMU for next block (it can currently
|
572 |
only be set by a memory fault) */
|
573 |
#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
|
574 |
if (env->hflags & HF_SOFTMMU_MASK) {
|
575 |
env->hflags &= ~HF_SOFTMMU_MASK; |
576 |
/* do not allow linking to another block */
|
577 |
T0 = 0;
|
578 |
} |
579 |
#endif
|
580 |
} |
581 |
} else {
|
582 |
env_to_regs(); |
583 |
} |
584 |
} /* for(;;) */
|
585 |
|
586 |
|
587 |
#if defined(TARGET_I386)
|
588 |
#if defined(USE_CODE_COPY)
|
589 |
if (env->native_fp_regs) {
|
590 |
save_native_fp_state(env); |
591 |
} |
592 |
#endif
|
593 |
/* restore flags in standard format */
|
594 |
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); |
595 |
|
596 |
/* restore global registers */
|
597 |
#ifdef reg_EAX
|
598 |
EAX = saved_EAX; |
599 |
#endif
|
600 |
#ifdef reg_ECX
|
601 |
ECX = saved_ECX; |
602 |
#endif
|
603 |
#ifdef reg_EDX
|
604 |
EDX = saved_EDX; |
605 |
#endif
|
606 |
#ifdef reg_EBX
|
607 |
EBX = saved_EBX; |
608 |
#endif
|
609 |
#ifdef reg_ESP
|
610 |
ESP = saved_ESP; |
611 |
#endif
|
612 |
#ifdef reg_EBP
|
613 |
EBP = saved_EBP; |
614 |
#endif
|
615 |
#ifdef reg_ESI
|
616 |
ESI = saved_ESI; |
617 |
#endif
|
618 |
#ifdef reg_EDI
|
619 |
EDI = saved_EDI; |
620 |
#endif
|
621 |
#elif defined(TARGET_ARM)
|
622 |
env->cpsr = compute_cpsr(); |
623 |
/* XXX: Save/restore host fpu exception state?. */
|
624 |
#elif defined(TARGET_SPARC)
|
625 |
#elif defined(TARGET_PPC)
|
626 |
#else
|
627 |
#error unsupported target CPU
|
628 |
#endif
|
629 |
#ifdef __sparc__
|
630 |
asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); |
631 |
#endif
|
632 |
T0 = saved_T0; |
633 |
T1 = saved_T1; |
634 |
T2 = saved_T2; |
635 |
env = saved_env; |
636 |
return ret;
|
637 |
} |
638 |
|
639 |
/* must only be called from the generated code as an exception can be
|
640 |
generated */
|
641 |
void tb_invalidate_page_range(target_ulong start, target_ulong end)
|
642 |
{ |
643 |
/* XXX: cannot enable it yet because it yields to MMU exception
|
644 |
where NIP != read address on PowerPC */
|
645 |
#if 0
|
646 |
target_ulong phys_addr;
|
647 |
phys_addr = get_phys_addr_code(env, start);
|
648 |
tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
|
649 |
#endif
|
650 |
} |
651 |
|
652 |
#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
653 |
|
654 |
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) |
655 |
{ |
656 |
CPUX86State *saved_env; |
657 |
|
658 |
saved_env = env; |
659 |
env = s; |
660 |
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
661 |
selector &= 0xffff;
|
662 |
cpu_x86_load_seg_cache(env, seg_reg, selector, |
663 |
(selector << 4), 0xffff, 0); |
664 |
} else {
|
665 |
load_seg(seg_reg, selector); |
666 |
} |
667 |
env = saved_env; |
668 |
} |
669 |
|
670 |
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) |
671 |
{ |
672 |
CPUX86State *saved_env; |
673 |
|
674 |
saved_env = env; |
675 |
env = s; |
676 |
|
677 |
helper_fsave((target_ulong)ptr, data32); |
678 |
|
679 |
env = saved_env; |
680 |
} |
681 |
|
682 |
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) |
683 |
{ |
684 |
CPUX86State *saved_env; |
685 |
|
686 |
saved_env = env; |
687 |
env = s; |
688 |
|
689 |
helper_frstor((target_ulong)ptr, data32); |
690 |
|
691 |
env = saved_env; |
692 |
} |
693 |
|
694 |
#endif /* TARGET_I386 */ |
695 |
|
696 |
#if !defined(CONFIG_SOFTMMU)
|
697 |
|
698 |
#if defined(TARGET_I386)
|
699 |
|
700 |
/* 'pc' is the host PC at which the exception was raised. 'address' is
|
701 |
the effective address of the memory exception. 'is_write' is 1 if a
|
702 |
write caused the exception and otherwise 0'. 'old_set' is the
|
703 |
signal set which should be restored */
|
704 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
705 |
int is_write, sigset_t *old_set,
|
706 |
void *puc)
|
707 |
{ |
708 |
TranslationBlock *tb; |
709 |
int ret;
|
710 |
|
711 |
if (cpu_single_env)
|
712 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
713 |
#if defined(DEBUG_SIGNAL)
|
714 |
qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
715 |
pc, address, is_write, *(unsigned long *)old_set); |
716 |
#endif
|
717 |
/* XXX: locking issue */
|
718 |
if (is_write && page_unprotect(address, pc, puc)) {
|
719 |
return 1; |
720 |
} |
721 |
|
722 |
/* see if it is an MMU fault */
|
723 |
ret = cpu_x86_handle_mmu_fault(env, address, is_write, |
724 |
((env->hflags & HF_CPL_MASK) == 3), 0); |
725 |
if (ret < 0) |
726 |
return 0; /* not an MMU fault */ |
727 |
if (ret == 0) |
728 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
729 |
/* now we have a real cpu fault */
|
730 |
tb = tb_find_pc(pc); |
731 |
if (tb) {
|
732 |
/* the PC is inside the translated code. It means that we have
|
733 |
a virtual CPU fault */
|
734 |
cpu_restore_state(tb, env, pc, puc); |
735 |
} |
736 |
if (ret == 1) { |
737 |
#if 0
|
738 |
printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
739 |
env->eip, env->cr[2], env->error_code);
|
740 |
#endif
|
741 |
/* we restore the process signal mask as the sigreturn should
|
742 |
do it (XXX: use sigsetjmp) */
|
743 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
744 |
raise_exception_err(EXCP0E_PAGE, env->error_code); |
745 |
} else {
|
746 |
/* activate soft MMU for this block */
|
747 |
env->hflags |= HF_SOFTMMU_MASK; |
748 |
cpu_resume_from_signal(env, puc); |
749 |
} |
750 |
/* never comes here */
|
751 |
return 1; |
752 |
} |
753 |
|
754 |
#elif defined(TARGET_ARM)
|
755 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
756 |
int is_write, sigset_t *old_set,
|
757 |
void *puc)
|
758 |
{ |
759 |
TranslationBlock *tb; |
760 |
int ret;
|
761 |
|
762 |
if (cpu_single_env)
|
763 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
764 |
#if defined(DEBUG_SIGNAL)
|
765 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
766 |
pc, address, is_write, *(unsigned long *)old_set); |
767 |
#endif
|
768 |
/* XXX: locking issue */
|
769 |
if (is_write && page_unprotect(address, pc, puc)) {
|
770 |
return 1; |
771 |
} |
772 |
/* see if it is an MMU fault */
|
773 |
ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); |
774 |
if (ret < 0) |
775 |
return 0; /* not an MMU fault */ |
776 |
if (ret == 0) |
777 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
778 |
/* now we have a real cpu fault */
|
779 |
tb = tb_find_pc(pc); |
780 |
if (tb) {
|
781 |
/* the PC is inside the translated code. It means that we have
|
782 |
a virtual CPU fault */
|
783 |
cpu_restore_state(tb, env, pc, puc); |
784 |
} |
785 |
/* we restore the process signal mask as the sigreturn should
|
786 |
do it (XXX: use sigsetjmp) */
|
787 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
788 |
cpu_loop_exit(); |
789 |
} |
790 |
#elif defined(TARGET_SPARC)
|
791 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
792 |
int is_write, sigset_t *old_set,
|
793 |
void *puc)
|
794 |
{ |
795 |
TranslationBlock *tb; |
796 |
int ret;
|
797 |
|
798 |
if (cpu_single_env)
|
799 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
800 |
#if defined(DEBUG_SIGNAL)
|
801 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
802 |
pc, address, is_write, *(unsigned long *)old_set); |
803 |
#endif
|
804 |
/* XXX: locking issue */
|
805 |
if (is_write && page_unprotect(address, pc, puc)) {
|
806 |
return 1; |
807 |
} |
808 |
/* see if it is an MMU fault */
|
809 |
ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); |
810 |
if (ret < 0) |
811 |
return 0; /* not an MMU fault */ |
812 |
if (ret == 0) |
813 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
814 |
/* now we have a real cpu fault */
|
815 |
tb = tb_find_pc(pc); |
816 |
if (tb) {
|
817 |
/* the PC is inside the translated code. It means that we have
|
818 |
a virtual CPU fault */
|
819 |
cpu_restore_state(tb, env, pc, puc); |
820 |
} |
821 |
/* we restore the process signal mask as the sigreturn should
|
822 |
do it (XXX: use sigsetjmp) */
|
823 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
824 |
cpu_loop_exit(); |
825 |
} |
826 |
#elif defined (TARGET_PPC)
|
827 |
static inline int handle_cpu_signal(unsigned long pc, unsigned long address, |
828 |
int is_write, sigset_t *old_set,
|
829 |
void *puc)
|
830 |
{ |
831 |
TranslationBlock *tb; |
832 |
int ret;
|
833 |
|
834 |
if (cpu_single_env)
|
835 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
836 |
#if defined(DEBUG_SIGNAL)
|
837 |
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
838 |
pc, address, is_write, *(unsigned long *)old_set); |
839 |
#endif
|
840 |
/* XXX: locking issue */
|
841 |
if (is_write && page_unprotect(address, pc, puc)) {
|
842 |
return 1; |
843 |
} |
844 |
|
845 |
/* see if it is an MMU fault */
|
846 |
ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
847 |
if (ret < 0) |
848 |
return 0; /* not an MMU fault */ |
849 |
if (ret == 0) |
850 |
return 1; /* the MMU fault was handled without causing real CPU fault */ |
851 |
|
852 |
/* now we have a real cpu fault */
|
853 |
tb = tb_find_pc(pc); |
854 |
if (tb) {
|
855 |
/* the PC is inside the translated code. It means that we have
|
856 |
a virtual CPU fault */
|
857 |
cpu_restore_state(tb, env, pc, puc); |
858 |
} |
859 |
if (ret == 1) { |
860 |
#if 0
|
861 |
printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
862 |
env->nip, env->error_code, tb);
|
863 |
#endif
|
864 |
/* we restore the process signal mask as the sigreturn should
|
865 |
do it (XXX: use sigsetjmp) */
|
866 |
sigprocmask(SIG_SETMASK, old_set, NULL);
|
867 |
do_raise_exception_err(env->exception_index, env->error_code); |
868 |
} else {
|
869 |
/* activate soft MMU for this block */
|
870 |
cpu_resume_from_signal(env, puc); |
871 |
} |
872 |
/* never comes here */
|
873 |
return 1; |
874 |
} |
875 |
#else
|
876 |
#error unsupported target CPU
|
877 |
#endif
|
878 |
|
879 |
#if defined(__i386__)
|
880 |
|
881 |
#if defined(USE_CODE_COPY)
|
882 |
static void cpu_send_trap(unsigned long pc, int trap, |
883 |
struct ucontext *uc)
|
884 |
{ |
885 |
TranslationBlock *tb; |
886 |
|
887 |
if (cpu_single_env)
|
888 |
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
889 |
/* now we have a real cpu fault */
|
890 |
tb = tb_find_pc(pc); |
891 |
if (tb) {
|
892 |
/* the PC is inside the translated code. It means that we have
|
893 |
a virtual CPU fault */
|
894 |
cpu_restore_state(tb, env, pc, uc); |
895 |
} |
896 |
sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
|
897 |
raise_exception_err(trap, env->error_code); |
898 |
} |
899 |
#endif
|
900 |
|
901 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
902 |
void *puc)
|
903 |
{ |
904 |
struct ucontext *uc = puc;
|
905 |
unsigned long pc; |
906 |
int trapno;
|
907 |
|
908 |
#ifndef REG_EIP
|
909 |
/* for glibc 2.1 */
|
910 |
#define REG_EIP EIP
|
911 |
#define REG_ERR ERR
|
912 |
#define REG_TRAPNO TRAPNO
|
913 |
#endif
|
914 |
pc = uc->uc_mcontext.gregs[REG_EIP]; |
915 |
trapno = uc->uc_mcontext.gregs[REG_TRAPNO]; |
916 |
#if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
917 |
if (trapno == 0x00 || trapno == 0x05) { |
918 |
/* send division by zero or bound exception */
|
919 |
cpu_send_trap(pc, trapno, uc); |
920 |
return 1; |
921 |
} else
|
922 |
#endif
|
923 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
924 |
trapno == 0xe ?
|
925 |
(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
926 |
&uc->uc_sigmask, puc); |
927 |
} |
928 |
|
929 |
#elif defined(__x86_64__)
|
930 |
|
931 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
932 |
void *puc)
|
933 |
{ |
934 |
struct ucontext *uc = puc;
|
935 |
unsigned long pc; |
936 |
|
937 |
pc = uc->uc_mcontext.gregs[REG_RIP]; |
938 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
939 |
uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
940 |
(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0, |
941 |
&uc->uc_sigmask, puc); |
942 |
} |
943 |
|
944 |
#elif defined(__powerpc__)
|
945 |
|
946 |
/***********************************************************************
|
947 |
* signal context platform-specific definitions
|
948 |
* From Wine
|
949 |
*/
|
950 |
#ifdef linux
|
951 |
/* All Registers access - only for local access */
|
952 |
# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
|
953 |
/* Gpr Registers access */
|
954 |
# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
|
955 |
# define IAR_sig(context) REG_sig(nip, context) /* Program counter */ |
956 |
# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */ |
957 |
# define CTR_sig(context) REG_sig(ctr, context) /* Count register */ |
958 |
# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */ |
959 |
# define LR_sig(context) REG_sig(link, context) /* Link register */ |
960 |
# define CR_sig(context) REG_sig(ccr, context) /* Condition register */ |
961 |
/* Float Registers access */
|
962 |
# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num]) |
963 |
# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4))) |
964 |
/* Exception Registers access */
|
965 |
# define DAR_sig(context) REG_sig(dar, context)
|
966 |
# define DSISR_sig(context) REG_sig(dsisr, context)
|
967 |
# define TRAP_sig(context) REG_sig(trap, context)
|
968 |
#endif /* linux */ |
969 |
|
970 |
#ifdef __APPLE__
|
971 |
# include <sys/ucontext.h> |
972 |
typedef struct ucontext SIGCONTEXT; |
973 |
/* All Registers access - only for local access */
|
974 |
# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
|
975 |
# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
|
976 |
# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
|
977 |
# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
|
978 |
/* Gpr Registers access */
|
979 |
# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context) |
980 |
# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */ |
981 |
# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */ |
982 |
# define CTR_sig(context) REG_sig(ctr, context)
|
983 |
# define XER_sig(context) REG_sig(xer, context) /* Link register */ |
984 |
# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */ |
985 |
# define CR_sig(context) REG_sig(cr, context) /* Condition register */ |
986 |
/* Float Registers access */
|
987 |
# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
|
988 |
# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context)) |
989 |
/* Exception Registers access */
|
990 |
# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */ |
991 |
# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
|
992 |
# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */ |
993 |
#endif /* __APPLE__ */ |
994 |
|
995 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
996 |
void *puc)
|
997 |
{ |
998 |
struct ucontext *uc = puc;
|
999 |
unsigned long pc; |
1000 |
int is_write;
|
1001 |
|
1002 |
pc = IAR_sig(uc); |
1003 |
is_write = 0;
|
1004 |
#if 0
|
1005 |
/* ppc 4xx case */
|
1006 |
if (DSISR_sig(uc) & 0x00800000)
|
1007 |
is_write = 1;
|
1008 |
#else
|
1009 |
if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) |
1010 |
is_write = 1;
|
1011 |
#endif
|
1012 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1013 |
is_write, &uc->uc_sigmask, puc); |
1014 |
} |
1015 |
|
1016 |
#elif defined(__alpha__)
|
1017 |
|
1018 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
1019 |
void *puc)
|
1020 |
{ |
1021 |
struct ucontext *uc = puc;
|
1022 |
uint32_t *pc = uc->uc_mcontext.sc_pc; |
1023 |
uint32_t insn = *pc; |
1024 |
int is_write = 0; |
1025 |
|
1026 |
/* XXX: need kernel patch to get write flag faster */
|
1027 |
switch (insn >> 26) { |
1028 |
case 0x0d: // stw |
1029 |
case 0x0e: // stb |
1030 |
case 0x0f: // stq_u |
1031 |
case 0x24: // stf |
1032 |
case 0x25: // stg |
1033 |
case 0x26: // sts |
1034 |
case 0x27: // stt |
1035 |
case 0x2c: // stl |
1036 |
case 0x2d: // stq |
1037 |
case 0x2e: // stl_c |
1038 |
case 0x2f: // stq_c |
1039 |
is_write = 1;
|
1040 |
} |
1041 |
|
1042 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1043 |
is_write, &uc->uc_sigmask, puc); |
1044 |
} |
1045 |
#elif defined(__sparc__)
|
1046 |
|
1047 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
1048 |
void *puc)
|
1049 |
{ |
1050 |
uint32_t *regs = (uint32_t *)(info + 1);
|
1051 |
void *sigmask = (regs + 20); |
1052 |
unsigned long pc; |
1053 |
int is_write;
|
1054 |
uint32_t insn; |
1055 |
|
1056 |
/* XXX: is there a standard glibc define ? */
|
1057 |
pc = regs[1];
|
1058 |
/* XXX: need kernel patch to get write flag faster */
|
1059 |
is_write = 0;
|
1060 |
insn = *(uint32_t *)pc; |
1061 |
if ((insn >> 30) == 3) { |
1062 |
switch((insn >> 19) & 0x3f) { |
1063 |
case 0x05: // stb |
1064 |
case 0x06: // sth |
1065 |
case 0x04: // st |
1066 |
case 0x07: // std |
1067 |
case 0x24: // stf |
1068 |
case 0x27: // stdf |
1069 |
case 0x25: // stfsr |
1070 |
is_write = 1;
|
1071 |
break;
|
1072 |
} |
1073 |
} |
1074 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1075 |
is_write, sigmask, NULL);
|
1076 |
} |
1077 |
|
1078 |
#elif defined(__arm__)
|
1079 |
|
1080 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
1081 |
void *puc)
|
1082 |
{ |
1083 |
struct ucontext *uc = puc;
|
1084 |
unsigned long pc; |
1085 |
int is_write;
|
1086 |
|
1087 |
pc = uc->uc_mcontext.gregs[R15]; |
1088 |
/* XXX: compute is_write */
|
1089 |
is_write = 0;
|
1090 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1091 |
is_write, |
1092 |
&uc->uc_sigmask); |
1093 |
} |
1094 |
|
1095 |
#elif defined(__mc68000)
|
1096 |
|
1097 |
int cpu_signal_handler(int host_signum, struct siginfo *info, |
1098 |
void *puc)
|
1099 |
{ |
1100 |
struct ucontext *uc = puc;
|
1101 |
unsigned long pc; |
1102 |
int is_write;
|
1103 |
|
1104 |
pc = uc->uc_mcontext.gregs[16];
|
1105 |
/* XXX: compute is_write */
|
1106 |
is_write = 0;
|
1107 |
return handle_cpu_signal(pc, (unsigned long)info->si_addr, |
1108 |
is_write, |
1109 |
&uc->uc_sigmask, puc); |
1110 |
} |
1111 |
|
1112 |
#else
|
1113 |
|
1114 |
#error host CPU specific signal handler needed
|
1115 |
|
1116 |
#endif
|
1117 |
|
1118 |
#endif /* !defined(CONFIG_SOFTMMU) */ |