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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * i386 virtual CPU header
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 2c0262af | bellard | #ifndef CPU_I386_H
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21 | 2c0262af | bellard | #define CPU_I386_H
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22 | 2c0262af | bellard | |
23 | 14ce26e7 | bellard | #include "config.h" |
24 | 14ce26e7 | bellard | |
25 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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26 | 14ce26e7 | bellard | #define TARGET_LONG_BITS 64 |
27 | 14ce26e7 | bellard | #else
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28 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
29 | 14ce26e7 | bellard | #endif
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30 | 3cf1e035 | bellard | |
31 | d720b93d | bellard | /* target supports implicit self modifying code */
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32 | d720b93d | bellard | #define TARGET_HAS_SMC
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33 | d720b93d | bellard | /* support for self modifying code even if the modified instruction is
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34 | d720b93d | bellard | close to the modifying instruction */
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35 | d720b93d | bellard | #define TARGET_HAS_PRECISE_SMC
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36 | d720b93d | bellard | |
37 | 2c0262af | bellard | #include "cpu-defs.h" |
38 | 2c0262af | bellard | |
39 | 7a0e1f41 | bellard | #include "softfloat.h" |
40 | 7a0e1f41 | bellard | |
41 | 58fe2f10 | bellard | #if defined(__i386__) && !defined(CONFIG_SOFTMMU)
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42 | 58fe2f10 | bellard | #define USE_CODE_COPY
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43 | 58fe2f10 | bellard | #endif
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44 | 58fe2f10 | bellard | |
45 | 2c0262af | bellard | #define R_EAX 0 |
46 | 2c0262af | bellard | #define R_ECX 1 |
47 | 2c0262af | bellard | #define R_EDX 2 |
48 | 2c0262af | bellard | #define R_EBX 3 |
49 | 2c0262af | bellard | #define R_ESP 4 |
50 | 2c0262af | bellard | #define R_EBP 5 |
51 | 2c0262af | bellard | #define R_ESI 6 |
52 | 2c0262af | bellard | #define R_EDI 7 |
53 | 2c0262af | bellard | |
54 | 2c0262af | bellard | #define R_AL 0 |
55 | 2c0262af | bellard | #define R_CL 1 |
56 | 2c0262af | bellard | #define R_DL 2 |
57 | 2c0262af | bellard | #define R_BL 3 |
58 | 2c0262af | bellard | #define R_AH 4 |
59 | 2c0262af | bellard | #define R_CH 5 |
60 | 2c0262af | bellard | #define R_DH 6 |
61 | 2c0262af | bellard | #define R_BH 7 |
62 | 2c0262af | bellard | |
63 | 2c0262af | bellard | #define R_ES 0 |
64 | 2c0262af | bellard | #define R_CS 1 |
65 | 2c0262af | bellard | #define R_SS 2 |
66 | 2c0262af | bellard | #define R_DS 3 |
67 | 2c0262af | bellard | #define R_FS 4 |
68 | 2c0262af | bellard | #define R_GS 5 |
69 | 2c0262af | bellard | |
70 | 2c0262af | bellard | /* segment descriptor fields */
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71 | 2c0262af | bellard | #define DESC_G_MASK (1 << 23) |
72 | 2c0262af | bellard | #define DESC_B_SHIFT 22 |
73 | 2c0262af | bellard | #define DESC_B_MASK (1 << DESC_B_SHIFT) |
74 | 14ce26e7 | bellard | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
75 | 14ce26e7 | bellard | #define DESC_L_MASK (1 << DESC_L_SHIFT) |
76 | 2c0262af | bellard | #define DESC_AVL_MASK (1 << 20) |
77 | 2c0262af | bellard | #define DESC_P_MASK (1 << 15) |
78 | 2c0262af | bellard | #define DESC_DPL_SHIFT 13 |
79 | 2c0262af | bellard | #define DESC_S_MASK (1 << 12) |
80 | 2c0262af | bellard | #define DESC_TYPE_SHIFT 8 |
81 | 2c0262af | bellard | #define DESC_A_MASK (1 << 8) |
82 | 2c0262af | bellard | |
83 | e670b89e | bellard | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
84 | e670b89e | bellard | #define DESC_C_MASK (1 << 10) /* code: conforming */ |
85 | e670b89e | bellard | #define DESC_R_MASK (1 << 9) /* code: readable */ |
86 | 2c0262af | bellard | |
87 | e670b89e | bellard | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
88 | e670b89e | bellard | #define DESC_W_MASK (1 << 9) /* data: writable */ |
89 | e670b89e | bellard | |
90 | e670b89e | bellard | #define DESC_TSS_BUSY_MASK (1 << 9) |
91 | 2c0262af | bellard | |
92 | 2c0262af | bellard | /* eflags masks */
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93 | 2c0262af | bellard | #define CC_C 0x0001 |
94 | 2c0262af | bellard | #define CC_P 0x0004 |
95 | 2c0262af | bellard | #define CC_A 0x0010 |
96 | 2c0262af | bellard | #define CC_Z 0x0040 |
97 | 2c0262af | bellard | #define CC_S 0x0080 |
98 | 2c0262af | bellard | #define CC_O 0x0800 |
99 | 2c0262af | bellard | |
100 | 2c0262af | bellard | #define TF_SHIFT 8 |
101 | 2c0262af | bellard | #define IOPL_SHIFT 12 |
102 | 2c0262af | bellard | #define VM_SHIFT 17 |
103 | 2c0262af | bellard | |
104 | 2c0262af | bellard | #define TF_MASK 0x00000100 |
105 | 2c0262af | bellard | #define IF_MASK 0x00000200 |
106 | 2c0262af | bellard | #define DF_MASK 0x00000400 |
107 | 2c0262af | bellard | #define IOPL_MASK 0x00003000 |
108 | 2c0262af | bellard | #define NT_MASK 0x00004000 |
109 | 2c0262af | bellard | #define RF_MASK 0x00010000 |
110 | 2c0262af | bellard | #define VM_MASK 0x00020000 |
111 | 2c0262af | bellard | #define AC_MASK 0x00040000 |
112 | 2c0262af | bellard | #define VIF_MASK 0x00080000 |
113 | 2c0262af | bellard | #define VIP_MASK 0x00100000 |
114 | 2c0262af | bellard | #define ID_MASK 0x00200000 |
115 | 2c0262af | bellard | |
116 | 2c0262af | bellard | /* hidden flags - used internally by qemu to represent additionnal cpu
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117 | 2c0262af | bellard | states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
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118 | 2c0262af | bellard | using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
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119 | 2c0262af | bellard | with eflags. */
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120 | 2c0262af | bellard | /* current cpl */
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121 | 2c0262af | bellard | #define HF_CPL_SHIFT 0 |
122 | 2c0262af | bellard | /* true if soft mmu is being used */
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123 | 2c0262af | bellard | #define HF_SOFTMMU_SHIFT 2 |
124 | 2c0262af | bellard | /* true if hardware interrupts must be disabled for next instruction */
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125 | 2c0262af | bellard | #define HF_INHIBIT_IRQ_SHIFT 3 |
126 | 2c0262af | bellard | /* 16 or 32 segments */
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127 | 2c0262af | bellard | #define HF_CS32_SHIFT 4 |
128 | 2c0262af | bellard | #define HF_SS32_SHIFT 5 |
129 | dc196a57 | bellard | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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130 | 2c0262af | bellard | #define HF_ADDSEG_SHIFT 6 |
131 | 65262d57 | bellard | /* copy of CR0.PE (protected mode) */
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132 | 65262d57 | bellard | #define HF_PE_SHIFT 7 |
133 | 65262d57 | bellard | #define HF_TF_SHIFT 8 /* must be same as eflags */ |
134 | 7eee2a50 | bellard | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
135 | 7eee2a50 | bellard | #define HF_EM_SHIFT 10 |
136 | 7eee2a50 | bellard | #define HF_TS_SHIFT 11 |
137 | 65262d57 | bellard | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
138 | 14ce26e7 | bellard | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
139 | 14ce26e7 | bellard | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
140 | 664e0f19 | bellard | #define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */ |
141 | 65262d57 | bellard | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
142 | 2c0262af | bellard | |
143 | 2c0262af | bellard | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
144 | 2c0262af | bellard | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
145 | 2c0262af | bellard | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
146 | 2c0262af | bellard | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
147 | 2c0262af | bellard | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
148 | 2c0262af | bellard | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
149 | 65262d57 | bellard | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
150 | 58fe2f10 | bellard | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
151 | 7eee2a50 | bellard | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
152 | 7eee2a50 | bellard | #define HF_EM_MASK (1 << HF_EM_SHIFT) |
153 | 7eee2a50 | bellard | #define HF_TS_MASK (1 << HF_TS_SHIFT) |
154 | 14ce26e7 | bellard | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
155 | 14ce26e7 | bellard | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
156 | 664e0f19 | bellard | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
157 | 2c0262af | bellard | |
158 | 2c0262af | bellard | #define CR0_PE_MASK (1 << 0) |
159 | 7eee2a50 | bellard | #define CR0_MP_MASK (1 << 1) |
160 | 7eee2a50 | bellard | #define CR0_EM_MASK (1 << 2) |
161 | 2c0262af | bellard | #define CR0_TS_MASK (1 << 3) |
162 | 2ee73ac3 | bellard | #define CR0_ET_MASK (1 << 4) |
163 | 7eee2a50 | bellard | #define CR0_NE_MASK (1 << 5) |
164 | 2c0262af | bellard | #define CR0_WP_MASK (1 << 16) |
165 | 2c0262af | bellard | #define CR0_AM_MASK (1 << 18) |
166 | 2c0262af | bellard | #define CR0_PG_MASK (1 << 31) |
167 | 2c0262af | bellard | |
168 | 2c0262af | bellard | #define CR4_VME_MASK (1 << 0) |
169 | 2c0262af | bellard | #define CR4_PVI_MASK (1 << 1) |
170 | 2c0262af | bellard | #define CR4_TSD_MASK (1 << 2) |
171 | 2c0262af | bellard | #define CR4_DE_MASK (1 << 3) |
172 | 2c0262af | bellard | #define CR4_PSE_MASK (1 << 4) |
173 | 64a595f2 | bellard | #define CR4_PAE_MASK (1 << 5) |
174 | 64a595f2 | bellard | #define CR4_PGE_MASK (1 << 7) |
175 | 14ce26e7 | bellard | #define CR4_PCE_MASK (1 << 8) |
176 | 14ce26e7 | bellard | #define CR4_OSFXSR_MASK (1 << 9) |
177 | 14ce26e7 | bellard | #define CR4_OSXMMEXCPT_MASK (1 << 10) |
178 | 2c0262af | bellard | |
179 | 2c0262af | bellard | #define PG_PRESENT_BIT 0 |
180 | 2c0262af | bellard | #define PG_RW_BIT 1 |
181 | 2c0262af | bellard | #define PG_USER_BIT 2 |
182 | 2c0262af | bellard | #define PG_PWT_BIT 3 |
183 | 2c0262af | bellard | #define PG_PCD_BIT 4 |
184 | 2c0262af | bellard | #define PG_ACCESSED_BIT 5 |
185 | 2c0262af | bellard | #define PG_DIRTY_BIT 6 |
186 | 2c0262af | bellard | #define PG_PSE_BIT 7 |
187 | 2c0262af | bellard | #define PG_GLOBAL_BIT 8 |
188 | 2c0262af | bellard | |
189 | 2c0262af | bellard | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
190 | 2c0262af | bellard | #define PG_RW_MASK (1 << PG_RW_BIT) |
191 | 2c0262af | bellard | #define PG_USER_MASK (1 << PG_USER_BIT) |
192 | 2c0262af | bellard | #define PG_PWT_MASK (1 << PG_PWT_BIT) |
193 | 2c0262af | bellard | #define PG_PCD_MASK (1 << PG_PCD_BIT) |
194 | 2c0262af | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
195 | 2c0262af | bellard | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
196 | 2c0262af | bellard | #define PG_PSE_MASK (1 << PG_PSE_BIT) |
197 | 2c0262af | bellard | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
198 | 2c0262af | bellard | |
199 | 2c0262af | bellard | #define PG_ERROR_W_BIT 1 |
200 | 2c0262af | bellard | |
201 | 2c0262af | bellard | #define PG_ERROR_P_MASK 0x01 |
202 | 2c0262af | bellard | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
203 | 2c0262af | bellard | #define PG_ERROR_U_MASK 0x04 |
204 | 2c0262af | bellard | #define PG_ERROR_RSVD_MASK 0x08 |
205 | 2c0262af | bellard | |
206 | 2c0262af | bellard | #define MSR_IA32_APICBASE 0x1b |
207 | 2c0262af | bellard | #define MSR_IA32_APICBASE_BSP (1<<8) |
208 | 2c0262af | bellard | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
209 | 2c0262af | bellard | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
210 | 2c0262af | bellard | |
211 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_CS 0x174 |
212 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_ESP 0x175 |
213 | 2c0262af | bellard | #define MSR_IA32_SYSENTER_EIP 0x176 |
214 | 2c0262af | bellard | |
215 | 14ce26e7 | bellard | #define MSR_EFER 0xc0000080 |
216 | 14ce26e7 | bellard | |
217 | 14ce26e7 | bellard | #define MSR_EFER_SCE (1 << 0) |
218 | 14ce26e7 | bellard | #define MSR_EFER_LME (1 << 8) |
219 | 14ce26e7 | bellard | #define MSR_EFER_LMA (1 << 10) |
220 | 14ce26e7 | bellard | #define MSR_EFER_NXE (1 << 11) |
221 | 14ce26e7 | bellard | #define MSR_EFER_FFXSR (1 << 14) |
222 | 14ce26e7 | bellard | |
223 | 14ce26e7 | bellard | #define MSR_STAR 0xc0000081 |
224 | 14ce26e7 | bellard | #define MSR_LSTAR 0xc0000082 |
225 | 14ce26e7 | bellard | #define MSR_CSTAR 0xc0000083 |
226 | 14ce26e7 | bellard | #define MSR_FMASK 0xc0000084 |
227 | 14ce26e7 | bellard | #define MSR_FSBASE 0xc0000100 |
228 | 14ce26e7 | bellard | #define MSR_GSBASE 0xc0000101 |
229 | 14ce26e7 | bellard | #define MSR_KERNELGSBASE 0xc0000102 |
230 | 14ce26e7 | bellard | |
231 | 14ce26e7 | bellard | /* cpuid_features bits */
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232 | 14ce26e7 | bellard | #define CPUID_FP87 (1 << 0) |
233 | 14ce26e7 | bellard | #define CPUID_VME (1 << 1) |
234 | 14ce26e7 | bellard | #define CPUID_DE (1 << 2) |
235 | 14ce26e7 | bellard | #define CPUID_PSE (1 << 3) |
236 | 14ce26e7 | bellard | #define CPUID_TSC (1 << 4) |
237 | 14ce26e7 | bellard | #define CPUID_MSR (1 << 5) |
238 | 14ce26e7 | bellard | #define CPUID_PAE (1 << 6) |
239 | 14ce26e7 | bellard | #define CPUID_MCE (1 << 7) |
240 | 14ce26e7 | bellard | #define CPUID_CX8 (1 << 8) |
241 | 14ce26e7 | bellard | #define CPUID_APIC (1 << 9) |
242 | 14ce26e7 | bellard | #define CPUID_SEP (1 << 11) /* sysenter/sysexit */ |
243 | 14ce26e7 | bellard | #define CPUID_MTRR (1 << 12) |
244 | 14ce26e7 | bellard | #define CPUID_PGE (1 << 13) |
245 | 14ce26e7 | bellard | #define CPUID_MCA (1 << 14) |
246 | 14ce26e7 | bellard | #define CPUID_CMOV (1 << 15) |
247 | 14ce26e7 | bellard | /* ... */
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248 | 14ce26e7 | bellard | #define CPUID_MMX (1 << 23) |
249 | 14ce26e7 | bellard | #define CPUID_FXSR (1 << 24) |
250 | 14ce26e7 | bellard | #define CPUID_SSE (1 << 25) |
251 | 14ce26e7 | bellard | #define CPUID_SSE2 (1 << 26) |
252 | 14ce26e7 | bellard | |
253 | 9df217a3 | bellard | #define CPUID_EXT_SS3 (1 << 0) |
254 | 9df217a3 | bellard | #define CPUID_EXT_MONITOR (1 << 3) |
255 | 9df217a3 | bellard | #define CPUID_EXT_CX16 (1 << 13) |
256 | 9df217a3 | bellard | |
257 | 9df217a3 | bellard | #define CPUID_EXT2_SYSCALL (1 << 11) |
258 | 9df217a3 | bellard | #define CPUID_EXT2_NX (1 << 20) |
259 | 9df217a3 | bellard | #define CPUID_EXT2_LM (1 << 29) |
260 | 9df217a3 | bellard | |
261 | 2c0262af | bellard | #define EXCP00_DIVZ 0 |
262 | 2c0262af | bellard | #define EXCP01_SSTP 1 |
263 | 2c0262af | bellard | #define EXCP02_NMI 2 |
264 | 2c0262af | bellard | #define EXCP03_INT3 3 |
265 | 2c0262af | bellard | #define EXCP04_INTO 4 |
266 | 2c0262af | bellard | #define EXCP05_BOUND 5 |
267 | 2c0262af | bellard | #define EXCP06_ILLOP 6 |
268 | 2c0262af | bellard | #define EXCP07_PREX 7 |
269 | 2c0262af | bellard | #define EXCP08_DBLE 8 |
270 | 2c0262af | bellard | #define EXCP09_XERR 9 |
271 | 2c0262af | bellard | #define EXCP0A_TSS 10 |
272 | 2c0262af | bellard | #define EXCP0B_NOSEG 11 |
273 | 2c0262af | bellard | #define EXCP0C_STACK 12 |
274 | 2c0262af | bellard | #define EXCP0D_GPF 13 |
275 | 2c0262af | bellard | #define EXCP0E_PAGE 14 |
276 | 2c0262af | bellard | #define EXCP10_COPR 16 |
277 | 2c0262af | bellard | #define EXCP11_ALGN 17 |
278 | 2c0262af | bellard | #define EXCP12_MCHK 18 |
279 | 2c0262af | bellard | |
280 | 2c0262af | bellard | enum {
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281 | 2c0262af | bellard | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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282 | 2c0262af | bellard | CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
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283 | d36cd60e | bellard | |
284 | d36cd60e | bellard | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
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285 | d36cd60e | bellard | CC_OP_MULW, |
286 | d36cd60e | bellard | CC_OP_MULL, |
287 | 14ce26e7 | bellard | CC_OP_MULQ, |
288 | 2c0262af | bellard | |
289 | 2c0262af | bellard | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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290 | 2c0262af | bellard | CC_OP_ADDW, |
291 | 2c0262af | bellard | CC_OP_ADDL, |
292 | 14ce26e7 | bellard | CC_OP_ADDQ, |
293 | 2c0262af | bellard | |
294 | 2c0262af | bellard | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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295 | 2c0262af | bellard | CC_OP_ADCW, |
296 | 2c0262af | bellard | CC_OP_ADCL, |
297 | 14ce26e7 | bellard | CC_OP_ADCQ, |
298 | 2c0262af | bellard | |
299 | 2c0262af | bellard | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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300 | 2c0262af | bellard | CC_OP_SUBW, |
301 | 2c0262af | bellard | CC_OP_SUBL, |
302 | 14ce26e7 | bellard | CC_OP_SUBQ, |
303 | 2c0262af | bellard | |
304 | 2c0262af | bellard | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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305 | 2c0262af | bellard | CC_OP_SBBW, |
306 | 2c0262af | bellard | CC_OP_SBBL, |
307 | 14ce26e7 | bellard | CC_OP_SBBQ, |
308 | 2c0262af | bellard | |
309 | 2c0262af | bellard | CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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310 | 2c0262af | bellard | CC_OP_LOGICW, |
311 | 2c0262af | bellard | CC_OP_LOGICL, |
312 | 14ce26e7 | bellard | CC_OP_LOGICQ, |
313 | 2c0262af | bellard | |
314 | 2c0262af | bellard | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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315 | 2c0262af | bellard | CC_OP_INCW, |
316 | 2c0262af | bellard | CC_OP_INCL, |
317 | 14ce26e7 | bellard | CC_OP_INCQ, |
318 | 2c0262af | bellard | |
319 | 2c0262af | bellard | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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320 | 2c0262af | bellard | CC_OP_DECW, |
321 | 2c0262af | bellard | CC_OP_DECL, |
322 | 14ce26e7 | bellard | CC_OP_DECQ, |
323 | 2c0262af | bellard | |
324 | 6b652794 | bellard | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
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325 | 2c0262af | bellard | CC_OP_SHLW, |
326 | 2c0262af | bellard | CC_OP_SHLL, |
327 | 14ce26e7 | bellard | CC_OP_SHLQ, |
328 | 2c0262af | bellard | |
329 | 2c0262af | bellard | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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330 | 2c0262af | bellard | CC_OP_SARW, |
331 | 2c0262af | bellard | CC_OP_SARL, |
332 | 14ce26e7 | bellard | CC_OP_SARQ, |
333 | 2c0262af | bellard | |
334 | 2c0262af | bellard | CC_OP_NB, |
335 | 2c0262af | bellard | }; |
336 | 2c0262af | bellard | |
337 | 7a0e1f41 | bellard | #ifdef FLOATX80
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338 | 2c0262af | bellard | #define USE_X86LDOUBLE
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339 | 2c0262af | bellard | #endif
|
340 | 2c0262af | bellard | |
341 | 2c0262af | bellard | #ifdef USE_X86LDOUBLE
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342 | 7a0e1f41 | bellard | typedef floatx80 CPU86_LDouble;
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343 | 2c0262af | bellard | #else
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344 | 7a0e1f41 | bellard | typedef float64 CPU86_LDouble;
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345 | 2c0262af | bellard | #endif
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346 | 2c0262af | bellard | |
347 | 2c0262af | bellard | typedef struct SegmentCache { |
348 | 2c0262af | bellard | uint32_t selector; |
349 | 14ce26e7 | bellard | target_ulong base; |
350 | 2c0262af | bellard | uint32_t limit; |
351 | 2c0262af | bellard | uint32_t flags; |
352 | 2c0262af | bellard | } SegmentCache; |
353 | 2c0262af | bellard | |
354 | 826461bb | bellard | typedef union { |
355 | 664e0f19 | bellard | uint8_t _b[16];
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356 | 664e0f19 | bellard | uint16_t _w[8];
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357 | 664e0f19 | bellard | uint32_t _l[4];
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358 | 664e0f19 | bellard | uint64_t _q[2];
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359 | 7a0e1f41 | bellard | float32 _s[4];
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360 | 7a0e1f41 | bellard | float64 _d[2];
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361 | 14ce26e7 | bellard | } XMMReg; |
362 | 14ce26e7 | bellard | |
363 | 826461bb | bellard | typedef union { |
364 | 826461bb | bellard | uint8_t _b[8];
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365 | 826461bb | bellard | uint16_t _w[2];
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366 | 826461bb | bellard | uint32_t _l[1];
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367 | 826461bb | bellard | uint64_t q; |
368 | 826461bb | bellard | } MMXReg; |
369 | 826461bb | bellard | |
370 | 826461bb | bellard | #ifdef WORDS_BIGENDIAN
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371 | 826461bb | bellard | #define XMM_B(n) _b[15 - (n)] |
372 | 826461bb | bellard | #define XMM_W(n) _w[7 - (n)] |
373 | 826461bb | bellard | #define XMM_L(n) _l[3 - (n)] |
374 | 664e0f19 | bellard | #define XMM_S(n) _s[3 - (n)] |
375 | 826461bb | bellard | #define XMM_Q(n) _q[1 - (n)] |
376 | 664e0f19 | bellard | #define XMM_D(n) _d[1 - (n)] |
377 | 826461bb | bellard | |
378 | 826461bb | bellard | #define MMX_B(n) _b[7 - (n)] |
379 | 826461bb | bellard | #define MMX_W(n) _w[3 - (n)] |
380 | 826461bb | bellard | #define MMX_L(n) _l[1 - (n)] |
381 | 826461bb | bellard | #else
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382 | 826461bb | bellard | #define XMM_B(n) _b[n]
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383 | 826461bb | bellard | #define XMM_W(n) _w[n]
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384 | 826461bb | bellard | #define XMM_L(n) _l[n]
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385 | 664e0f19 | bellard | #define XMM_S(n) _s[n]
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386 | 826461bb | bellard | #define XMM_Q(n) _q[n]
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387 | 664e0f19 | bellard | #define XMM_D(n) _d[n]
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388 | 826461bb | bellard | |
389 | 826461bb | bellard | #define MMX_B(n) _b[n]
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390 | 826461bb | bellard | #define MMX_W(n) _w[n]
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391 | 826461bb | bellard | #define MMX_L(n) _l[n]
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392 | 826461bb | bellard | #endif
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393 | 664e0f19 | bellard | #define MMX_Q(n) q
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394 | 826461bb | bellard | |
395 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
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396 | 14ce26e7 | bellard | #define CPU_NB_REGS 16 |
397 | 14ce26e7 | bellard | #else
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398 | 14ce26e7 | bellard | #define CPU_NB_REGS 8 |
399 | 14ce26e7 | bellard | #endif
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400 | 14ce26e7 | bellard | |
401 | 2c0262af | bellard | typedef struct CPUX86State { |
402 | 14ce26e7 | bellard | #if TARGET_LONG_BITS > HOST_LONG_BITS
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403 | 14ce26e7 | bellard | /* temporaries if we cannot store them in host registers */
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404 | 14ce26e7 | bellard | target_ulong t0, t1, t2; |
405 | 14ce26e7 | bellard | #endif
|
406 | 14ce26e7 | bellard | |
407 | 2c0262af | bellard | /* standard registers */
|
408 | 14ce26e7 | bellard | target_ulong regs[CPU_NB_REGS]; |
409 | 14ce26e7 | bellard | target_ulong eip; |
410 | 14ce26e7 | bellard | target_ulong eflags; /* eflags register. During CPU emulation, CC
|
411 | 2c0262af | bellard | flags and DF are set to zero because they are
|
412 | 2c0262af | bellard | stored elsewhere */
|
413 | 2c0262af | bellard | |
414 | 2c0262af | bellard | /* emulator internal eflags handling */
|
415 | 14ce26e7 | bellard | target_ulong cc_src; |
416 | 14ce26e7 | bellard | target_ulong cc_dst; |
417 | 2c0262af | bellard | uint32_t cc_op; |
418 | 2c0262af | bellard | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
|
419 | 2c0262af | bellard | uint32_t hflags; /* hidden flags, see HF_xxx constants */
|
420 | 2c0262af | bellard | |
421 | 9df217a3 | bellard | /* segments */
|
422 | 9df217a3 | bellard | SegmentCache segs[6]; /* selector values */ |
423 | 9df217a3 | bellard | SegmentCache ldt; |
424 | 9df217a3 | bellard | SegmentCache tr; |
425 | 9df217a3 | bellard | SegmentCache gdt; /* only base and limit are used */
|
426 | 9df217a3 | bellard | SegmentCache idt; /* only base and limit are used */
|
427 | 9df217a3 | bellard | |
428 | 9df217a3 | bellard | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
429 | 9df217a3 | bellard | uint32_t a20_mask; |
430 | 9df217a3 | bellard | |
431 | 2c0262af | bellard | /* FPU state */
|
432 | 2c0262af | bellard | unsigned int fpstt; /* top of stack index */ |
433 | 2c0262af | bellard | unsigned int fpus; |
434 | 2c0262af | bellard | unsigned int fpuc; |
435 | 2c0262af | bellard | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
436 | 664e0f19 | bellard | union {
|
437 | 664e0f19 | bellard | #ifdef USE_X86LDOUBLE
|
438 | 664e0f19 | bellard | CPU86_LDouble d __attribute__((aligned(16)));
|
439 | 664e0f19 | bellard | #else
|
440 | 664e0f19 | bellard | CPU86_LDouble d; |
441 | 664e0f19 | bellard | #endif
|
442 | 664e0f19 | bellard | MMXReg mmx; |
443 | 664e0f19 | bellard | } fpregs[8];
|
444 | 2c0262af | bellard | |
445 | 2c0262af | bellard | /* emulator internal variables */
|
446 | 7a0e1f41 | bellard | float_status fp_status; |
447 | 2c0262af | bellard | CPU86_LDouble ft0; |
448 | 2c0262af | bellard | union {
|
449 | 2c0262af | bellard | float f;
|
450 | 2c0262af | bellard | double d;
|
451 | 2c0262af | bellard | int i32;
|
452 | 2c0262af | bellard | int64_t i64; |
453 | 2c0262af | bellard | } fp_convert; |
454 | 2c0262af | bellard | |
455 | 7a0e1f41 | bellard | float_status sse_status; |
456 | 664e0f19 | bellard | uint32_t mxcsr; |
457 | 14ce26e7 | bellard | XMMReg xmm_regs[CPU_NB_REGS]; |
458 | 14ce26e7 | bellard | XMMReg xmm_t0; |
459 | 664e0f19 | bellard | MMXReg mmx_t0; |
460 | 14ce26e7 | bellard | |
461 | 2c0262af | bellard | /* sysenter registers */
|
462 | 2c0262af | bellard | uint32_t sysenter_cs; |
463 | 2c0262af | bellard | uint32_t sysenter_esp; |
464 | 2c0262af | bellard | uint32_t sysenter_eip; |
465 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
466 | 14ce26e7 | bellard | target_ulong efer; |
467 | 14ce26e7 | bellard | target_ulong star; |
468 | 14ce26e7 | bellard | target_ulong lstar; |
469 | 14ce26e7 | bellard | target_ulong cstar; |
470 | 14ce26e7 | bellard | target_ulong fmask; |
471 | 14ce26e7 | bellard | target_ulong kernelgsbase; |
472 | 14ce26e7 | bellard | #endif
|
473 | 58fe2f10 | bellard | |
474 | 58fe2f10 | bellard | /* temporary data for USE_CODE_COPY mode */
|
475 | 7eee2a50 | bellard | #ifdef USE_CODE_COPY
|
476 | 58fe2f10 | bellard | uint32_t tmp0; |
477 | 58fe2f10 | bellard | uint32_t saved_esp; |
478 | 7eee2a50 | bellard | int native_fp_regs; /* if true, the FPU state is in the native CPU regs */ |
479 | 7eee2a50 | bellard | #endif
|
480 | 2c0262af | bellard | |
481 | 2c0262af | bellard | /* exception/interrupt handling */
|
482 | 2c0262af | bellard | jmp_buf jmp_env; |
483 | 2c0262af | bellard | int exception_index;
|
484 | 2c0262af | bellard | int error_code;
|
485 | 2c0262af | bellard | int exception_is_int;
|
486 | 826461bb | bellard | target_ulong exception_next_eip; |
487 | 2c0262af | bellard | struct TranslationBlock *current_tb; /* currently executing TB */ |
488 | 14ce26e7 | bellard | target_ulong dr[8]; /* debug registers */ |
489 | 2c0262af | bellard | int interrupt_request;
|
490 | 2c0262af | bellard | int user_mode_only; /* user mode only simulation */ |
491 | 2c0262af | bellard | |
492 | d720b93d | bellard | /* soft mmu support */
|
493 | d720b93d | bellard | /* in order to avoid passing too many arguments to the memory
|
494 | d720b93d | bellard | write helpers, we store some rarely used information in the CPU
|
495 | d720b93d | bellard | context) */
|
496 | d720b93d | bellard | unsigned long mem_write_pc; /* host pc at which the memory was |
497 | d720b93d | bellard | written */
|
498 | 14ce26e7 | bellard | target_ulong mem_write_vaddr; /* target virtual addr at which the
|
499 | 14ce26e7 | bellard | memory was written */
|
500 | 2c0262af | bellard | /* 0 = kernel, 1 = user */
|
501 | 2c0262af | bellard | CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
|
502 | 2c0262af | bellard | CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
|
503 | 2c0262af | bellard | |
504 | ffddfee3 | bellard | /* from this point: preserved by CPU reset */
|
505 | 2c0262af | bellard | /* ice debug support */
|
506 | 14ce26e7 | bellard | target_ulong breakpoints[MAX_BREAKPOINTS]; |
507 | 2c0262af | bellard | int nb_breakpoints;
|
508 | 2c0262af | bellard | int singlestep_enabled;
|
509 | 2c0262af | bellard | |
510 | 14ce26e7 | bellard | /* processor features (e.g. for CPUID insn) */
|
511 | 14ce26e7 | bellard | uint32_t cpuid_vendor1; |
512 | 14ce26e7 | bellard | uint32_t cpuid_vendor2; |
513 | 14ce26e7 | bellard | uint32_t cpuid_vendor3; |
514 | 14ce26e7 | bellard | uint32_t cpuid_version; |
515 | 14ce26e7 | bellard | uint32_t cpuid_features; |
516 | 9df217a3 | bellard | uint32_t cpuid_ext_features; |
517 | 14ce26e7 | bellard | |
518 | 9df217a3 | bellard | #ifdef USE_KQEMU
|
519 | 9df217a3 | bellard | int kqemu_enabled;
|
520 | 9df217a3 | bellard | #endif
|
521 | 14ce26e7 | bellard | /* in order to simplify APIC support, we leave this pointer to the
|
522 | 14ce26e7 | bellard | user */
|
523 | 14ce26e7 | bellard | struct APICState *apic_state;
|
524 | 2c0262af | bellard | /* user data */
|
525 | 2c0262af | bellard | void *opaque;
|
526 | 2c0262af | bellard | } CPUX86State; |
527 | 2c0262af | bellard | |
528 | 2c0262af | bellard | CPUX86State *cpu_x86_init(void);
|
529 | 2c0262af | bellard | int cpu_x86_exec(CPUX86State *s);
|
530 | 2c0262af | bellard | void cpu_x86_close(CPUX86State *s);
|
531 | d720b93d | bellard | int cpu_get_pic_interrupt(CPUX86State *s);
|
532 | 2ee73ac3 | bellard | /* MSDOS compatibility mode FPU exception support */
|
533 | 2ee73ac3 | bellard | void cpu_set_ferr(CPUX86State *s);
|
534 | 2c0262af | bellard | |
535 | 2c0262af | bellard | /* this function must always be used to load data in the segment
|
536 | 2c0262af | bellard | cache: it synchronizes the hflags with the segment cache values */
|
537 | 2c0262af | bellard | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
538 | 2c0262af | bellard | int seg_reg, unsigned int selector, |
539 | 14ce26e7 | bellard | uint32_t base, unsigned int limit, |
540 | 2c0262af | bellard | unsigned int flags) |
541 | 2c0262af | bellard | { |
542 | 2c0262af | bellard | SegmentCache *sc; |
543 | 2c0262af | bellard | unsigned int new_hflags; |
544 | 2c0262af | bellard | |
545 | 2c0262af | bellard | sc = &env->segs[seg_reg]; |
546 | 2c0262af | bellard | sc->selector = selector; |
547 | 2c0262af | bellard | sc->base = base; |
548 | 2c0262af | bellard | sc->limit = limit; |
549 | 2c0262af | bellard | sc->flags = flags; |
550 | 2c0262af | bellard | |
551 | 2c0262af | bellard | /* update the hidden flags */
|
552 | 14ce26e7 | bellard | { |
553 | 14ce26e7 | bellard | if (seg_reg == R_CS) {
|
554 | 14ce26e7 | bellard | #ifdef TARGET_X86_64
|
555 | 14ce26e7 | bellard | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
|
556 | 14ce26e7 | bellard | /* long mode */
|
557 | 14ce26e7 | bellard | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
558 | 14ce26e7 | bellard | env->hflags &= ~(HF_ADDSEG_MASK); |
559 | 14ce26e7 | bellard | } else
|
560 | 14ce26e7 | bellard | #endif
|
561 | 14ce26e7 | bellard | { |
562 | 14ce26e7 | bellard | /* legacy / compatibility case */
|
563 | 14ce26e7 | bellard | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
564 | 14ce26e7 | bellard | >> (DESC_B_SHIFT - HF_CS32_SHIFT); |
565 | 14ce26e7 | bellard | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | |
566 | 14ce26e7 | bellard | new_hflags; |
567 | 14ce26e7 | bellard | } |
568 | 14ce26e7 | bellard | } |
569 | 14ce26e7 | bellard | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) |
570 | 14ce26e7 | bellard | >> (DESC_B_SHIFT - HF_SS32_SHIFT); |
571 | 14ce26e7 | bellard | if (env->hflags & HF_CS64_MASK) {
|
572 | 14ce26e7 | bellard | /* zero base assumed for DS, ES and SS in long mode */
|
573 | 14ce26e7 | bellard | } else if (!(env->cr[0] & CR0_PE_MASK) || |
574 | 735a8fd3 | bellard | (env->eflags & VM_MASK) || |
575 | 735a8fd3 | bellard | !(env->hflags & HF_CS32_MASK)) { |
576 | 14ce26e7 | bellard | /* XXX: try to avoid this test. The problem comes from the
|
577 | 14ce26e7 | bellard | fact that is real mode or vm86 mode we only modify the
|
578 | 14ce26e7 | bellard | 'base' and 'selector' fields of the segment cache to go
|
579 | 14ce26e7 | bellard | faster. A solution may be to force addseg to one in
|
580 | 14ce26e7 | bellard | translate-i386.c. */
|
581 | 14ce26e7 | bellard | new_hflags |= HF_ADDSEG_MASK; |
582 | 14ce26e7 | bellard | } else {
|
583 | 735a8fd3 | bellard | new_hflags |= ((env->segs[R_DS].base | |
584 | 735a8fd3 | bellard | env->segs[R_ES].base | |
585 | 735a8fd3 | bellard | env->segs[R_SS].base) != 0) <<
|
586 | 14ce26e7 | bellard | HF_ADDSEG_SHIFT; |
587 | 14ce26e7 | bellard | } |
588 | 14ce26e7 | bellard | env->hflags = (env->hflags & |
589 | 14ce26e7 | bellard | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
590 | 2c0262af | bellard | } |
591 | 2c0262af | bellard | } |
592 | 2c0262af | bellard | |
593 | 2c0262af | bellard | /* wrapper, just in case memory mappings must be changed */
|
594 | 2c0262af | bellard | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) |
595 | 2c0262af | bellard | { |
596 | 2c0262af | bellard | #if HF_CPL_MASK == 3 |
597 | 2c0262af | bellard | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; |
598 | 2c0262af | bellard | #else
|
599 | 2c0262af | bellard | #error HF_CPL_MASK is hardcoded
|
600 | 2c0262af | bellard | #endif
|
601 | 2c0262af | bellard | } |
602 | 2c0262af | bellard | |
603 | 1f1af9fd | bellard | /* used for debug or cpu save/restore */
|
604 | 1f1af9fd | bellard | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
|
605 | 1f1af9fd | bellard | CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper); |
606 | 1f1af9fd | bellard | |
607 | 2c0262af | bellard | /* the following helpers are only usable in user mode simulation as
|
608 | 2c0262af | bellard | they can trigger unexpected exceptions */
|
609 | 2c0262af | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
610 | 2c0262af | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32); |
611 | 2c0262af | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32); |
612 | 2c0262af | bellard | |
613 | 2c0262af | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
|
614 | 2c0262af | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
|
615 | 2c0262af | bellard | is returned if the signal was handled by the virtual CPU. */
|
616 | 2c0262af | bellard | struct siginfo;
|
617 | 2c0262af | bellard | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
618 | 2c0262af | bellard | void *puc);
|
619 | 461c0471 | bellard | void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
620 | 2c0262af | bellard | |
621 | 28ab0e2e | bellard | uint64_t cpu_get_tsc(CPUX86State *env); |
622 | 28ab0e2e | bellard | |
623 | 14ce26e7 | bellard | void cpu_set_apic_base(CPUX86State *env, uint64_t val);
|
624 | 14ce26e7 | bellard | uint64_t cpu_get_apic_base(CPUX86State *env); |
625 | 9230e66e | bellard | void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
|
626 | 9230e66e | bellard | #ifndef NO_CPU_IO_DEFS
|
627 | 9230e66e | bellard | uint8_t cpu_get_apic_tpr(CPUX86State *env); |
628 | 9230e66e | bellard | #endif
|
629 | 14ce26e7 | bellard | |
630 | 64a595f2 | bellard | /* will be suppressed */
|
631 | 64a595f2 | bellard | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
|
632 | 64a595f2 | bellard | |
633 | 2c0262af | bellard | /* used to debug */
|
634 | 2c0262af | bellard | #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ |
635 | 2c0262af | bellard | #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ |
636 | 2c0262af | bellard | |
637 | 2c0262af | bellard | #define TARGET_PAGE_BITS 12 |
638 | 2c0262af | bellard | #include "cpu-all.h" |
639 | 2c0262af | bellard | |
640 | 2c0262af | bellard | #endif /* CPU_I386_H */ |