Revision b7ee1603 hw/pci.h

b/hw/pci.h
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#define PCI_COMMAND		0x04	/* 16 bits */
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#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
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#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
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#define  PCI_COMMAND_MASTER	0x4	/* Enable bus master */
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#define PCI_STATUS              0x06    /* 16 bits */
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#define PCI_REVISION_ID         0x08    /* 8 bits  */
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#define PCI_CLASS_DEVICE        0x0a    /* Device class */
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#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
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#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
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#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
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#define  PCI_HEADER_TYPE_NORMAL		0
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#define  PCI_HEADER_TYPE_BRIDGE		1
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#define  PCI_HEADER_TYPE_CARDBUS	2
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#define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
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#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
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#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
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#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
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#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
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#define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */
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#define PCI_SUBSYSTEM_ID        0x2e    /* 16 bits */
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#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
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#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
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#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
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#define PCI_MIN_GNT		0x3e	/* 8 bits */
......
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#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)


  		





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/* Size of the standard PCI config header */


  		





  
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#define PCI_CONFIG_HEADER_SIZE 0x40


  		





  
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/* Size of the standard PCI config space */


  		





  
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#define PCI_CONFIG_SPACE_SIZE 0x100


  		





  
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struct PCIDevice {


  		





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    DeviceState qdev;


  		





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    /* PCI config space */


  		





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    uint8_t config[256];


  		





  
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    uint8_t config[PCI_CONFIG_SPACE_SIZE];


  		





  
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    /* Used to implement R/W bytes */


  		





  
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    uint8_t wmask[PCI_CONFIG_SPACE_SIZE];


  		





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    /* the following fields are read only */


  		





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    PCIBus *bus;


  		












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