Revision b89e94af target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 2496 | 2496 |
gen_helper_check_ieee_exceptions(); |
| 2497 | 2497 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2498 | 2498 |
break; |
| 2499 |
case 0x42: |
|
| 2499 |
case 0x42: /* faddd */
|
|
| 2500 | 2500 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2501 | 2501 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2502 | 2502 |
gen_clear_float_exceptions(); |
| ... | ... | |
| 2520 | 2520 |
gen_helper_check_ieee_exceptions(); |
| 2521 | 2521 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2522 | 2522 |
break; |
| 2523 |
case 0x46: |
|
| 2523 |
case 0x46: /* fsubd */
|
|
| 2524 | 2524 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2525 | 2525 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2526 | 2526 |
gen_clear_float_exceptions(); |
| ... | ... | |
| 2571 | 2571 |
gen_helper_check_ieee_exceptions(); |
| 2572 | 2572 |
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
| 2573 | 2573 |
break; |
| 2574 |
case 0x4e: |
|
| 2574 |
case 0x4e: /* fdivd */
|
|
| 2575 | 2575 |
gen_op_load_fpr_DT0(DFPREG(rs1)); |
| 2576 | 2576 |
gen_op_load_fpr_DT1(DFPREG(rs2)); |
| 2577 | 2577 |
gen_clear_float_exceptions(); |
| ... | ... | |
| 3136 | 3136 |
cpu_src1 = get_src1(insn, cpu_src1); |
| 3137 | 3137 |
cpu_src2 = get_src2(insn, cpu_src2); |
| 3138 | 3138 |
switch (xop & ~0x10) {
|
| 3139 |
case 0x0: |
|
| 3139 |
case 0x0: /* add */
|
|
| 3140 | 3140 |
if (IS_IMM) {
|
| 3141 | 3141 |
simm = GET_FIELDs(insn, 19, 31); |
| 3142 | 3142 |
if (xop & 0x10) {
|
| ... | ... | |
| 3152 | 3152 |
} |
| 3153 | 3153 |
} |
| 3154 | 3154 |
break; |
| 3155 |
case 0x1: |
|
| 3155 |
case 0x1: /* and */
|
|
| 3156 | 3156 |
if (IS_IMM) {
|
| 3157 | 3157 |
simm = GET_FIELDs(insn, 19, 31); |
| 3158 | 3158 |
tcg_gen_andi_tl(cpu_dst, cpu_src1, simm); |
| ... | ... | |
| 3163 | 3163 |
gen_op_logic_cc(cpu_dst); |
| 3164 | 3164 |
} |
| 3165 | 3165 |
break; |
| 3166 |
case 0x2: |
|
| 3166 |
case 0x2: /* or */
|
|
| 3167 | 3167 |
if (IS_IMM) {
|
| 3168 | 3168 |
simm = GET_FIELDs(insn, 19, 31); |
| 3169 | 3169 |
tcg_gen_ori_tl(cpu_dst, cpu_src1, simm); |
| ... | ... | |
| 3173 | 3173 |
if (xop & 0x10) |
| 3174 | 3174 |
gen_op_logic_cc(cpu_dst); |
| 3175 | 3175 |
break; |
| 3176 |
case 0x3: |
|
| 3176 |
case 0x3: /* xor */
|
|
| 3177 | 3177 |
if (IS_IMM) {
|
| 3178 | 3178 |
simm = GET_FIELDs(insn, 19, 31); |
| 3179 | 3179 |
tcg_gen_xori_tl(cpu_dst, cpu_src1, simm); |
| ... | ... | |
| 3183 | 3183 |
if (xop & 0x10) |
| 3184 | 3184 |
gen_op_logic_cc(cpu_dst); |
| 3185 | 3185 |
break; |
| 3186 |
case 0x4: |
|
| 3186 |
case 0x4: /* sub */
|
|
| 3187 | 3187 |
if (IS_IMM) {
|
| 3188 | 3188 |
simm = GET_FIELDs(insn, 19, 31); |
| 3189 | 3189 |
if (xop & 0x10) {
|
| ... | ... | |
| 3199 | 3199 |
} |
| 3200 | 3200 |
} |
| 3201 | 3201 |
break; |
| 3202 |
case 0x5: |
|
| 3202 |
case 0x5: /* andn */
|
|
| 3203 | 3203 |
if (IS_IMM) {
|
| 3204 | 3204 |
simm = GET_FIELDs(insn, 19, 31); |
| 3205 | 3205 |
tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm); |
| ... | ... | |
| 3209 | 3209 |
if (xop & 0x10) |
| 3210 | 3210 |
gen_op_logic_cc(cpu_dst); |
| 3211 | 3211 |
break; |
| 3212 |
case 0x6: |
|
| 3212 |
case 0x6: /* orn */
|
|
| 3213 | 3213 |
if (IS_IMM) {
|
| 3214 | 3214 |
simm = GET_FIELDs(insn, 19, 31); |
| 3215 | 3215 |
tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm); |
| ... | ... | |
| 3219 | 3219 |
if (xop & 0x10) |
| 3220 | 3220 |
gen_op_logic_cc(cpu_dst); |
| 3221 | 3221 |
break; |
| 3222 |
case 0x7: |
|
| 3222 |
case 0x7: /* xorn */
|
|
| 3223 | 3223 |
if (IS_IMM) {
|
| 3224 | 3224 |
simm = GET_FIELDs(insn, 19, 31); |
| 3225 | 3225 |
tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm); |
| ... | ... | |
| 3230 | 3230 |
if (xop & 0x10) |
| 3231 | 3231 |
gen_op_logic_cc(cpu_dst); |
| 3232 | 3232 |
break; |
| 3233 |
case 0x8: |
|
| 3233 |
case 0x8: /* addx, V9 addc */
|
|
| 3234 | 3234 |
if (IS_IMM) {
|
| 3235 | 3235 |
simm = GET_FIELDs(insn, 19, 31); |
| 3236 | 3236 |
if (xop & 0x10) |
| ... | ... | |
| 3260 | 3260 |
} |
| 3261 | 3261 |
break; |
| 3262 | 3262 |
#endif |
| 3263 |
case 0xa: |
|
| 3263 |
case 0xa: /* umul */
|
|
| 3264 | 3264 |
CHECK_IU_FEATURE(dc, MUL); |
| 3265 | 3265 |
gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
| 3266 | 3266 |
if (xop & 0x10) |
| 3267 | 3267 |
gen_op_logic_cc(cpu_dst); |
| 3268 | 3268 |
break; |
| 3269 |
case 0xb: |
|
| 3269 |
case 0xb: /* smul */
|
|
| 3270 | 3270 |
CHECK_IU_FEATURE(dc, MUL); |
| 3271 | 3271 |
gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
| 3272 | 3272 |
if (xop & 0x10) |
| 3273 | 3273 |
gen_op_logic_cc(cpu_dst); |
| 3274 | 3274 |
break; |
| 3275 |
case 0xc: |
|
| 3275 |
case 0xc: /* subx, V9 subc */
|
|
| 3276 | 3276 |
if (IS_IMM) {
|
| 3277 | 3277 |
simm = GET_FIELDs(insn, 19, 31); |
| 3278 | 3278 |
if (xop & 0x10) {
|
| ... | ... | |
| 3300 | 3300 |
tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2); |
| 3301 | 3301 |
break; |
| 3302 | 3302 |
#endif |
| 3303 |
case 0xe: |
|
| 3303 |
case 0xe: /* udiv */
|
|
| 3304 | 3304 |
CHECK_IU_FEATURE(dc, DIV); |
| 3305 | 3305 |
gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2); |
| 3306 | 3306 |
if (xop & 0x10) |
| 3307 | 3307 |
gen_op_div_cc(cpu_dst); |
| 3308 | 3308 |
break; |
| 3309 |
case 0xf: |
|
| 3309 |
case 0xf: /* sdiv */
|
|
| 3310 | 3310 |
CHECK_IU_FEATURE(dc, DIV); |
| 3311 | 3311 |
gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2); |
| 3312 | 3312 |
if (xop & 0x10) |
| ... | ... | |
| 4385 | 4385 |
(xop > 0x17 && xop <= 0x1d ) || |
| 4386 | 4386 |
(xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
|
| 4387 | 4387 |
switch (xop) {
|
| 4388 |
case 0x0: /* load unsigned word */ |
|
| 4388 |
case 0x0: /* ld, V9 lduw, load unsigned word */
|
|
| 4389 | 4389 |
gen_address_mask(dc, cpu_addr); |
| 4390 | 4390 |
tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); |
| 4391 | 4391 |
break; |
| 4392 |
case 0x1: /* load unsigned byte */ |
|
| 4392 |
case 0x1: /* ldub, load unsigned byte */
|
|
| 4393 | 4393 |
gen_address_mask(dc, cpu_addr); |
| 4394 | 4394 |
tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); |
| 4395 | 4395 |
break; |
| 4396 |
case 0x2: /* load unsigned halfword */ |
|
| 4396 |
case 0x2: /* lduh, load unsigned halfword */
|
|
| 4397 | 4397 |
gen_address_mask(dc, cpu_addr); |
| 4398 | 4398 |
tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); |
| 4399 | 4399 |
break; |
| 4400 |
case 0x3: /* load double word */ |
|
| 4400 |
case 0x3: /* ldd, load double word */
|
|
| 4401 | 4401 |
if (rd & 1) |
| 4402 | 4402 |
goto illegal_insn; |
| 4403 | 4403 |
else {
|
| ... | ... | |
| 4417 | 4417 |
tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL); |
| 4418 | 4418 |
} |
| 4419 | 4419 |
break; |
| 4420 |
case 0x9: /* load signed byte */ |
|
| 4420 |
case 0x9: /* ldsb, load signed byte */
|
|
| 4421 | 4421 |
gen_address_mask(dc, cpu_addr); |
| 4422 | 4422 |
tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
| 4423 | 4423 |
break; |
| 4424 |
case 0xa: /* load signed halfword */ |
|
| 4424 |
case 0xa: /* ldsh, load signed halfword */
|
|
| 4425 | 4425 |
gen_address_mask(dc, cpu_addr); |
| 4426 | 4426 |
tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); |
| 4427 | 4427 |
break; |
| ... | ... | |
| 4436 | 4436 |
tcg_temp_free(r_const); |
| 4437 | 4437 |
} |
| 4438 | 4438 |
break; |
| 4439 |
case 0x0f: /* swap register with memory. Also |
|
| 4439 |
case 0x0f: /* swap, swap register with memory. Also
|
|
| 4440 | 4440 |
atomically */ |
| 4441 | 4441 |
CHECK_IU_FEATURE(dc, SWAP); |
| 4442 | 4442 |
gen_movl_reg_TN(rd, cpu_val); |
| ... | ... | |
| 4446 | 4446 |
tcg_gen_mov_tl(cpu_val, cpu_tmp0); |
| 4447 | 4447 |
break; |
| 4448 | 4448 |
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
| 4449 |
case 0x10: /* load word alternate */ |
|
| 4449 |
case 0x10: /* lda, V9 lduwa, load word alternate */
|
|
| 4450 | 4450 |
#ifndef TARGET_SPARC64 |
| 4451 | 4451 |
if (IS_IMM) |
| 4452 | 4452 |
goto illegal_insn; |
| ... | ... | |
| 4456 | 4456 |
save_state(dc, cpu_cond); |
| 4457 | 4457 |
gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); |
| 4458 | 4458 |
break; |
| 4459 |
case 0x11: /* load unsigned byte alternate */ |
|
| 4459 |
case 0x11: /* lduba, load unsigned byte alternate */
|
|
| 4460 | 4460 |
#ifndef TARGET_SPARC64 |
| 4461 | 4461 |
if (IS_IMM) |
| 4462 | 4462 |
goto illegal_insn; |
| ... | ... | |
| 4466 | 4466 |
save_state(dc, cpu_cond); |
| 4467 | 4467 |
gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); |
| 4468 | 4468 |
break; |
| 4469 |
case 0x12: /* load unsigned halfword alternate */ |
|
| 4469 |
case 0x12: /* lduha, load unsigned halfword alternate */
|
|
| 4470 | 4470 |
#ifndef TARGET_SPARC64 |
| 4471 | 4471 |
if (IS_IMM) |
| 4472 | 4472 |
goto illegal_insn; |
| ... | ... | |
| 4476 | 4476 |
save_state(dc, cpu_cond); |
| 4477 | 4477 |
gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); |
| 4478 | 4478 |
break; |
| 4479 |
case 0x13: /* load double word alternate */ |
|
| 4479 |
case 0x13: /* ldda, load double word alternate */
|
|
| 4480 | 4480 |
#ifndef TARGET_SPARC64 |
| 4481 | 4481 |
if (IS_IMM) |
| 4482 | 4482 |
goto illegal_insn; |
| ... | ... | |
| 4488 | 4488 |
save_state(dc, cpu_cond); |
| 4489 | 4489 |
gen_ldda_asi(cpu_val, cpu_addr, insn, rd); |
| 4490 | 4490 |
goto skip_move; |
| 4491 |
case 0x19: /* load signed byte alternate */ |
|
| 4491 |
case 0x19: /* ldsba, load signed byte alternate */
|
|
| 4492 | 4492 |
#ifndef TARGET_SPARC64 |
| 4493 | 4493 |
if (IS_IMM) |
| 4494 | 4494 |
goto illegal_insn; |
| ... | ... | |
| 4498 | 4498 |
save_state(dc, cpu_cond); |
| 4499 | 4499 |
gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); |
| 4500 | 4500 |
break; |
| 4501 |
case 0x1a: /* load signed halfword alternate */ |
|
| 4501 |
case 0x1a: /* ldsha, load signed halfword alternate */
|
|
| 4502 | 4502 |
#ifndef TARGET_SPARC64 |
| 4503 | 4503 |
if (IS_IMM) |
| 4504 | 4504 |
goto illegal_insn; |
| ... | ... | |
| 4518 | 4518 |
save_state(dc, cpu_cond); |
| 4519 | 4519 |
gen_ldstub_asi(cpu_val, cpu_addr, insn); |
| 4520 | 4520 |
break; |
| 4521 |
case 0x1f: /* swap reg with alt. memory. Also |
|
| 4521 |
case 0x1f: /* swapa, swap reg with alt. memory. Also
|
|
| 4522 | 4522 |
atomically */ |
| 4523 | 4523 |
CHECK_IU_FEATURE(dc, SWAP); |
| 4524 | 4524 |
#ifndef TARGET_SPARC64 |
| ... | ... | |
| 4586 | 4586 |
goto jmp_insn; |
| 4587 | 4587 |
save_state(dc, cpu_cond); |
| 4588 | 4588 |
switch (xop) {
|
| 4589 |
case 0x20: /* load fpreg */ |
|
| 4589 |
case 0x20: /* ldf, load fpreg */
|
|
| 4590 | 4590 |
gen_address_mask(dc, cpu_addr); |
| 4591 | 4591 |
tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
| 4592 | 4592 |
tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0); |
| ... | ... | |
| 4605 | 4605 |
} |
| 4606 | 4606 |
#endif |
| 4607 | 4607 |
break; |
| 4608 |
case 0x22: /* load quad fpreg */ |
|
| 4608 |
case 0x22: /* ldqf, load quad fpreg */
|
|
| 4609 | 4609 |
{
|
| 4610 | 4610 |
TCGv_i32 r_const; |
| 4611 | 4611 |
|
| ... | ... | |
| 4616 | 4616 |
gen_op_store_QT0_fpr(QFPREG(rd)); |
| 4617 | 4617 |
} |
| 4618 | 4618 |
break; |
| 4619 |
case 0x23: /* load double fpreg */ |
|
| 4619 |
case 0x23: /* lddf, load double fpreg */
|
|
| 4620 | 4620 |
{
|
| 4621 | 4621 |
TCGv_i32 r_const; |
| 4622 | 4622 |
|
| ... | ... | |
| 4633 | 4633 |
xop == 0xe || xop == 0x1e) {
|
| 4634 | 4634 |
gen_movl_reg_TN(rd, cpu_val); |
| 4635 | 4635 |
switch (xop) {
|
| 4636 |
case 0x4: /* store word */ |
|
| 4636 |
case 0x4: /* st, store word */
|
|
| 4637 | 4637 |
gen_address_mask(dc, cpu_addr); |
| 4638 | 4638 |
tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
| 4639 | 4639 |
break; |
| 4640 |
case 0x5: /* store byte */ |
|
| 4640 |
case 0x5: /* stb, store byte */
|
|
| 4641 | 4641 |
gen_address_mask(dc, cpu_addr); |
| 4642 | 4642 |
tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); |
| 4643 | 4643 |
break; |
| 4644 |
case 0x6: /* store halfword */ |
|
| 4644 |
case 0x6: /* sth, store halfword */
|
|
| 4645 | 4645 |
gen_address_mask(dc, cpu_addr); |
| 4646 | 4646 |
tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); |
| 4647 | 4647 |
break; |
| 4648 |
case 0x7: /* store double word */ |
|
| 4648 |
case 0x7: /* std, store double word */
|
|
| 4649 | 4649 |
if (rd & 1) |
| 4650 | 4650 |
goto illegal_insn; |
| 4651 | 4651 |
else {
|
| ... | ... | |
| 4662 | 4662 |
} |
| 4663 | 4663 |
break; |
| 4664 | 4664 |
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) |
| 4665 |
case 0x14: /* store word alternate */ |
|
| 4665 |
case 0x14: /* sta, V9 stwa, store word alternate */
|
|
| 4666 | 4666 |
#ifndef TARGET_SPARC64 |
| 4667 | 4667 |
if (IS_IMM) |
| 4668 | 4668 |
goto illegal_insn; |
| ... | ... | |
| 4672 | 4672 |
save_state(dc, cpu_cond); |
| 4673 | 4673 |
gen_st_asi(cpu_val, cpu_addr, insn, 4); |
| 4674 | 4674 |
break; |
| 4675 |
case 0x15: /* store byte alternate */ |
|
| 4675 |
case 0x15: /* stba, store byte alternate */
|
|
| 4676 | 4676 |
#ifndef TARGET_SPARC64 |
| 4677 | 4677 |
if (IS_IMM) |
| 4678 | 4678 |
goto illegal_insn; |
| ... | ... | |
| 4682 | 4682 |
save_state(dc, cpu_cond); |
| 4683 | 4683 |
gen_st_asi(cpu_val, cpu_addr, insn, 1); |
| 4684 | 4684 |
break; |
| 4685 |
case 0x16: /* store halfword alternate */ |
|
| 4685 |
case 0x16: /* stha, store halfword alternate */
|
|
| 4686 | 4686 |
#ifndef TARGET_SPARC64 |
| 4687 | 4687 |
if (IS_IMM) |
| 4688 | 4688 |
goto illegal_insn; |
| ... | ... | |
| 4692 | 4692 |
save_state(dc, cpu_cond); |
| 4693 | 4693 |
gen_st_asi(cpu_val, cpu_addr, insn, 2); |
| 4694 | 4694 |
break; |
| 4695 |
case 0x17: /* store double word alternate */ |
|
| 4695 |
case 0x17: /* stda, store double word alternate */
|
|
| 4696 | 4696 |
#ifndef TARGET_SPARC64 |
| 4697 | 4697 |
if (IS_IMM) |
| 4698 | 4698 |
goto illegal_insn; |
| ... | ... | |
| 4725 | 4725 |
goto jmp_insn; |
| 4726 | 4726 |
save_state(dc, cpu_cond); |
| 4727 | 4727 |
switch (xop) {
|
| 4728 |
case 0x24: /* store fpreg */ |
|
| 4728 |
case 0x24: /* stf, store fpreg */
|
|
| 4729 | 4729 |
gen_address_mask(dc, cpu_addr); |
| 4730 | 4730 |
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]); |
| 4731 | 4731 |
tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx); |
| ... | ... | |
| 4768 | 4768 |
goto nfq_insn; |
| 4769 | 4769 |
#endif |
| 4770 | 4770 |
#endif |
| 4771 |
case 0x27: /* store double fpreg */ |
|
| 4771 |
case 0x27: /* stdf, store double fpreg */
|
|
| 4772 | 4772 |
{
|
| 4773 | 4773 |
TCGv_i32 r_const; |
| 4774 | 4774 |
|
Also available in: Unified diff