Archipelago » qemu

/*

 *  i386 translation

 *

 *  Copyright (c) 2003 Fabrice Bellard

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include <signal.h>

#include <assert.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#include "helper.h"

#include "tcg-op.h"

#define PREFIX_REPZ   0x01

#define PREFIX_REPNZ  0x02

#define PREFIX_LOCK   0x04

#define PREFIX_DATA   0x08

#define PREFIX_ADR    0x10

#ifdef TARGET_X86_64

#define X86_64_ONLY(x) x

#define X86_64_DEF(x...) x

#define CODE64(s) ((s)->code64)

#define REX_X(s) ((s)->rex_x)

#define REX_B(s) ((s)->rex_b)

/* XXX: gcc generates push/pop in some opcodes, so we cannot use them */

#if 1

#define BUGGY_64(x) NULL

#endif

#else

#define X86_64_ONLY(x) NULL

#define X86_64_DEF(x...)

#define CODE64(s) 0

#define REX_X(s) 0

#define REX_B(s) 0

#endif

//#define MACRO_TEST   1

/* global register indexes */

static TCGv cpu_env, cpu_T[2], cpu_A0;

/* local register indexes (only used inside old micro ops) */

static TCGv cpu_tmp0, cpu_tmp1, cpu_tmp2, cpu_tmp3, cpu_ptr0, cpu_ptr1;

#ifdef TARGET_X86_64

static int x86_64_hregs;

#endif

typedef struct DisasContext {

    /* current insn context */

    int override; /* -1 if no override */

    int prefix;

    int aflag, dflag;

    target_ulong pc; /* pc = eip + cs_base */

    int is_jmp; /* 1 = means jump (stop translation), 2 means CPU

                   static state change (stop translation) */

    /* current block context */

    target_ulong cs_base; /* base of CS segment */

    int pe;     /* protected mode */

    int code32; /* 32 bit code segment */

#ifdef TARGET_X86_64

    int lma;    /* long mode active */

    int code64; /* 64 bit code segment */

    int rex_x, rex_b;

#endif

    int ss32;   /* 32 bit stack segment */

    int cc_op;  /* current CC operation */

    int addseg; /* non zero if either DS/ES/SS have a non zero base */

    int f_st;   /* currently unused */

    int vm86;   /* vm86 mode */

    int cpl;

    int iopl;

    int tf;     /* TF cpu flag */

    int singlestep_enabled; /* "hardware" single step enabled */

    int jmp_opt; /* use direct block chaining for direct jumps */

    int mem_index; /* select memory access functions */

    uint64_t flags; /* all execution flags */

    struct TranslationBlock *tb;

    int popl_esp_hack; /* for correct popl with esp base handling */

    int rip_offset; /* only used in x86_64, but left for simplicity */

    int cpuid_features;

    int cpuid_ext_features;

    int cpuid_ext2_features;

} DisasContext;

static void gen_eob(DisasContext *s);

static void gen_jmp(DisasContext *s, target_ulong eip);

static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);

/* i386 arith/logic operations */

enum {

    OP_ADDL,

    OP_ORL,

    OP_ADCL,

    OP_SBBL,

    OP_ANDL,

    OP_SUBL,

    OP_XORL,

    OP_CMPL,

};

/* i386 shift ops */

enum {

    OP_ROL,

    OP_ROR,

    OP_RCL,

    OP_RCR,

    OP_SHL,

    OP_SHR,

    OP_SHL1, /* undocumented */

    OP_SAR = 7,

};

/* operand size */

enum {

    OT_BYTE = 0,

    OT_WORD,

    OT_LONG,

    OT_QUAD,

};

enum {

    /* I386 int registers */

    OR_EAX,   /* MUST be even numbered */

    OR_ECX,

    OR_EDX,

    OR_EBX,

    OR_ESP,

    OR_EBP,

    OR_ESI,

    OR_EDI,

    OR_TMP0 = 16,    /* temporary operand register */

    OR_TMP1,

    OR_A0, /* temporary register used when doing address evaluation */

};

static inline void gen_op_movl_T0_0(void)

{

    tcg_gen_movi_tl(cpu_T[0], 0);

}

static inline void gen_op_movl_T0_im(int32_t val)

{

    tcg_gen_movi_tl(cpu_T[0], val);

}

static inline void gen_op_movl_T0_imu(uint32_t val)

{

    tcg_gen_movi_tl(cpu_T[0], val);

}

static inline void gen_op_movl_T1_im(int32_t val)

{

    tcg_gen_movi_tl(cpu_T[1], val);

}

static inline void gen_op_movl_T1_imu(uint32_t val)

{

    tcg_gen_movi_tl(cpu_T[1], val);

}

static inline void gen_op_movl_A0_im(uint32_t val)

{

    tcg_gen_movi_tl(cpu_A0, val);

}

#ifdef TARGET_X86_64

static inline void gen_op_movq_A0_im(int64_t val)

{

    tcg_gen_movi_tl(cpu_A0, val);

}

#endif

static inline void gen_movtl_T0_im(target_ulong val)

{

    tcg_gen_movi_tl(cpu_T[0], val);

}

static inline void gen_movtl_T1_im(target_ulong val)

{

    tcg_gen_movi_tl(cpu_T[1], val);

}

static inline void gen_op_andl_T0_ffff(void)

{

    tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);

}

static inline void gen_op_andl_T0_im(uint32_t val)

{

    tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);

}

static inline void gen_op_movl_T0_T1(void)

{

    tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);

}

static inline void gen_op_andl_A0_ffff(void)

{

    tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);

}

#ifdef TARGET_X86_64

#define NB_OP_SIZES 4

#define DEF_REGS(prefix, suffix) \

  prefix ## EAX ## suffix,\

  prefix ## ECX ## suffix,\

  prefix ## EDX ## suffix,\

  prefix ## EBX ## suffix,\

  prefix ## ESP ## suffix,\

  prefix ## EBP ## suffix,\

  prefix ## ESI ## suffix,\

  prefix ## EDI ## suffix,\

  prefix ## R8 ## suffix,\

  prefix ## R9 ## suffix,\

  prefix ## R10 ## suffix,\

  prefix ## R11 ## suffix,\

  prefix ## R12 ## suffix,\

  prefix ## R13 ## suffix,\

  prefix ## R14 ## suffix,\

  prefix ## R15 ## suffix,

#else /* !TARGET_X86_64 */

#define NB_OP_SIZES 3

#define DEF_REGS(prefix, suffix) \

  prefix ## EAX ## suffix,\

  prefix ## ECX ## suffix,\

  prefix ## EDX ## suffix,\

  prefix ## EBX ## suffix,\

  prefix ## ESP ## suffix,\

  prefix ## EBP ## suffix,\

  prefix ## ESI ## suffix,\

  prefix ## EDI ## suffix,

#endif /* !TARGET_X86_64 */

#if defined(WORDS_BIGENDIAN)

#define REG_B_OFFSET (sizeof(target_ulong) - 1)

#define REG_H_OFFSET (sizeof(target_ulong) - 2)

#define REG_W_OFFSET (sizeof(target_ulong) - 2)

#define REG_L_OFFSET (sizeof(target_ulong) - 4)

#define REG_LH_OFFSET (sizeof(target_ulong) - 8)

#else

#define REG_B_OFFSET 0

#define REG_H_OFFSET 1

#define REG_W_OFFSET 0

#define REG_L_OFFSET 0

#define REG_LH_OFFSET 4

#endif

static inline void gen_op_mov_reg_TN(int ot, int t_index, int reg)

{

    switch(ot) {

    case OT_BYTE:

        if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {

            tcg_gen_st8_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);

        } else {

            tcg_gen_st8_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);

        }

        break;

    case OT_WORD:

        tcg_gen_st16_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);

        break;

#ifdef TARGET_X86_64

    case OT_LONG:

        tcg_gen_st32_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);

        /* high part of register set to zero */

        tcg_gen_movi_tl(cpu_tmp0, 0);

        tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);

        break;

    default:

    case OT_QUAD:

        tcg_gen_st_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]));

        break;

#else

    default:

    case OT_LONG:

        tcg_gen_st32_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);

        break;

#endif

    }

}

static inline void gen_op_mov_reg_T0(int ot, int reg)

{

    gen_op_mov_reg_TN(ot, 0, reg);

}

static inline void gen_op_mov_reg_T1(int ot, int reg)

{

    gen_op_mov_reg_TN(ot, 1, reg);

}

static inline void gen_op_mov_reg_A0(int size, int reg)

{

    switch(size) {

    case 0:

        tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);

        break;

#ifdef TARGET_X86_64

    case 1:

        tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);

        /* high part of register set to zero */

        tcg_gen_movi_tl(cpu_tmp0, 0);

        tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);

        break;

    default:

    case 2:

        tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));

        break;

#else

    default:

    case 1:

        tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);

        break;

#endif

    }

}

static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)

{

    switch(ot) {

    case OT_BYTE:

        if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {

            goto std_case;

        } else {

            tcg_gen_ld8u_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);

        }

        break;

    default:

    std_case:

        tcg_gen_ld_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]));

        break;

    }

}

static inline void gen_op_movl_A0_reg(int reg)

{

    tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);

}

static inline void gen_op_addl_A0_im(int32_t val)

{

    tcg_gen_addi_tl(cpu_A0, cpu_A0, val);

#ifdef TARGET_X86_64

    tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);

#endif

}

#ifdef TARGET_X86_64

static inline void gen_op_addq_A0_im(int64_t val)

{

    tcg_gen_addi_tl(cpu_A0, cpu_A0, val);

}

#endif

static void gen_add_A0_im(DisasContext *s, int val)

{

#ifdef TARGET_X86_64

    if (CODE64(s))

        gen_op_addq_A0_im(val);

    else

#endif

        gen_op_addl_A0_im(val);

}

static inline void gen_op_addl_T0_T1(void)

{

    tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

}

static inline void gen_op_jmp_T0(void)

{

    tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));

}

static inline void gen_op_addw_ESP_im(int32_t val)

{

    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]));

    tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);

    tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]) + REG_W_OFFSET);

}

static inline void gen_op_addl_ESP_im(int32_t val)

{

    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]));

    tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);

#ifdef TARGET_X86_64

    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);

#endif

    tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]));

}

#ifdef TARGET_X86_64

static inline void gen_op_addq_ESP_im(int32_t val)

{

    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]));

    tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);

    tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]));

}

#endif

static inline void gen_op_set_cc_op(int32_t val)

{

    tcg_gen_movi_tl(cpu_tmp0, val);

    tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, cc_op));

}

static inline void gen_op_addl_A0_reg_sN(int shift, int reg)

{

    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

    if (shift != 0) 

        tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);

    tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);

#ifdef TARGET_X86_64

    tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);

#endif

}

static inline void gen_op_movl_A0_seg(int reg)

{

    tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);

}

static inline void gen_op_addl_A0_seg(int reg)

{

    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));

    tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);

#ifdef TARGET_X86_64

    tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);

#endif

}

#ifdef TARGET_X86_64

static inline void gen_op_movq_A0_seg(int reg)

{

    tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));

}

static inline void gen_op_addq_A0_seg(int reg)

{

    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));

    tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);

}

static inline void gen_op_movq_A0_reg(int reg)

{

    tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));

}

static inline void gen_op_addq_A0_reg_sN(int shift, int reg)

{

    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

    if (shift != 0) 

        tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);

    tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);

}

#endif

static GenOpFunc *gen_op_cmov_reg_T1_T0[NB_OP_SIZES - 1][CPU_NB_REGS] = {

    [0] = {

        DEF_REGS(gen_op_cmovw_, _T1_T0)

    },

    [1] = {

        DEF_REGS(gen_op_cmovl_, _T1_T0)

    },

#ifdef TARGET_X86_64

    [2] = {

        DEF_REGS(gen_op_cmovq_, _T1_T0)

    },

#endif

};

#define DEF_ARITHC(SUFFIX)\

    {\

        gen_op_adcb ## SUFFIX ## _T0_T1_cc,\

        gen_op_sbbb ## SUFFIX ## _T0_T1_cc,\

    },\

    {\

        gen_op_adcw ## SUFFIX ## _T0_T1_cc,\

        gen_op_sbbw ## SUFFIX ## _T0_T1_cc,\

    },\

    {\

        gen_op_adcl ## SUFFIX ## _T0_T1_cc,\

        gen_op_sbbl ## SUFFIX ## _T0_T1_cc,\

    },\

    {\

        X86_64_ONLY(gen_op_adcq ## SUFFIX ## _T0_T1_cc),\

        X86_64_ONLY(gen_op_sbbq ## SUFFIX ## _T0_T1_cc),\

    },

static GenOpFunc *gen_op_arithc_T0_T1_cc[4][2] = {

    DEF_ARITHC( )

};

static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[3 * 4][2] = {

    DEF_ARITHC(_raw)

#ifndef CONFIG_USER_ONLY

    DEF_ARITHC(_kernel)

    DEF_ARITHC(_user)

#endif

};

static const int cc_op_arithb[8] = {

    CC_OP_ADDB,

    CC_OP_LOGICB,

    CC_OP_ADDB,

    CC_OP_SUBB,

    CC_OP_LOGICB,

    CC_OP_SUBB,

    CC_OP_LOGICB,

    CC_OP_SUBB,

};

#define DEF_CMPXCHG(SUFFIX)\

    gen_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc,\

    gen_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc,\

    gen_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc,\

    X86_64_ONLY(gen_op_cmpxchgq ## SUFFIX ## _T0_T1_EAX_cc),

static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[4] = {

    DEF_CMPXCHG( )

};

static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[3 * 4] = {

    DEF_CMPXCHG(_raw)

#ifndef CONFIG_USER_ONLY

    DEF_CMPXCHG(_kernel)

    DEF_CMPXCHG(_user)

#endif

};

#define DEF_SHIFT(SUFFIX)\

    {\

        gen_op_rolb ## SUFFIX ## _T0_T1_cc,\

        gen_op_rorb ## SUFFIX ## _T0_T1_cc,\

        gen_op_rclb ## SUFFIX ## _T0_T1_cc,\

        gen_op_rcrb ## SUFFIX ## _T0_T1_cc,\

        gen_op_shlb ## SUFFIX ## _T0_T1_cc,\

        gen_op_shrb ## SUFFIX ## _T0_T1_cc,\

        gen_op_shlb ## SUFFIX ## _T0_T1_cc,\

        gen_op_sarb ## SUFFIX ## _T0_T1_cc,\

    },\

    {\

        gen_op_rolw ## SUFFIX ## _T0_T1_cc,\

        gen_op_rorw ## SUFFIX ## _T0_T1_cc,\

        gen_op_rclw ## SUFFIX ## _T0_T1_cc,\

        gen_op_rcrw ## SUFFIX ## _T0_T1_cc,\

        gen_op_shlw ## SUFFIX ## _T0_T1_cc,\

        gen_op_shrw ## SUFFIX ## _T0_T1_cc,\

        gen_op_shlw ## SUFFIX ## _T0_T1_cc,\

        gen_op_sarw ## SUFFIX ## _T0_T1_cc,\

    },\

    {\

        gen_op_roll ## SUFFIX ## _T0_T1_cc,\

        gen_op_rorl ## SUFFIX ## _T0_T1_cc,\

        gen_op_rcll ## SUFFIX ## _T0_T1_cc,\

        gen_op_rcrl ## SUFFIX ## _T0_T1_cc,\

        gen_op_shll ## SUFFIX ## _T0_T1_cc,\

        gen_op_shrl ## SUFFIX ## _T0_T1_cc,\

        gen_op_shll ## SUFFIX ## _T0_T1_cc,\

        gen_op_sarl ## SUFFIX ## _T0_T1_cc,\

    },\

    {\

        X86_64_ONLY(gen_op_rolq ## SUFFIX ## _T0_T1_cc),\

        X86_64_ONLY(gen_op_rorq ## SUFFIX ## _T0_T1_cc),\

        X86_64_ONLY(gen_op_rclq ## SUFFIX ## _T0_T1_cc),\

        X86_64_ONLY(gen_op_rcrq ## SUFFIX ## _T0_T1_cc),\

        X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\

        X86_64_ONLY(gen_op_shrq ## SUFFIX ## _T0_T1_cc),\

        X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\

        X86_64_ONLY(gen_op_sarq ## SUFFIX ## _T0_T1_cc),\

    },

static GenOpFunc *gen_op_shift_T0_T1_cc[4][8] = {

    DEF_SHIFT( )

};

static GenOpFunc *gen_op_shift_mem_T0_T1_cc[3 * 4][8] = {

    DEF_SHIFT(_raw)

#ifndef CONFIG_USER_ONLY

    DEF_SHIFT(_kernel)

    DEF_SHIFT(_user)

#endif

};

#define DEF_SHIFTD(SUFFIX, op)\

    {\

        NULL,\

        NULL,\

    },\

    {\

        gen_op_shldw ## SUFFIX ## _T0_T1_ ## op ## _cc,\

        gen_op_shrdw ## SUFFIX ## _T0_T1_ ## op ## _cc,\

     },\

    {\

        gen_op_shldl ## SUFFIX ## _T0_T1_ ## op ## _cc,\

        gen_op_shrdl ## SUFFIX ## _T0_T1_ ## op ## _cc,\

    },\

    {\

X86_64_DEF(gen_op_shldq ## SUFFIX ## _T0_T1_ ## op ## _cc,\

           gen_op_shrdq ## SUFFIX ## _T0_T1_ ## op ## _cc,)\

    },

static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[4][2] = {

    DEF_SHIFTD(, im)

};

static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[4][2] = {

    DEF_SHIFTD(, ECX)

};

static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[3 * 4][2] = {

    DEF_SHIFTD(_raw, im)

#ifndef CONFIG_USER_ONLY

    DEF_SHIFTD(_kernel, im)

    DEF_SHIFTD(_user, im)

#endif

};

static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[3 * 4][2] = {

    DEF_SHIFTD(_raw, ECX)

#ifndef CONFIG_USER_ONLY

    DEF_SHIFTD(_kernel, ECX)

    DEF_SHIFTD(_user, ECX)

#endif

};

static GenOpFunc *gen_op_btx_T0_T1_cc[3][4] = {

    [0] = {

        gen_op_btw_T0_T1_cc,

        gen_op_btsw_T0_T1_cc,

        gen_op_btrw_T0_T1_cc,

        gen_op_btcw_T0_T1_cc,

    },

    [1] = {

        gen_op_btl_T0_T1_cc,

        gen_op_btsl_T0_T1_cc,

        gen_op_btrl_T0_T1_cc,

        gen_op_btcl_T0_T1_cc,

    },

#ifdef TARGET_X86_64

    [2] = {

        gen_op_btq_T0_T1_cc,

        gen_op_btsq_T0_T1_cc,

        gen_op_btrq_T0_T1_cc,

        gen_op_btcq_T0_T1_cc,

    },

#endif

};

static GenOpFunc *gen_op_add_bit_A0_T1[3] = {

    gen_op_add_bitw_A0_T1,

    gen_op_add_bitl_A0_T1,

    X86_64_ONLY(gen_op_add_bitq_A0_T1),

};

static GenOpFunc *gen_op_bsx_T0_cc[3][2] = {

    [0] = {

        gen_op_bsfw_T0_cc,

        gen_op_bsrw_T0_cc,

    },

    [1] = {

        gen_op_bsfl_T0_cc,

        gen_op_bsrl_T0_cc,

    },

#ifdef TARGET_X86_64

    [2] = {

        gen_op_bsfq_T0_cc,

        gen_op_bsrq_T0_cc,

    },

#endif

};

static inline void gen_op_lds_T0_A0(int idx)

{

    int mem_index = (idx >> 2) - 1;

    switch(idx & 3) {

    case 0:

        tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);

        break;

    case 1:

        tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);

        break;

    default:

    case 2:

        tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);

        break;

    }

}

/* sign does not matter, except for lidt/lgdt call (TODO: fix it) */

static inline void gen_op_ld_T0_A0(int idx)

{

    int mem_index = (idx >> 2) - 1;

    switch(idx & 3) {

    case 0:

        tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, mem_index);

        break;

    case 1:

        tcg_gen_qemu_ld16u(cpu_T[0], cpu_A0, mem_index);

        break;

    case 2:

        tcg_gen_qemu_ld32u(cpu_T[0], cpu_A0, mem_index);

        break;

    default:

    case 3:

        tcg_gen_qemu_ld64(cpu_T[0], cpu_A0, mem_index);

        break;

    }

}

static inline void gen_op_ldu_T0_A0(int idx)

{

    gen_op_ld_T0_A0(idx);

}

static inline void gen_op_ld_T1_A0(int idx)

{

    int mem_index = (idx >> 2) - 1;

    switch(idx & 3) {

    case 0:

        tcg_gen_qemu_ld8u(cpu_T[1], cpu_A0, mem_index);

        break;

    case 1:

        tcg_gen_qemu_ld16u(cpu_T[1], cpu_A0, mem_index);

        break;

    case 2:

        tcg_gen_qemu_ld32u(cpu_T[1], cpu_A0, mem_index);

        break;

    default:

    case 3:

        tcg_gen_qemu_ld64(cpu_T[1], cpu_A0, mem_index);

        break;

    }

}

static inline void gen_op_st_T0_A0(int idx)

{

    int mem_index = (idx >> 2) - 1;

    switch(idx & 3) {

    case 0:

        tcg_gen_qemu_st8(cpu_T[0], cpu_A0, mem_index);

        break;

    case 1:

        tcg_gen_qemu_st16(cpu_T[0], cpu_A0, mem_index);

        break;

    case 2:

        tcg_gen_qemu_st32(cpu_T[0], cpu_A0, mem_index);

        break;

    default:

    case 3:

        tcg_gen_qemu_st64(cpu_T[0], cpu_A0, mem_index);

        break;

    }

}

static inline void gen_op_st_T1_A0(int idx)

{

    int mem_index = (idx >> 2) - 1;

    switch(idx & 3) {

    case 0:

        tcg_gen_qemu_st8(cpu_T[1], cpu_A0, mem_index);

        break;

    case 1:

        tcg_gen_qemu_st16(cpu_T[1], cpu_A0, mem_index);

        break;

    case 2:

        tcg_gen_qemu_st32(cpu_T[1], cpu_A0, mem_index);

        break;

    default:

    case 3:

        tcg_gen_qemu_st64(cpu_T[1], cpu_A0, mem_index);

        break;

    }

}

static inline void gen_jmp_im(target_ulong pc)

{

    tcg_gen_movi_tl(cpu_tmp0, pc);

    tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));

}

static inline void gen_string_movl_A0_ESI(DisasContext *s)

{

    int override;

    override = s->override;

#ifdef TARGET_X86_64

    if (s->aflag == 2) {

        if (override >= 0) {

            gen_op_movq_A0_seg(override);

            gen_op_addq_A0_reg_sN(0, R_ESI);

        } else {

            gen_op_movq_A0_reg(R_ESI);

        }

    } else

#endif

    if (s->aflag) {

        /* 32 bit address */

        if (s->addseg && override < 0)

            override = R_DS;

        if (override >= 0) {

            gen_op_movl_A0_seg(override);

            gen_op_addl_A0_reg_sN(0, R_ESI);

        } else {

            gen_op_movl_A0_reg(R_ESI);

        }

    } else {

        /* 16 address, always override */

        if (override < 0)

            override = R_DS;

        gen_op_movl_A0_reg(R_ESI);

        gen_op_andl_A0_ffff();

        gen_op_addl_A0_seg(override);

    }

}

static inline void gen_string_movl_A0_EDI(DisasContext *s)

{

#ifdef TARGET_X86_64

    if (s->aflag == 2) {

        gen_op_movq_A0_reg(R_EDI);

    } else

#endif

    if (s->aflag) {

        if (s->addseg) {

            gen_op_movl_A0_seg(R_ES);

            gen_op_addl_A0_reg_sN(0, R_EDI);

        } else {

            gen_op_movl_A0_reg(R_EDI);

        }

    } else {

        gen_op_movl_A0_reg(R_EDI);

        gen_op_andl_A0_ffff();

        gen_op_addl_A0_seg(R_ES);

    }

}