Revision b8b6a50b target-i386/TODO
| b/target-i386/TODO | ||
|---|---|---|
| 3 | 3 |
- rework eflags optimization (will be a consequence of TCG port) |
| 4 | 4 |
- SVM: rework the implementation: simplify code, move most intercept |
| 5 | 5 |
tests as dynamic, correct segment access, verify exception safety, |
| 6 |
remove most of the added CPU state.
|
|
| 6 |
cpu save/restore, SMM save/restore.
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|
| 7 | 7 |
- arpl eflags computation is invalid |
| 8 | 8 |
- x86_64: fxsave/fxrestore intel/amd differences |
| 9 | 9 |
- x86_64: lcall/ljmp intel/amd differences ? |
| 10 | 10 |
- x86_64: cmpxchgl intel/amd differences ? |
| 11 |
- x86_64: cmovl bug intel/amd differences ? |
|
| 11 |
- x86_64: cmovl intel/amd differences ? |
|
| 12 |
- cmpxchg16b + cmpxchg8b cpuid test |
|
| 12 | 13 |
- x86: monitor invalid |
| 13 | 14 |
- better code fetch (different exception handling + CS.limit support) |
| 14 | 15 |
- user/kernel PUSHL/POPL in helper.c |
| ... | ... | |
| 19 | 20 |
- full support of segment limit/rights |
| 20 | 21 |
- full x87 exception support |
| 21 | 22 |
- improve x87 bit exactness (use bochs code ?) |
| 23 |
- DRx register support |
|
| 24 |
- CR0.AC emulation |
|
| 25 |
- SSE alignment checks |
|
| 26 |
- fix SSE min/max with nans |
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| 22 | 27 |
|
| 23 | 28 |
Optimizations/Features: |
| 24 | 29 |
|
| 25 | 30 |
- finish TCG port |
| 31 |
- add SVM nested paging support |
|
| 32 |
- add VMX support |
|
| 33 |
- add AVX support |
|
| 34 |
- add SSE5 support |
|
| 26 | 35 |
- evaluate x87 stack pointer statically |
| 27 | 36 |
- find a way to avoid translating several time the same TB if CR0.TS |
| 28 | 37 |
is set or not. |
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