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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU MC146818 RTC emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sysemu.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 87ecb68b | pbrook | #include "isa.h" |
29 | 16b29ae1 | aliguori | #include "hpet_emul.h" |
30 | 80cabfad | bellard | |
31 | 80cabfad | bellard | //#define DEBUG_CMOS
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32 | 80cabfad | bellard | |
33 | 80cabfad | bellard | #define RTC_SECONDS 0 |
34 | 80cabfad | bellard | #define RTC_SECONDS_ALARM 1 |
35 | 80cabfad | bellard | #define RTC_MINUTES 2 |
36 | 80cabfad | bellard | #define RTC_MINUTES_ALARM 3 |
37 | 80cabfad | bellard | #define RTC_HOURS 4 |
38 | 80cabfad | bellard | #define RTC_HOURS_ALARM 5 |
39 | 80cabfad | bellard | #define RTC_ALARM_DONT_CARE 0xC0 |
40 | 80cabfad | bellard | |
41 | 80cabfad | bellard | #define RTC_DAY_OF_WEEK 6 |
42 | 80cabfad | bellard | #define RTC_DAY_OF_MONTH 7 |
43 | 80cabfad | bellard | #define RTC_MONTH 8 |
44 | 80cabfad | bellard | #define RTC_YEAR 9 |
45 | 80cabfad | bellard | |
46 | 80cabfad | bellard | #define RTC_REG_A 10 |
47 | 80cabfad | bellard | #define RTC_REG_B 11 |
48 | 80cabfad | bellard | #define RTC_REG_C 12 |
49 | 80cabfad | bellard | #define RTC_REG_D 13 |
50 | 80cabfad | bellard | |
51 | dff38e7b | bellard | #define REG_A_UIP 0x80 |
52 | 80cabfad | bellard | |
53 | dff38e7b | bellard | #define REG_B_SET 0x80 |
54 | dff38e7b | bellard | #define REG_B_PIE 0x40 |
55 | dff38e7b | bellard | #define REG_B_AIE 0x20 |
56 | dff38e7b | bellard | #define REG_B_UIE 0x10 |
57 | 6f1bf24d | aurel32 | #define REG_B_DM 0x04 |
58 | dff38e7b | bellard | |
59 | dff38e7b | bellard | struct RTCState {
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60 | dff38e7b | bellard | uint8_t cmos_data[128];
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61 | dff38e7b | bellard | uint8_t cmos_index; |
62 | 43f493af | bellard | struct tm current_tm;
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63 | 42fc73a1 | aurel32 | int base_year;
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64 | d537cf6c | pbrook | qemu_irq irq; |
65 | 18c6e2ff | ths | int it_shift;
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66 | dff38e7b | bellard | /* periodic timer */
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67 | dff38e7b | bellard | QEMUTimer *periodic_timer; |
68 | dff38e7b | bellard | int64_t next_periodic_time; |
69 | dff38e7b | bellard | /* second update */
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70 | dff38e7b | bellard | int64_t next_second_time; |
71 | 73822ec8 | aliguori | #ifdef TARGET_I386
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72 | 73822ec8 | aliguori | uint32_t irq_coalesced; |
73 | 73822ec8 | aliguori | uint32_t period; |
74 | 73822ec8 | aliguori | #endif
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75 | dff38e7b | bellard | QEMUTimer *second_timer; |
76 | dff38e7b | bellard | QEMUTimer *second_timer2; |
77 | dff38e7b | bellard | }; |
78 | dff38e7b | bellard | |
79 | 16b29ae1 | aliguori | static void rtc_irq_raise(qemu_irq irq) { |
80 | c50c2d68 | aurel32 | /* When HPET is operating in legacy mode, RTC interrupts are disabled
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81 | 16b29ae1 | aliguori | * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
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82 | c50c2d68 | aurel32 | * mode is established while interrupt is raised. We want it to
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83 | 16b29ae1 | aliguori | * be lowered in any case
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84 | c50c2d68 | aurel32 | */
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85 | 16b29ae1 | aliguori | #if defined TARGET_I386 || defined TARGET_X86_64
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86 | c50c2d68 | aurel32 | if (!hpet_in_legacy_mode())
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87 | 16b29ae1 | aliguori | #endif
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88 | 16b29ae1 | aliguori | qemu_irq_raise(irq); |
89 | 16b29ae1 | aliguori | } |
90 | 16b29ae1 | aliguori | |
91 | dff38e7b | bellard | static void rtc_set_time(RTCState *s); |
92 | dff38e7b | bellard | static void rtc_copy_date(RTCState *s); |
93 | dff38e7b | bellard | |
94 | dff38e7b | bellard | static void rtc_timer_update(RTCState *s, int64_t current_time) |
95 | dff38e7b | bellard | { |
96 | dff38e7b | bellard | int period_code, period;
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97 | dff38e7b | bellard | int64_t cur_clock, next_irq_clock; |
98 | dff38e7b | bellard | |
99 | dff38e7b | bellard | period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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100 | 16b29ae1 | aliguori | #if defined TARGET_I386 || defined TARGET_X86_64
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101 | c50c2d68 | aurel32 | /* disable periodic timer if hpet is in legacy mode, since interrupts are
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102 | 16b29ae1 | aliguori | * disabled anyway.
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103 | 16b29ae1 | aliguori | */
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104 | 16b29ae1 | aliguori | if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE) && !hpet_in_legacy_mode()) { |
105 | 16b29ae1 | aliguori | #else
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106 | 16b29ae1 | aliguori | if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) { |
107 | 16b29ae1 | aliguori | #endif
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108 | dff38e7b | bellard | if (period_code <= 2) |
109 | dff38e7b | bellard | period_code += 7;
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110 | dff38e7b | bellard | /* period in 32 Khz cycles */
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111 | dff38e7b | bellard | period = 1 << (period_code - 1); |
112 | 73822ec8 | aliguori | #ifdef TARGET_I386
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113 | 73822ec8 | aliguori | if(period != s->period)
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114 | 73822ec8 | aliguori | s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
115 | 73822ec8 | aliguori | s->period = period; |
116 | 73822ec8 | aliguori | #endif
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117 | dff38e7b | bellard | /* compute 32 khz clock */
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118 | dff38e7b | bellard | cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
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119 | dff38e7b | bellard | next_irq_clock = (cur_clock & ~(period - 1)) + period;
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120 | dff38e7b | bellard | s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1; |
121 | dff38e7b | bellard | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
122 | dff38e7b | bellard | } else {
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123 | 73822ec8 | aliguori | #ifdef TARGET_I386
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124 | 73822ec8 | aliguori | s->irq_coalesced = 0;
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125 | 73822ec8 | aliguori | #endif
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126 | dff38e7b | bellard | qemu_del_timer(s->periodic_timer); |
127 | dff38e7b | bellard | } |
128 | dff38e7b | bellard | } |
129 | dff38e7b | bellard | |
130 | dff38e7b | bellard | static void rtc_periodic_timer(void *opaque) |
131 | dff38e7b | bellard | { |
132 | dff38e7b | bellard | RTCState *s = opaque; |
133 | dff38e7b | bellard | |
134 | dff38e7b | bellard | rtc_timer_update(s, s->next_periodic_time); |
135 | 73822ec8 | aliguori | #ifdef TARGET_I386
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136 | 73822ec8 | aliguori | if ((s->cmos_data[RTC_REG_C] & 0xc0) && rtc_td_hack) { |
137 | 73822ec8 | aliguori | s->irq_coalesced++; |
138 | 73822ec8 | aliguori | return;
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139 | 73822ec8 | aliguori | } |
140 | 73822ec8 | aliguori | #endif
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141 | dff38e7b | bellard | s->cmos_data[RTC_REG_C] |= 0xc0;
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142 | 16b29ae1 | aliguori | rtc_irq_raise(s->irq); |
143 | dff38e7b | bellard | } |
144 | 80cabfad | bellard | |
145 | b41a2cd1 | bellard | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
146 | 80cabfad | bellard | { |
147 | b41a2cd1 | bellard | RTCState *s = opaque; |
148 | 80cabfad | bellard | |
149 | 80cabfad | bellard | if ((addr & 1) == 0) { |
150 | 80cabfad | bellard | s->cmos_index = data & 0x7f;
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151 | 80cabfad | bellard | } else {
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152 | 80cabfad | bellard | #ifdef DEBUG_CMOS
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153 | 80cabfad | bellard | printf("cmos: write index=0x%02x val=0x%02x\n",
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154 | 80cabfad | bellard | s->cmos_index, data); |
155 | 3b46e624 | ths | #endif
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156 | dff38e7b | bellard | switch(s->cmos_index) {
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157 | 80cabfad | bellard | case RTC_SECONDS_ALARM:
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158 | 80cabfad | bellard | case RTC_MINUTES_ALARM:
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159 | 80cabfad | bellard | case RTC_HOURS_ALARM:
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160 | 80cabfad | bellard | /* XXX: not supported */
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161 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
162 | 80cabfad | bellard | break;
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163 | 80cabfad | bellard | case RTC_SECONDS:
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164 | 80cabfad | bellard | case RTC_MINUTES:
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165 | 80cabfad | bellard | case RTC_HOURS:
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166 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
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167 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
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168 | 80cabfad | bellard | case RTC_MONTH:
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169 | 80cabfad | bellard | case RTC_YEAR:
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170 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
171 | dff38e7b | bellard | /* if in set mode, do not update the time */
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172 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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173 | dff38e7b | bellard | rtc_set_time(s); |
174 | dff38e7b | bellard | } |
175 | 80cabfad | bellard | break;
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176 | 80cabfad | bellard | case RTC_REG_A:
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177 | dff38e7b | bellard | /* UIP bit is read only */
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178 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
179 | dff38e7b | bellard | (s->cmos_data[RTC_REG_A] & REG_A_UIP); |
180 | dff38e7b | bellard | rtc_timer_update(s, qemu_get_clock(vm_clock)); |
181 | dff38e7b | bellard | break;
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182 | 80cabfad | bellard | case RTC_REG_B:
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183 | dff38e7b | bellard | if (data & REG_B_SET) {
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184 | dff38e7b | bellard | /* set mode: reset UIP mode */
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185 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
186 | dff38e7b | bellard | data &= ~REG_B_UIE; |
187 | dff38e7b | bellard | } else {
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188 | dff38e7b | bellard | /* if disabling set mode, update the time */
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189 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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190 | dff38e7b | bellard | rtc_set_time(s); |
191 | dff38e7b | bellard | } |
192 | dff38e7b | bellard | } |
193 | dff38e7b | bellard | s->cmos_data[RTC_REG_B] = data; |
194 | dff38e7b | bellard | rtc_timer_update(s, qemu_get_clock(vm_clock)); |
195 | 80cabfad | bellard | break;
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196 | 80cabfad | bellard | case RTC_REG_C:
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197 | 80cabfad | bellard | case RTC_REG_D:
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198 | 80cabfad | bellard | /* cannot write to them */
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199 | 80cabfad | bellard | break;
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200 | 80cabfad | bellard | default:
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201 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
202 | 80cabfad | bellard | break;
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203 | 80cabfad | bellard | } |
204 | 80cabfad | bellard | } |
205 | 80cabfad | bellard | } |
206 | 80cabfad | bellard | |
207 | dff38e7b | bellard | static inline int to_bcd(RTCState *s, int a) |
208 | 80cabfad | bellard | { |
209 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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210 | dff38e7b | bellard | return a;
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211 | dff38e7b | bellard | } else {
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212 | dff38e7b | bellard | return ((a / 10) << 4) | (a % 10); |
213 | dff38e7b | bellard | } |
214 | 80cabfad | bellard | } |
215 | 80cabfad | bellard | |
216 | dff38e7b | bellard | static inline int from_bcd(RTCState *s, int a) |
217 | 80cabfad | bellard | { |
218 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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219 | dff38e7b | bellard | return a;
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220 | dff38e7b | bellard | } else {
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221 | dff38e7b | bellard | return ((a >> 4) * 10) + (a & 0x0f); |
222 | dff38e7b | bellard | } |
223 | dff38e7b | bellard | } |
224 | dff38e7b | bellard | |
225 | dff38e7b | bellard | static void rtc_set_time(RTCState *s) |
226 | dff38e7b | bellard | { |
227 | 43f493af | bellard | struct tm *tm = &s->current_tm;
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228 | dff38e7b | bellard | |
229 | dff38e7b | bellard | tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]); |
230 | dff38e7b | bellard | tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]); |
231 | 43f493af | bellard | tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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232 | 43f493af | bellard | if (!(s->cmos_data[RTC_REG_B] & 0x02) && |
233 | 43f493af | bellard | (s->cmos_data[RTC_HOURS] & 0x80)) {
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234 | 43f493af | bellard | tm->tm_hour += 12;
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235 | 43f493af | bellard | } |
236 | 6f1bf24d | aurel32 | tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
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237 | dff38e7b | bellard | tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
238 | dff38e7b | bellard | tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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239 | 42fc73a1 | aurel32 | tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
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240 | 43f493af | bellard | } |
241 | 43f493af | bellard | |
242 | 43f493af | bellard | static void rtc_copy_date(RTCState *s) |
243 | 43f493af | bellard | { |
244 | 43f493af | bellard | const struct tm *tm = &s->current_tm; |
245 | 42fc73a1 | aurel32 | int year;
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246 | dff38e7b | bellard | |
247 | 43f493af | bellard | s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec); |
248 | 43f493af | bellard | s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min); |
249 | 43f493af | bellard | if (s->cmos_data[RTC_REG_B] & 0x02) { |
250 | 43f493af | bellard | /* 24 hour format */
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251 | 43f493af | bellard | s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour); |
252 | 43f493af | bellard | } else {
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253 | 43f493af | bellard | /* 12 hour format */
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254 | 43f493af | bellard | s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
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255 | 43f493af | bellard | if (tm->tm_hour >= 12) |
256 | 43f493af | bellard | s->cmos_data[RTC_HOURS] |= 0x80;
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257 | 43f493af | bellard | } |
258 | 6f1bf24d | aurel32 | s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday + 1);
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259 | 43f493af | bellard | s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday); |
260 | 43f493af | bellard | s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
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261 | 42fc73a1 | aurel32 | year = (tm->tm_year - s->base_year) % 100;
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262 | 42fc73a1 | aurel32 | if (year < 0) |
263 | 42fc73a1 | aurel32 | year += 100;
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264 | 42fc73a1 | aurel32 | s->cmos_data[RTC_YEAR] = to_bcd(s, year); |
265 | 43f493af | bellard | } |
266 | 43f493af | bellard | |
267 | 43f493af | bellard | /* month is between 0 and 11. */
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268 | 43f493af | bellard | static int get_days_in_month(int month, int year) |
269 | 43f493af | bellard | { |
270 | 5fafdf24 | ths | static const int days_tab[12] = { |
271 | 5fafdf24 | ths | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
272 | 43f493af | bellard | }; |
273 | 43f493af | bellard | int d;
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274 | 43f493af | bellard | if ((unsigned )month >= 12) |
275 | 43f493af | bellard | return 31; |
276 | 43f493af | bellard | d = days_tab[month]; |
277 | 43f493af | bellard | if (month == 1) { |
278 | 43f493af | bellard | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
279 | 43f493af | bellard | d++; |
280 | 43f493af | bellard | } |
281 | 43f493af | bellard | return d;
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282 | 43f493af | bellard | } |
283 | 43f493af | bellard | |
284 | 43f493af | bellard | /* update 'tm' to the next second */
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285 | 43f493af | bellard | static void rtc_next_second(struct tm *tm) |
286 | 43f493af | bellard | { |
287 | 43f493af | bellard | int days_in_month;
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288 | 43f493af | bellard | |
289 | 43f493af | bellard | tm->tm_sec++; |
290 | 43f493af | bellard | if ((unsigned)tm->tm_sec >= 60) { |
291 | 43f493af | bellard | tm->tm_sec = 0;
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292 | 43f493af | bellard | tm->tm_min++; |
293 | 43f493af | bellard | if ((unsigned)tm->tm_min >= 60) { |
294 | 43f493af | bellard | tm->tm_min = 0;
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295 | 43f493af | bellard | tm->tm_hour++; |
296 | 43f493af | bellard | if ((unsigned)tm->tm_hour >= 24) { |
297 | 43f493af | bellard | tm->tm_hour = 0;
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298 | 43f493af | bellard | /* next day */
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299 | 43f493af | bellard | tm->tm_wday++; |
300 | 43f493af | bellard | if ((unsigned)tm->tm_wday >= 7) |
301 | 43f493af | bellard | tm->tm_wday = 0;
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302 | 5fafdf24 | ths | days_in_month = get_days_in_month(tm->tm_mon, |
303 | 43f493af | bellard | tm->tm_year + 1900);
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304 | 43f493af | bellard | tm->tm_mday++; |
305 | 43f493af | bellard | if (tm->tm_mday < 1) { |
306 | 43f493af | bellard | tm->tm_mday = 1;
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307 | 43f493af | bellard | } else if (tm->tm_mday > days_in_month) { |
308 | 43f493af | bellard | tm->tm_mday = 1;
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309 | 43f493af | bellard | tm->tm_mon++; |
310 | 43f493af | bellard | if (tm->tm_mon >= 12) { |
311 | 43f493af | bellard | tm->tm_mon = 0;
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312 | 43f493af | bellard | tm->tm_year++; |
313 | 43f493af | bellard | } |
314 | 43f493af | bellard | } |
315 | 43f493af | bellard | } |
316 | 43f493af | bellard | } |
317 | 43f493af | bellard | } |
318 | dff38e7b | bellard | } |
319 | dff38e7b | bellard | |
320 | 43f493af | bellard | |
321 | dff38e7b | bellard | static void rtc_update_second(void *opaque) |
322 | dff38e7b | bellard | { |
323 | dff38e7b | bellard | RTCState *s = opaque; |
324 | 4721c457 | bellard | int64_t delay; |
325 | dff38e7b | bellard | |
326 | dff38e7b | bellard | /* if the oscillator is not in normal operation, we do not update */
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327 | dff38e7b | bellard | if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
328 | dff38e7b | bellard | s->next_second_time += ticks_per_sec; |
329 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
330 | dff38e7b | bellard | } else {
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331 | 43f493af | bellard | rtc_next_second(&s->current_tm); |
332 | 3b46e624 | ths | |
333 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
334 | dff38e7b | bellard | /* update in progress bit */
|
335 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
336 | dff38e7b | bellard | } |
337 | 4721c457 | bellard | /* should be 244 us = 8 / 32768 seconds, but currently the
|
338 | 4721c457 | bellard | timers do not have the necessary resolution. */
|
339 | 4721c457 | bellard | delay = (ticks_per_sec * 1) / 100; |
340 | 4721c457 | bellard | if (delay < 1) |
341 | 4721c457 | bellard | delay = 1;
|
342 | 5fafdf24 | ths | qemu_mod_timer(s->second_timer2, |
343 | 4721c457 | bellard | s->next_second_time + delay); |
344 | dff38e7b | bellard | } |
345 | dff38e7b | bellard | } |
346 | dff38e7b | bellard | |
347 | dff38e7b | bellard | static void rtc_update_second2(void *opaque) |
348 | dff38e7b | bellard | { |
349 | dff38e7b | bellard | RTCState *s = opaque; |
350 | dff38e7b | bellard | |
351 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
352 | dff38e7b | bellard | rtc_copy_date(s); |
353 | dff38e7b | bellard | } |
354 | dff38e7b | bellard | |
355 | dff38e7b | bellard | /* check alarm */
|
356 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
357 | dff38e7b | bellard | if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
358 | 43f493af | bellard | s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
359 | dff38e7b | bellard | ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
360 | 43f493af | bellard | s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
361 | dff38e7b | bellard | ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
362 | 43f493af | bellard | s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) { |
363 | dff38e7b | bellard | |
364 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] |= 0xa0;
|
365 | 16b29ae1 | aliguori | rtc_irq_raise(s->irq); |
366 | dff38e7b | bellard | } |
367 | dff38e7b | bellard | } |
368 | dff38e7b | bellard | |
369 | dff38e7b | bellard | /* update ended interrupt */
|
370 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
|
371 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] |= 0x90;
|
372 | 16b29ae1 | aliguori | rtc_irq_raise(s->irq); |
373 | dff38e7b | bellard | } |
374 | dff38e7b | bellard | |
375 | dff38e7b | bellard | /* clear update in progress bit */
|
376 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
377 | dff38e7b | bellard | |
378 | dff38e7b | bellard | s->next_second_time += ticks_per_sec; |
379 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
380 | 80cabfad | bellard | } |
381 | 80cabfad | bellard | |
382 | b41a2cd1 | bellard | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
383 | 80cabfad | bellard | { |
384 | b41a2cd1 | bellard | RTCState *s = opaque; |
385 | 80cabfad | bellard | int ret;
|
386 | 80cabfad | bellard | if ((addr & 1) == 0) { |
387 | 80cabfad | bellard | return 0xff; |
388 | 80cabfad | bellard | } else {
|
389 | 80cabfad | bellard | switch(s->cmos_index) {
|
390 | 80cabfad | bellard | case RTC_SECONDS:
|
391 | 80cabfad | bellard | case RTC_MINUTES:
|
392 | 80cabfad | bellard | case RTC_HOURS:
|
393 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
|
394 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
|
395 | 80cabfad | bellard | case RTC_MONTH:
|
396 | 80cabfad | bellard | case RTC_YEAR:
|
397 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
398 | 80cabfad | bellard | break;
|
399 | 80cabfad | bellard | case RTC_REG_A:
|
400 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
401 | 80cabfad | bellard | break;
|
402 | 80cabfad | bellard | case RTC_REG_C:
|
403 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
404 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
405 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
406 | 73822ec8 | aliguori | if(s->irq_coalesced) {
|
407 | 73822ec8 | aliguori | apic_reset_irq_delivered(); |
408 | 73822ec8 | aliguori | qemu_irq_raise(s->irq); |
409 | 73822ec8 | aliguori | if (apic_get_irq_delivered())
|
410 | 73822ec8 | aliguori | s->irq_coalesced--; |
411 | 73822ec8 | aliguori | break;
|
412 | 73822ec8 | aliguori | } |
413 | 73822ec8 | aliguori | #endif
|
414 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] = 0x00;
|
415 | 80cabfad | bellard | break;
|
416 | 80cabfad | bellard | default:
|
417 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
418 | 80cabfad | bellard | break;
|
419 | 80cabfad | bellard | } |
420 | 80cabfad | bellard | #ifdef DEBUG_CMOS
|
421 | 80cabfad | bellard | printf("cmos: read index=0x%02x val=0x%02x\n",
|
422 | 80cabfad | bellard | s->cmos_index, ret); |
423 | 80cabfad | bellard | #endif
|
424 | 80cabfad | bellard | return ret;
|
425 | 80cabfad | bellard | } |
426 | 80cabfad | bellard | } |
427 | 80cabfad | bellard | |
428 | dff38e7b | bellard | void rtc_set_memory(RTCState *s, int addr, int val) |
429 | dff38e7b | bellard | { |
430 | dff38e7b | bellard | if (addr >= 0 && addr <= 127) |
431 | dff38e7b | bellard | s->cmos_data[addr] = val; |
432 | dff38e7b | bellard | } |
433 | dff38e7b | bellard | |
434 | dff38e7b | bellard | void rtc_set_date(RTCState *s, const struct tm *tm) |
435 | dff38e7b | bellard | { |
436 | 43f493af | bellard | s->current_tm = *tm; |
437 | dff38e7b | bellard | rtc_copy_date(s); |
438 | dff38e7b | bellard | } |
439 | dff38e7b | bellard | |
440 | ea55ffb3 | ths | /* PC cmos mappings */
|
441 | ea55ffb3 | ths | #define REG_IBM_CENTURY_BYTE 0x32 |
442 | ea55ffb3 | ths | #define REG_IBM_PS2_CENTURY_BYTE 0x37 |
443 | ea55ffb3 | ths | |
444 | 9596ebb7 | pbrook | static void rtc_set_date_from_host(RTCState *s) |
445 | ea55ffb3 | ths | { |
446 | f6503059 | balrog | struct tm tm;
|
447 | ea55ffb3 | ths | int val;
|
448 | ea55ffb3 | ths | |
449 | ea55ffb3 | ths | /* set the CMOS date */
|
450 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
|
451 | f6503059 | balrog | rtc_set_date(s, &tm); |
452 | ea55ffb3 | ths | |
453 | f6503059 | balrog | val = to_bcd(s, (tm.tm_year / 100) + 19); |
454 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); |
455 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); |
456 | ea55ffb3 | ths | } |
457 | ea55ffb3 | ths | |
458 | dff38e7b | bellard | static void rtc_save(QEMUFile *f, void *opaque) |
459 | dff38e7b | bellard | { |
460 | dff38e7b | bellard | RTCState *s = opaque; |
461 | dff38e7b | bellard | |
462 | dff38e7b | bellard | qemu_put_buffer(f, s->cmos_data, 128);
|
463 | dff38e7b | bellard | qemu_put_8s(f, &s->cmos_index); |
464 | 3b46e624 | ths | |
465 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_sec); |
466 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_min); |
467 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_hour); |
468 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_wday); |
469 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_mday); |
470 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_mon); |
471 | bee8d684 | ths | qemu_put_be32(f, s->current_tm.tm_year); |
472 | dff38e7b | bellard | |
473 | dff38e7b | bellard | qemu_put_timer(f, s->periodic_timer); |
474 | bee8d684 | ths | qemu_put_be64(f, s->next_periodic_time); |
475 | dff38e7b | bellard | |
476 | bee8d684 | ths | qemu_put_be64(f, s->next_second_time); |
477 | dff38e7b | bellard | qemu_put_timer(f, s->second_timer); |
478 | dff38e7b | bellard | qemu_put_timer(f, s->second_timer2); |
479 | 80cabfad | bellard | } |
480 | 80cabfad | bellard | |
481 | dff38e7b | bellard | static int rtc_load(QEMUFile *f, void *opaque, int version_id) |
482 | 80cabfad | bellard | { |
483 | dff38e7b | bellard | RTCState *s = opaque; |
484 | dff38e7b | bellard | |
485 | dff38e7b | bellard | if (version_id != 1) |
486 | dff38e7b | bellard | return -EINVAL;
|
487 | 80cabfad | bellard | |
488 | dff38e7b | bellard | qemu_get_buffer(f, s->cmos_data, 128);
|
489 | dff38e7b | bellard | qemu_get_8s(f, &s->cmos_index); |
490 | 43f493af | bellard | |
491 | bee8d684 | ths | s->current_tm.tm_sec=qemu_get_be32(f); |
492 | bee8d684 | ths | s->current_tm.tm_min=qemu_get_be32(f); |
493 | bee8d684 | ths | s->current_tm.tm_hour=qemu_get_be32(f); |
494 | bee8d684 | ths | s->current_tm.tm_wday=qemu_get_be32(f); |
495 | bee8d684 | ths | s->current_tm.tm_mday=qemu_get_be32(f); |
496 | bee8d684 | ths | s->current_tm.tm_mon=qemu_get_be32(f); |
497 | bee8d684 | ths | s->current_tm.tm_year=qemu_get_be32(f); |
498 | dff38e7b | bellard | |
499 | dff38e7b | bellard | qemu_get_timer(f, s->periodic_timer); |
500 | bee8d684 | ths | s->next_periodic_time=qemu_get_be64(f); |
501 | dff38e7b | bellard | |
502 | bee8d684 | ths | s->next_second_time=qemu_get_be64(f); |
503 | dff38e7b | bellard | qemu_get_timer(f, s->second_timer); |
504 | dff38e7b | bellard | qemu_get_timer(f, s->second_timer2); |
505 | dff38e7b | bellard | return 0; |
506 | dff38e7b | bellard | } |
507 | dff38e7b | bellard | |
508 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
509 | 73822ec8 | aliguori | static void rtc_save_td(QEMUFile *f, void *opaque) |
510 | 73822ec8 | aliguori | { |
511 | 73822ec8 | aliguori | RTCState *s = opaque; |
512 | 73822ec8 | aliguori | |
513 | 73822ec8 | aliguori | qemu_put_be32(f, s->irq_coalesced); |
514 | 73822ec8 | aliguori | qemu_put_be32(f, s->period); |
515 | 73822ec8 | aliguori | } |
516 | 73822ec8 | aliguori | |
517 | 73822ec8 | aliguori | static int rtc_load_td(QEMUFile *f, void *opaque, int version_id) |
518 | 73822ec8 | aliguori | { |
519 | 73822ec8 | aliguori | RTCState *s = opaque; |
520 | 73822ec8 | aliguori | |
521 | 73822ec8 | aliguori | if (version_id != 1) |
522 | 73822ec8 | aliguori | return -EINVAL;
|
523 | 73822ec8 | aliguori | |
524 | 73822ec8 | aliguori | s->irq_coalesced = qemu_get_be32(f); |
525 | 73822ec8 | aliguori | s->period = qemu_get_be32(f); |
526 | 73822ec8 | aliguori | return 0; |
527 | 73822ec8 | aliguori | } |
528 | 73822ec8 | aliguori | #endif
|
529 | 73822ec8 | aliguori | |
530 | 42fc73a1 | aurel32 | RTCState *rtc_init(int base, qemu_irq irq, int base_year) |
531 | dff38e7b | bellard | { |
532 | dff38e7b | bellard | RTCState *s; |
533 | dff38e7b | bellard | |
534 | dff38e7b | bellard | s = qemu_mallocz(sizeof(RTCState));
|
535 | 80cabfad | bellard | |
536 | 80cabfad | bellard | s->irq = irq; |
537 | 80cabfad | bellard | s->cmos_data[RTC_REG_A] = 0x26;
|
538 | 80cabfad | bellard | s->cmos_data[RTC_REG_B] = 0x02;
|
539 | 80cabfad | bellard | s->cmos_data[RTC_REG_C] = 0x00;
|
540 | 80cabfad | bellard | s->cmos_data[RTC_REG_D] = 0x80;
|
541 | 80cabfad | bellard | |
542 | 42fc73a1 | aurel32 | s->base_year = base_year; |
543 | ea55ffb3 | ths | rtc_set_date_from_host(s); |
544 | ea55ffb3 | ths | |
545 | 5fafdf24 | ths | s->periodic_timer = qemu_new_timer(vm_clock, |
546 | dff38e7b | bellard | rtc_periodic_timer, s); |
547 | 5fafdf24 | ths | s->second_timer = qemu_new_timer(vm_clock, |
548 | dff38e7b | bellard | rtc_update_second, s); |
549 | 5fafdf24 | ths | s->second_timer2 = qemu_new_timer(vm_clock, |
550 | dff38e7b | bellard | rtc_update_second2, s); |
551 | dff38e7b | bellard | |
552 | dff38e7b | bellard | s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; |
553 | dff38e7b | bellard | qemu_mod_timer(s->second_timer2, s->next_second_time); |
554 | dff38e7b | bellard | |
555 | b41a2cd1 | bellard | register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
556 | b41a2cd1 | bellard | register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
557 | dff38e7b | bellard | |
558 | dff38e7b | bellard | register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); |
559 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
560 | 73822ec8 | aliguori | if (rtc_td_hack)
|
561 | 73822ec8 | aliguori | register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s); |
562 | 73822ec8 | aliguori | #endif
|
563 | dff38e7b | bellard | return s;
|
564 | 80cabfad | bellard | } |
565 | 80cabfad | bellard | |
566 | 2ca9d013 | ths | /* Memory mapped interface */
|
567 | 9596ebb7 | pbrook | static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr) |
568 | 2ca9d013 | ths | { |
569 | 2ca9d013 | ths | RTCState *s = opaque; |
570 | 2ca9d013 | ths | |
571 | 8da3ff18 | pbrook | return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF; |
572 | 2ca9d013 | ths | } |
573 | 2ca9d013 | ths | |
574 | 9596ebb7 | pbrook | static void cmos_mm_writeb (void *opaque, |
575 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
576 | 2ca9d013 | ths | { |
577 | 2ca9d013 | ths | RTCState *s = opaque; |
578 | 2ca9d013 | ths | |
579 | 8da3ff18 | pbrook | cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
|
580 | 2ca9d013 | ths | } |
581 | 2ca9d013 | ths | |
582 | 9596ebb7 | pbrook | static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr) |
583 | 2ca9d013 | ths | { |
584 | 2ca9d013 | ths | RTCState *s = opaque; |
585 | 18c6e2ff | ths | uint32_t val; |
586 | 2ca9d013 | ths | |
587 | 8da3ff18 | pbrook | val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
|
588 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
589 | 18c6e2ff | ths | val = bswap16(val); |
590 | 18c6e2ff | ths | #endif
|
591 | 18c6e2ff | ths | return val;
|
592 | 2ca9d013 | ths | } |
593 | 2ca9d013 | ths | |
594 | 9596ebb7 | pbrook | static void cmos_mm_writew (void *opaque, |
595 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
596 | 2ca9d013 | ths | { |
597 | 2ca9d013 | ths | RTCState *s = opaque; |
598 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
599 | 18c6e2ff | ths | value = bswap16(value); |
600 | 18c6e2ff | ths | #endif
|
601 | 8da3ff18 | pbrook | cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
|
602 | 2ca9d013 | ths | } |
603 | 2ca9d013 | ths | |
604 | 9596ebb7 | pbrook | static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr) |
605 | 2ca9d013 | ths | { |
606 | 2ca9d013 | ths | RTCState *s = opaque; |
607 | 18c6e2ff | ths | uint32_t val; |
608 | 2ca9d013 | ths | |
609 | 8da3ff18 | pbrook | val = cmos_ioport_read(s, addr >> s->it_shift); |
610 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
611 | 18c6e2ff | ths | val = bswap32(val); |
612 | 18c6e2ff | ths | #endif
|
613 | 18c6e2ff | ths | return val;
|
614 | 2ca9d013 | ths | } |
615 | 2ca9d013 | ths | |
616 | 9596ebb7 | pbrook | static void cmos_mm_writel (void *opaque, |
617 | 9596ebb7 | pbrook | target_phys_addr_t addr, uint32_t value) |
618 | 2ca9d013 | ths | { |
619 | 2ca9d013 | ths | RTCState *s = opaque; |
620 | 18c6e2ff | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
621 | 18c6e2ff | ths | value = bswap32(value); |
622 | 18c6e2ff | ths | #endif
|
623 | 8da3ff18 | pbrook | cmos_ioport_write(s, addr >> s->it_shift, value); |
624 | 2ca9d013 | ths | } |
625 | 2ca9d013 | ths | |
626 | 2ca9d013 | ths | static CPUReadMemoryFunc *rtc_mm_read[] = {
|
627 | 2ca9d013 | ths | &cmos_mm_readb, |
628 | 2ca9d013 | ths | &cmos_mm_readw, |
629 | 2ca9d013 | ths | &cmos_mm_readl, |
630 | 2ca9d013 | ths | }; |
631 | 2ca9d013 | ths | |
632 | 2ca9d013 | ths | static CPUWriteMemoryFunc *rtc_mm_write[] = {
|
633 | 2ca9d013 | ths | &cmos_mm_writeb, |
634 | 2ca9d013 | ths | &cmos_mm_writew, |
635 | 2ca9d013 | ths | &cmos_mm_writel, |
636 | 2ca9d013 | ths | }; |
637 | 2ca9d013 | ths | |
638 | 42fc73a1 | aurel32 | RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
|
639 | 42fc73a1 | aurel32 | int base_year)
|
640 | 2ca9d013 | ths | { |
641 | 2ca9d013 | ths | RTCState *s; |
642 | 2ca9d013 | ths | int io_memory;
|
643 | 2ca9d013 | ths | |
644 | 2ca9d013 | ths | s = qemu_mallocz(sizeof(RTCState));
|
645 | 2ca9d013 | ths | |
646 | 2ca9d013 | ths | s->irq = irq; |
647 | 2ca9d013 | ths | s->cmos_data[RTC_REG_A] = 0x26;
|
648 | 2ca9d013 | ths | s->cmos_data[RTC_REG_B] = 0x02;
|
649 | 2ca9d013 | ths | s->cmos_data[RTC_REG_C] = 0x00;
|
650 | 2ca9d013 | ths | s->cmos_data[RTC_REG_D] = 0x80;
|
651 | 2ca9d013 | ths | |
652 | 42fc73a1 | aurel32 | s->base_year = base_year; |
653 | 2ca9d013 | ths | rtc_set_date_from_host(s); |
654 | 2ca9d013 | ths | |
655 | 2ca9d013 | ths | s->periodic_timer = qemu_new_timer(vm_clock, |
656 | 2ca9d013 | ths | rtc_periodic_timer, s); |
657 | 2ca9d013 | ths | s->second_timer = qemu_new_timer(vm_clock, |
658 | 2ca9d013 | ths | rtc_update_second, s); |
659 | 2ca9d013 | ths | s->second_timer2 = qemu_new_timer(vm_clock, |
660 | 2ca9d013 | ths | rtc_update_second2, s); |
661 | 2ca9d013 | ths | |
662 | 2ca9d013 | ths | s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; |
663 | 2ca9d013 | ths | qemu_mod_timer(s->second_timer2, s->next_second_time); |
664 | 2ca9d013 | ths | |
665 | 2ca9d013 | ths | io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
|
666 | 18c6e2ff | ths | cpu_register_physical_memory(base, 2 << it_shift, io_memory);
|
667 | 2ca9d013 | ths | |
668 | 2ca9d013 | ths | register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); |
669 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
670 | 73822ec8 | aliguori | if (rtc_td_hack)
|
671 | 73822ec8 | aliguori | register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s); |
672 | 73822ec8 | aliguori | #endif
|
673 | 2ca9d013 | ths | return s;
|
674 | 2ca9d013 | ths | } |