root / hw / mips_mipssim.c @ b8c18e4c
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1 | f0fc6f8f | ths | /*
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2 | f0fc6f8f | ths | * QEMU/mipssim emulation
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3 | f0fc6f8f | ths | *
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4 | f0fc6f8f | ths | * Emulates a very simple machine model similiar to the one use by the
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5 | f0fc6f8f | ths | * proprietary MIPS emulator.
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6 | a79ee211 | ths | *
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7 | a79ee211 | ths | * Copyright (c) 2007 Thiemo Seufer
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8 | a79ee211 | ths | *
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9 | a79ee211 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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10 | a79ee211 | ths | * of this software and associated documentation files (the "Software"), to deal
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11 | a79ee211 | ths | * in the Software without restriction, including without limitation the rights
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12 | a79ee211 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 | a79ee211 | ths | * copies of the Software, and to permit persons to whom the Software is
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14 | a79ee211 | ths | * furnished to do so, subject to the following conditions:
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15 | a79ee211 | ths | *
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16 | a79ee211 | ths | * The above copyright notice and this permission notice shall be included in
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17 | a79ee211 | ths | * all copies or substantial portions of the Software.
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18 | a79ee211 | ths | *
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19 | a79ee211 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 | a79ee211 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 | a79ee211 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 | a79ee211 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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23 | a79ee211 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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24 | a79ee211 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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25 | a79ee211 | ths | * THE SOFTWARE.
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26 | f0fc6f8f | ths | */
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27 | 87ecb68b | pbrook | #include "hw.h" |
28 | 87ecb68b | pbrook | #include "mips.h" |
29 | 87ecb68b | pbrook | #include "pc.h" |
30 | 87ecb68b | pbrook | #include "isa.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "sysemu.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | f0fc6f8f | ths | |
35 | f0fc6f8f | ths | #ifdef TARGET_WORDS_BIGENDIAN
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36 | f0fc6f8f | ths | #define BIOS_FILENAME "mips_bios.bin" |
37 | f0fc6f8f | ths | #else
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38 | f0fc6f8f | ths | #define BIOS_FILENAME "mipsel_bios.bin" |
39 | f0fc6f8f | ths | #endif
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40 | f0fc6f8f | ths | |
41 | f0fc6f8f | ths | #ifdef TARGET_MIPS64
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42 | f0fc6f8f | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL) |
43 | f0fc6f8f | ths | #else
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44 | f0fc6f8f | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU) |
45 | f0fc6f8f | ths | #endif
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46 | f0fc6f8f | ths | |
47 | f0fc6f8f | ths | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
48 | f0fc6f8f | ths | |
49 | 7df526e3 | ths | static struct _loaderparams { |
50 | 7df526e3 | ths | int ram_size;
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51 | 7df526e3 | ths | const char *kernel_filename; |
52 | 7df526e3 | ths | const char *kernel_cmdline; |
53 | 7df526e3 | ths | const char *initrd_filename; |
54 | 7df526e3 | ths | } loaderparams; |
55 | 7df526e3 | ths | |
56 | f0fc6f8f | ths | static void load_kernel (CPUState *env) |
57 | f0fc6f8f | ths | { |
58 | f0fc6f8f | ths | int64_t entry, kernel_low, kernel_high; |
59 | f0fc6f8f | ths | long kernel_size;
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60 | f0fc6f8f | ths | long initrd_size;
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61 | f0fc6f8f | ths | ram_addr_t initrd_offset; |
62 | f0fc6f8f | ths | |
63 | 7df526e3 | ths | kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, |
64 | b55266b5 | blueswir1 | (uint64_t *)&entry, (uint64_t *)&kernel_low, |
65 | b55266b5 | blueswir1 | (uint64_t *)&kernel_high); |
66 | f0fc6f8f | ths | if (kernel_size >= 0) { |
67 | f0fc6f8f | ths | if ((entry & ~0x7fffffffULL) == 0x80000000) |
68 | f0fc6f8f | ths | entry = (int32_t)entry; |
69 | b5dc7732 | ths | env->active_tc.PC = entry; |
70 | f0fc6f8f | ths | } else {
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71 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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72 | 7df526e3 | ths | loaderparams.kernel_filename); |
73 | f0fc6f8f | ths | exit(1);
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74 | f0fc6f8f | ths | } |
75 | f0fc6f8f | ths | |
76 | f0fc6f8f | ths | /* load initrd */
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77 | f0fc6f8f | ths | initrd_size = 0;
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78 | f0fc6f8f | ths | initrd_offset = 0;
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79 | 7df526e3 | ths | if (loaderparams.initrd_filename) {
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80 | 7df526e3 | ths | initrd_size = get_image_size (loaderparams.initrd_filename); |
81 | f0fc6f8f | ths | if (initrd_size > 0) { |
82 | f0fc6f8f | ths | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
83 | 7df526e3 | ths | if (initrd_offset + initrd_size > loaderparams.ram_size) {
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84 | f0fc6f8f | ths | fprintf(stderr, |
85 | f0fc6f8f | ths | "qemu: memory too small for initial ram disk '%s'\n",
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86 | 7df526e3 | ths | loaderparams.initrd_filename); |
87 | f0fc6f8f | ths | exit(1);
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88 | f0fc6f8f | ths | } |
89 | 7df526e3 | ths | initrd_size = load_image(loaderparams.initrd_filename, |
90 | f0fc6f8f | ths | phys_ram_base + initrd_offset); |
91 | f0fc6f8f | ths | } |
92 | f0fc6f8f | ths | if (initrd_size == (target_ulong) -1) { |
93 | f0fc6f8f | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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94 | 7df526e3 | ths | loaderparams.initrd_filename); |
95 | f0fc6f8f | ths | exit(1);
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96 | f0fc6f8f | ths | } |
97 | f0fc6f8f | ths | } |
98 | f0fc6f8f | ths | } |
99 | f0fc6f8f | ths | |
100 | f0fc6f8f | ths | static void main_cpu_reset(void *opaque) |
101 | f0fc6f8f | ths | { |
102 | f0fc6f8f | ths | CPUState *env = opaque; |
103 | f0fc6f8f | ths | cpu_reset(env); |
104 | f0fc6f8f | ths | |
105 | 7df526e3 | ths | if (loaderparams.kernel_filename)
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106 | f0fc6f8f | ths | load_kernel (env); |
107 | f0fc6f8f | ths | } |
108 | f0fc6f8f | ths | |
109 | f0fc6f8f | ths | static void |
110 | 00f82b8a | aurel32 | mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size,
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111 | 3023f332 | aliguori | const char *boot_device, |
112 | f0fc6f8f | ths | const char *kernel_filename, const char *kernel_cmdline, |
113 | f0fc6f8f | ths | const char *initrd_filename, const char *cpu_model) |
114 | f0fc6f8f | ths | { |
115 | f0fc6f8f | ths | char buf[1024]; |
116 | f0fc6f8f | ths | unsigned long bios_offset; |
117 | f0fc6f8f | ths | CPUState *env; |
118 | b5334159 | ths | int bios_size;
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119 | f0fc6f8f | ths | |
120 | f0fc6f8f | ths | /* Init CPUs. */
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121 | f0fc6f8f | ths | if (cpu_model == NULL) { |
122 | f0fc6f8f | ths | #ifdef TARGET_MIPS64
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123 | f0fc6f8f | ths | cpu_model = "5Kf";
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124 | f0fc6f8f | ths | #else
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125 | f0fc6f8f | ths | cpu_model = "24Kf";
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126 | f0fc6f8f | ths | #endif
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127 | f0fc6f8f | ths | } |
128 | aaed909a | bellard | env = cpu_init(cpu_model); |
129 | aaed909a | bellard | if (!env) {
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130 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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131 | aaed909a | bellard | exit(1);
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132 | aaed909a | bellard | } |
133 | f0fc6f8f | ths | qemu_register_reset(main_cpu_reset, env); |
134 | f0fc6f8f | ths | |
135 | f0fc6f8f | ths | /* Allocate RAM. */
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136 | f0fc6f8f | ths | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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137 | f0fc6f8f | ths | |
138 | f0fc6f8f | ths | /* Load a BIOS / boot exception handler image. */
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139 | b5334159 | ths | bios_offset = ram_size + vga_ram_size; |
140 | f0fc6f8f | ths | if (bios_name == NULL) |
141 | f0fc6f8f | ths | bios_name = BIOS_FILENAME; |
142 | f0fc6f8f | ths | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
143 | b5334159 | ths | bios_size = load_image(buf, phys_ram_base + bios_offset); |
144 | b5334159 | ths | if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) { |
145 | f0fc6f8f | ths | /* Bail out if we have neither a kernel image nor boot vector code. */
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146 | f0fc6f8f | ths | fprintf(stderr, |
147 | f0fc6f8f | ths | "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
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148 | f0fc6f8f | ths | buf); |
149 | f0fc6f8f | ths | exit(1);
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150 | f0fc6f8f | ths | } else {
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151 | b5334159 | ths | /* Map the BIOS / boot exception handler. */
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152 | f0fc6f8f | ths | cpu_register_physical_memory(0x1fc00000LL,
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153 | b5334159 | ths | bios_size, bios_offset | IO_MEM_ROM); |
154 | b5334159 | ths | /* We have a boot vector start address. */
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155 | b5dc7732 | ths | env->active_tc.PC = (target_long)(int32_t)0xbfc00000;
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156 | f0fc6f8f | ths | } |
157 | f0fc6f8f | ths | |
158 | f0fc6f8f | ths | if (kernel_filename) {
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159 | 7df526e3 | ths | loaderparams.ram_size = ram_size; |
160 | 7df526e3 | ths | loaderparams.kernel_filename = kernel_filename; |
161 | 7df526e3 | ths | loaderparams.kernel_cmdline = kernel_cmdline; |
162 | 7df526e3 | ths | loaderparams.initrd_filename = initrd_filename; |
163 | f0fc6f8f | ths | load_kernel(env); |
164 | f0fc6f8f | ths | } |
165 | f0fc6f8f | ths | |
166 | f0fc6f8f | ths | /* Init CPU internal devices. */
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167 | f0fc6f8f | ths | cpu_mips_irq_init_cpu(env); |
168 | f0fc6f8f | ths | cpu_mips_clock_init(env); |
169 | f0fc6f8f | ths | |
170 | f0fc6f8f | ths | /* Register 64 KB of ISA IO space at 0x1fd00000. */
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171 | f0fc6f8f | ths | isa_mmio_init(0x1fd00000, 0x00010000); |
172 | f0fc6f8f | ths | |
173 | f0fc6f8f | ths | /* A single 16450 sits at offset 0x3f8. It is attached to
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174 | f0fc6f8f | ths | MIPS CPU INT2, which is interrupt 4. */
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175 | f0fc6f8f | ths | if (serial_hds[0]) |
176 | b6cd0ea1 | aurel32 | serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]); |
177 | f0fc6f8f | ths | |
178 | 0ae18cee | aliguori | if (nd_table[0].vlan) |
179 | 0ae18cee | aliguori | /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
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180 | 0ae18cee | aliguori | mipsnet_init(0x4200, env->irq[2], &nd_table[0]); |
181 | f0fc6f8f | ths | } |
182 | f0fc6f8f | ths | |
183 | f0fc6f8f | ths | QEMUMachine mips_mipssim_machine = { |
184 | eec2743e | ths | .name = "mipssim",
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185 | eec2743e | ths | .desc = "MIPS MIPSsim platform",
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186 | eec2743e | ths | .init = mips_mipssim_init, |
187 | eec2743e | ths | .ram_require = BIOS_SIZE + VGA_RAM_SIZE /* unused */,
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188 | eec2743e | ths | .nodisk_ok = 1,
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189 | f0fc6f8f | ths | }; |