root / hw / pxa2xx_mmci.c @ b8c18e4c
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1 | a171fe39 | balrog | /*
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2 | a171fe39 | balrog | * Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
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3 | a171fe39 | balrog | *
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4 | a171fe39 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | a171fe39 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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6 | a171fe39 | balrog | *
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7 | a171fe39 | balrog | * This code is licensed under the GPLv2.
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8 | a171fe39 | balrog | */
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9 | a171fe39 | balrog | |
10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "pxa.h" |
12 | a171fe39 | balrog | #include "sd.h" |
13 | a171fe39 | balrog | |
14 | a171fe39 | balrog | struct pxa2xx_mmci_s {
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15 | a171fe39 | balrog | qemu_irq irq; |
16 | a171fe39 | balrog | void *dma;
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17 | a171fe39 | balrog | |
18 | a171fe39 | balrog | SDState *card; |
19 | a171fe39 | balrog | |
20 | a171fe39 | balrog | uint32_t status; |
21 | a171fe39 | balrog | uint32_t clkrt; |
22 | a171fe39 | balrog | uint32_t spi; |
23 | a171fe39 | balrog | uint32_t cmdat; |
24 | a171fe39 | balrog | uint32_t resp_tout; |
25 | a171fe39 | balrog | uint32_t read_tout; |
26 | a171fe39 | balrog | int blklen;
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27 | a171fe39 | balrog | int numblk;
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28 | a171fe39 | balrog | uint32_t intmask; |
29 | a171fe39 | balrog | uint32_t intreq; |
30 | a171fe39 | balrog | int cmd;
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31 | a171fe39 | balrog | uint32_t arg; |
32 | a171fe39 | balrog | |
33 | a171fe39 | balrog | int active;
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34 | a171fe39 | balrog | int bytesleft;
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35 | a171fe39 | balrog | uint8_t tx_fifo[64];
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36 | a171fe39 | balrog | int tx_start;
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37 | a171fe39 | balrog | int tx_len;
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38 | a171fe39 | balrog | uint8_t rx_fifo[32];
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39 | a171fe39 | balrog | int rx_start;
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40 | a171fe39 | balrog | int rx_len;
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41 | a171fe39 | balrog | uint16_t resp_fifo[9];
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42 | a171fe39 | balrog | int resp_len;
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43 | a171fe39 | balrog | |
44 | a171fe39 | balrog | int cmdreq;
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45 | a171fe39 | balrog | int ac_width;
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46 | a171fe39 | balrog | }; |
47 | a171fe39 | balrog | |
48 | a171fe39 | balrog | #define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */ |
49 | a171fe39 | balrog | #define MMC_STAT 0x04 /* MMC Status register */ |
50 | a171fe39 | balrog | #define MMC_CLKRT 0x08 /* MMC Clock Rate register */ |
51 | a171fe39 | balrog | #define MMC_SPI 0x0c /* MMC SPI Mode register */ |
52 | a171fe39 | balrog | #define MMC_CMDAT 0x10 /* MMC Command/Data register */ |
53 | a171fe39 | balrog | #define MMC_RESTO 0x14 /* MMC Response Time-Out register */ |
54 | a171fe39 | balrog | #define MMC_RDTO 0x18 /* MMC Read Time-Out register */ |
55 | a171fe39 | balrog | #define MMC_BLKLEN 0x1c /* MMC Block Length register */ |
56 | a171fe39 | balrog | #define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */ |
57 | a171fe39 | balrog | #define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */ |
58 | a171fe39 | balrog | #define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */ |
59 | a171fe39 | balrog | #define MMC_I_REG 0x2c /* MMC Interrupt Request register */ |
60 | a171fe39 | balrog | #define MMC_CMD 0x30 /* MMC Command register */ |
61 | a171fe39 | balrog | #define MMC_ARGH 0x34 /* MMC Argument High register */ |
62 | a171fe39 | balrog | #define MMC_ARGL 0x38 /* MMC Argument Low register */ |
63 | a171fe39 | balrog | #define MMC_RES 0x3c /* MMC Response FIFO */ |
64 | a171fe39 | balrog | #define MMC_RXFIFO 0x40 /* MMC Receive FIFO */ |
65 | a171fe39 | balrog | #define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */ |
66 | a171fe39 | balrog | #define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */ |
67 | a171fe39 | balrog | #define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */ |
68 | a171fe39 | balrog | |
69 | a171fe39 | balrog | /* Bitfield masks */
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70 | a171fe39 | balrog | #define STRPCL_STOP_CLK (1 << 0) |
71 | a171fe39 | balrog | #define STRPCL_STRT_CLK (1 << 1) |
72 | a171fe39 | balrog | #define STAT_TOUT_RES (1 << 1) |
73 | a171fe39 | balrog | #define STAT_CLK_EN (1 << 8) |
74 | a171fe39 | balrog | #define STAT_DATA_DONE (1 << 11) |
75 | a171fe39 | balrog | #define STAT_PRG_DONE (1 << 12) |
76 | a171fe39 | balrog | #define STAT_END_CMDRES (1 << 13) |
77 | a171fe39 | balrog | #define SPI_SPI_MODE (1 << 0) |
78 | a171fe39 | balrog | #define CMDAT_RES_TYPE (3 << 0) |
79 | a171fe39 | balrog | #define CMDAT_DATA_EN (1 << 2) |
80 | a171fe39 | balrog | #define CMDAT_WR_RD (1 << 3) |
81 | a171fe39 | balrog | #define CMDAT_DMA_EN (1 << 7) |
82 | a171fe39 | balrog | #define CMDAT_STOP_TRAN (1 << 10) |
83 | a171fe39 | balrog | #define INT_DATA_DONE (1 << 0) |
84 | a171fe39 | balrog | #define INT_PRG_DONE (1 << 1) |
85 | a171fe39 | balrog | #define INT_END_CMD (1 << 2) |
86 | a171fe39 | balrog | #define INT_STOP_CMD (1 << 3) |
87 | a171fe39 | balrog | #define INT_CLK_OFF (1 << 4) |
88 | a171fe39 | balrog | #define INT_RXFIFO_REQ (1 << 5) |
89 | a171fe39 | balrog | #define INT_TXFIFO_REQ (1 << 6) |
90 | a171fe39 | balrog | #define INT_TINT (1 << 7) |
91 | a171fe39 | balrog | #define INT_DAT_ERR (1 << 8) |
92 | a171fe39 | balrog | #define INT_RES_ERR (1 << 9) |
93 | a171fe39 | balrog | #define INT_RD_STALLED (1 << 10) |
94 | a171fe39 | balrog | #define INT_SDIO_INT (1 << 11) |
95 | a171fe39 | balrog | #define INT_SDIO_SACK (1 << 12) |
96 | a171fe39 | balrog | #define PRTBUF_PRT_BUF (1 << 0) |
97 | a171fe39 | balrog | |
98 | a171fe39 | balrog | /* Route internal interrupt lines to the global IC and DMA */
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99 | a171fe39 | balrog | static void pxa2xx_mmci_int_update(struct pxa2xx_mmci_s *s) |
100 | a171fe39 | balrog | { |
101 | a171fe39 | balrog | uint32_t mask = s->intmask; |
102 | a171fe39 | balrog | if (s->cmdat & CMDAT_DMA_EN) {
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103 | a171fe39 | balrog | mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ; |
104 | a171fe39 | balrog | |
105 | a171fe39 | balrog | pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma,
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106 | a171fe39 | balrog | PXA2XX_RX_RQ_MMCI, !!(s->intreq & INT_RXFIFO_REQ)); |
107 | a171fe39 | balrog | pxa2xx_dma_request((struct pxa2xx_dma_state_s *) s->dma,
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108 | a171fe39 | balrog | PXA2XX_TX_RQ_MMCI, !!(s->intreq & INT_TXFIFO_REQ)); |
109 | a171fe39 | balrog | } |
110 | a171fe39 | balrog | |
111 | a171fe39 | balrog | qemu_set_irq(s->irq, !!(s->intreq & ~mask)); |
112 | a171fe39 | balrog | } |
113 | a171fe39 | balrog | |
114 | a171fe39 | balrog | static void pxa2xx_mmci_fifo_update(struct pxa2xx_mmci_s *s) |
115 | a171fe39 | balrog | { |
116 | a171fe39 | balrog | if (!s->active)
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117 | a171fe39 | balrog | return;
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118 | a171fe39 | balrog | |
119 | a171fe39 | balrog | if (s->cmdat & CMDAT_WR_RD) {
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120 | a171fe39 | balrog | while (s->bytesleft && s->tx_len) {
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121 | a171fe39 | balrog | sd_write_data(s->card, s->tx_fifo[s->tx_start ++]); |
122 | a171fe39 | balrog | s->tx_start &= 0x1f;
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123 | a171fe39 | balrog | s->tx_len --; |
124 | a171fe39 | balrog | s->bytesleft --; |
125 | a171fe39 | balrog | } |
126 | a171fe39 | balrog | if (s->bytesleft)
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127 | a171fe39 | balrog | s->intreq |= INT_TXFIFO_REQ; |
128 | a171fe39 | balrog | } else
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129 | a171fe39 | balrog | while (s->bytesleft && s->rx_len < 32) { |
130 | a171fe39 | balrog | s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
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131 | a171fe39 | balrog | sd_read_data(s->card); |
132 | a171fe39 | balrog | s->bytesleft --; |
133 | a171fe39 | balrog | s->intreq |= INT_RXFIFO_REQ; |
134 | a171fe39 | balrog | } |
135 | a171fe39 | balrog | |
136 | a171fe39 | balrog | if (!s->bytesleft) {
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137 | a171fe39 | balrog | s->active = 0;
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138 | a171fe39 | balrog | s->intreq |= INT_DATA_DONE; |
139 | a171fe39 | balrog | s->status |= STAT_DATA_DONE; |
140 | a171fe39 | balrog | |
141 | a171fe39 | balrog | if (s->cmdat & CMDAT_WR_RD) {
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142 | a171fe39 | balrog | s->intreq |= INT_PRG_DONE; |
143 | a171fe39 | balrog | s->status |= STAT_PRG_DONE; |
144 | a171fe39 | balrog | } |
145 | a171fe39 | balrog | } |
146 | a171fe39 | balrog | |
147 | a171fe39 | balrog | pxa2xx_mmci_int_update(s); |
148 | a171fe39 | balrog | } |
149 | a171fe39 | balrog | |
150 | a171fe39 | balrog | static void pxa2xx_mmci_wakequeues(struct pxa2xx_mmci_s *s) |
151 | a171fe39 | balrog | { |
152 | a171fe39 | balrog | int rsplen, i;
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153 | a171fe39 | balrog | struct sd_request_s request;
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154 | a171fe39 | balrog | uint8_t response[16];
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155 | a171fe39 | balrog | |
156 | a171fe39 | balrog | s->active = 1;
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157 | a171fe39 | balrog | s->rx_len = 0;
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158 | a171fe39 | balrog | s->tx_len = 0;
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159 | a171fe39 | balrog | s->cmdreq = 0;
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160 | a171fe39 | balrog | |
161 | a171fe39 | balrog | request.cmd = s->cmd; |
162 | a171fe39 | balrog | request.arg = s->arg; |
163 | a171fe39 | balrog | request.crc = 0; /* FIXME */ |
164 | a171fe39 | balrog | |
165 | a171fe39 | balrog | rsplen = sd_do_command(s->card, &request, response); |
166 | a171fe39 | balrog | s->intreq |= INT_END_CMD; |
167 | a171fe39 | balrog | |
168 | a171fe39 | balrog | memset(s->resp_fifo, 0, sizeof(s->resp_fifo)); |
169 | a171fe39 | balrog | switch (s->cmdat & CMDAT_RES_TYPE) {
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170 | a171fe39 | balrog | #define PXAMMCI_RESP(wd, value0, value1) \
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171 | a171fe39 | balrog | s->resp_fifo[(wd) + 0] |= (value0); \
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172 | a171fe39 | balrog | s->resp_fifo[(wd) + 1] |= (value1) << 8; |
173 | a171fe39 | balrog | case 0: /* No response */ |
174 | a171fe39 | balrog | goto complete;
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175 | a171fe39 | balrog | |
176 | a171fe39 | balrog | case 1: /* R1, R4, R5 or R6 */ |
177 | a171fe39 | balrog | if (rsplen < 4) |
178 | a171fe39 | balrog | goto timeout;
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179 | a171fe39 | balrog | goto complete;
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180 | a171fe39 | balrog | |
181 | a171fe39 | balrog | case 2: /* R2 */ |
182 | a171fe39 | balrog | if (rsplen < 16) |
183 | a171fe39 | balrog | goto timeout;
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184 | a171fe39 | balrog | goto complete;
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185 | a171fe39 | balrog | |
186 | a171fe39 | balrog | case 3: /* R3 */ |
187 | a171fe39 | balrog | if (rsplen < 4) |
188 | a171fe39 | balrog | goto timeout;
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189 | a171fe39 | balrog | goto complete;
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190 | a171fe39 | balrog | |
191 | a171fe39 | balrog | complete:
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192 | a171fe39 | balrog | for (i = 0; rsplen > 0; i ++, rsplen -= 2) { |
193 | a171fe39 | balrog | PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]); |
194 | a171fe39 | balrog | } |
195 | a171fe39 | balrog | s->status |= STAT_END_CMDRES; |
196 | a171fe39 | balrog | |
197 | a171fe39 | balrog | if (!(s->cmdat & CMDAT_DATA_EN))
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198 | a171fe39 | balrog | s->active = 0;
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199 | a171fe39 | balrog | else
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200 | a171fe39 | balrog | s->bytesleft = s->numblk * s->blklen; |
201 | a171fe39 | balrog | |
202 | a171fe39 | balrog | s->resp_len = 0;
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203 | a171fe39 | balrog | break;
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204 | a171fe39 | balrog | |
205 | a171fe39 | balrog | timeout:
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206 | a171fe39 | balrog | s->active = 0;
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207 | a171fe39 | balrog | s->status |= STAT_TOUT_RES; |
208 | a171fe39 | balrog | break;
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209 | a171fe39 | balrog | } |
210 | a171fe39 | balrog | |
211 | a171fe39 | balrog | pxa2xx_mmci_fifo_update(s); |
212 | a171fe39 | balrog | } |
213 | a171fe39 | balrog | |
214 | a171fe39 | balrog | static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset) |
215 | a171fe39 | balrog | { |
216 | a171fe39 | balrog | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
217 | a171fe39 | balrog | uint32_t ret; |
218 | a171fe39 | balrog | |
219 | a171fe39 | balrog | switch (offset) {
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220 | a171fe39 | balrog | case MMC_STRPCL:
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221 | a171fe39 | balrog | return 0; |
222 | a171fe39 | balrog | case MMC_STAT:
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223 | a171fe39 | balrog | return s->status;
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224 | a171fe39 | balrog | case MMC_CLKRT:
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225 | a171fe39 | balrog | return s->clkrt;
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226 | a171fe39 | balrog | case MMC_SPI:
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227 | a171fe39 | balrog | return s->spi;
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228 | a171fe39 | balrog | case MMC_CMDAT:
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229 | a171fe39 | balrog | return s->cmdat;
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230 | a171fe39 | balrog | case MMC_RESTO:
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231 | a171fe39 | balrog | return s->resp_tout;
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232 | a171fe39 | balrog | case MMC_RDTO:
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233 | a171fe39 | balrog | return s->read_tout;
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234 | a171fe39 | balrog | case MMC_BLKLEN:
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235 | a171fe39 | balrog | return s->blklen;
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236 | a171fe39 | balrog | case MMC_NUMBLK:
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237 | a171fe39 | balrog | return s->numblk;
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238 | a171fe39 | balrog | case MMC_PRTBUF:
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239 | a171fe39 | balrog | return 0; |
240 | a171fe39 | balrog | case MMC_I_MASK:
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241 | a171fe39 | balrog | return s->intmask;
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242 | a171fe39 | balrog | case MMC_I_REG:
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243 | a171fe39 | balrog | return s->intreq;
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244 | a171fe39 | balrog | case MMC_CMD:
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245 | a171fe39 | balrog | return s->cmd | 0x40; |
246 | a171fe39 | balrog | case MMC_ARGH:
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247 | a171fe39 | balrog | return s->arg >> 16; |
248 | a171fe39 | balrog | case MMC_ARGL:
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249 | a171fe39 | balrog | return s->arg & 0xffff; |
250 | a171fe39 | balrog | case MMC_RES:
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251 | a171fe39 | balrog | if (s->resp_len < 9) |
252 | a171fe39 | balrog | return s->resp_fifo[s->resp_len ++];
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253 | a171fe39 | balrog | return 0; |
254 | a171fe39 | balrog | case MMC_RXFIFO:
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255 | a171fe39 | balrog | ret = 0;
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256 | a171fe39 | balrog | while (s->ac_width -- && s->rx_len) {
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257 | a171fe39 | balrog | ret |= s->rx_fifo[s->rx_start ++] << (s->ac_width << 3);
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258 | a171fe39 | balrog | s->rx_start &= 0x1f;
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259 | a171fe39 | balrog | s->rx_len --; |
260 | a171fe39 | balrog | } |
261 | a171fe39 | balrog | s->intreq &= ~INT_RXFIFO_REQ; |
262 | a171fe39 | balrog | pxa2xx_mmci_fifo_update(s); |
263 | a171fe39 | balrog | return ret;
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264 | a171fe39 | balrog | case MMC_RDWAIT:
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265 | a171fe39 | balrog | return 0; |
266 | a171fe39 | balrog | case MMC_BLKS_REM:
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267 | a171fe39 | balrog | return s->numblk;
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268 | a171fe39 | balrog | default:
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269 | a171fe39 | balrog | cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n", |
270 | a171fe39 | balrog | __FUNCTION__, offset); |
271 | a171fe39 | balrog | } |
272 | a171fe39 | balrog | |
273 | a171fe39 | balrog | return 0; |
274 | a171fe39 | balrog | } |
275 | a171fe39 | balrog | |
276 | a171fe39 | balrog | static void pxa2xx_mmci_write(void *opaque, |
277 | a171fe39 | balrog | target_phys_addr_t offset, uint32_t value) |
278 | a171fe39 | balrog | { |
279 | a171fe39 | balrog | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
280 | a171fe39 | balrog | |
281 | a171fe39 | balrog | switch (offset) {
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282 | a171fe39 | balrog | case MMC_STRPCL:
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283 | a171fe39 | balrog | if (value & STRPCL_STRT_CLK) {
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284 | a171fe39 | balrog | s->status |= STAT_CLK_EN; |
285 | a171fe39 | balrog | s->intreq &= ~INT_CLK_OFF; |
286 | a171fe39 | balrog | |
287 | a171fe39 | balrog | if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
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288 | a171fe39 | balrog | s->status &= STAT_CLK_EN; |
289 | a171fe39 | balrog | pxa2xx_mmci_wakequeues(s); |
290 | a171fe39 | balrog | } |
291 | a171fe39 | balrog | } |
292 | a171fe39 | balrog | |
293 | a171fe39 | balrog | if (value & STRPCL_STOP_CLK) {
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294 | a171fe39 | balrog | s->status &= ~STAT_CLK_EN; |
295 | a171fe39 | balrog | s->intreq |= INT_CLK_OFF; |
296 | a171fe39 | balrog | s->active = 0;
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297 | a171fe39 | balrog | } |
298 | a171fe39 | balrog | |
299 | a171fe39 | balrog | pxa2xx_mmci_int_update(s); |
300 | a171fe39 | balrog | break;
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301 | a171fe39 | balrog | |
302 | a171fe39 | balrog | case MMC_CLKRT:
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303 | a171fe39 | balrog | s->clkrt = value & 7;
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304 | a171fe39 | balrog | break;
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305 | a171fe39 | balrog | |
306 | a171fe39 | balrog | case MMC_SPI:
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307 | a171fe39 | balrog | s->spi = value & 0xf;
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308 | a171fe39 | balrog | if (value & SPI_SPI_MODE)
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309 | a171fe39 | balrog | printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
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310 | a171fe39 | balrog | break;
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311 | a171fe39 | balrog | |
312 | a171fe39 | balrog | case MMC_CMDAT:
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313 | a171fe39 | balrog | s->cmdat = value & 0x3dff;
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314 | a171fe39 | balrog | s->active = 0;
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315 | a171fe39 | balrog | s->cmdreq = 1;
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316 | a171fe39 | balrog | if (!(value & CMDAT_STOP_TRAN)) {
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317 | a171fe39 | balrog | s->status &= STAT_CLK_EN; |
318 | a171fe39 | balrog | |
319 | a171fe39 | balrog | if (s->status & STAT_CLK_EN)
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320 | a171fe39 | balrog | pxa2xx_mmci_wakequeues(s); |
321 | a171fe39 | balrog | } |
322 | a171fe39 | balrog | |
323 | a171fe39 | balrog | pxa2xx_mmci_int_update(s); |
324 | a171fe39 | balrog | break;
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325 | a171fe39 | balrog | |
326 | a171fe39 | balrog | case MMC_RESTO:
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327 | a171fe39 | balrog | s->resp_tout = value & 0x7f;
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328 | a171fe39 | balrog | break;
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329 | a171fe39 | balrog | |
330 | a171fe39 | balrog | case MMC_RDTO:
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331 | a171fe39 | balrog | s->read_tout = value & 0xffff;
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332 | a171fe39 | balrog | break;
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333 | a171fe39 | balrog | |
334 | a171fe39 | balrog | case MMC_BLKLEN:
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335 | a171fe39 | balrog | s->blklen = value & 0xfff;
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336 | a171fe39 | balrog | break;
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337 | a171fe39 | balrog | |
338 | a171fe39 | balrog | case MMC_NUMBLK:
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339 | a171fe39 | balrog | s->numblk = value & 0xffff;
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340 | a171fe39 | balrog | break;
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341 | a171fe39 | balrog | |
342 | a171fe39 | balrog | case MMC_PRTBUF:
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343 | a171fe39 | balrog | if (value & PRTBUF_PRT_BUF) {
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344 | a171fe39 | balrog | s->tx_start ^= 32;
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345 | a171fe39 | balrog | s->tx_len = 0;
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346 | a171fe39 | balrog | } |
347 | a171fe39 | balrog | pxa2xx_mmci_fifo_update(s); |
348 | a171fe39 | balrog | break;
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349 | a171fe39 | balrog | |
350 | a171fe39 | balrog | case MMC_I_MASK:
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351 | a171fe39 | balrog | s->intmask = value & 0x1fff;
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352 | a171fe39 | balrog | pxa2xx_mmci_int_update(s); |
353 | a171fe39 | balrog | break;
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354 | a171fe39 | balrog | |
355 | a171fe39 | balrog | case MMC_CMD:
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356 | a171fe39 | balrog | s->cmd = value & 0x3f;
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357 | a171fe39 | balrog | break;
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358 | a171fe39 | balrog | |
359 | a171fe39 | balrog | case MMC_ARGH:
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360 | a171fe39 | balrog | s->arg &= 0x0000ffff;
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361 | a171fe39 | balrog | s->arg |= value << 16;
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362 | a171fe39 | balrog | break;
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363 | a171fe39 | balrog | |
364 | a171fe39 | balrog | case MMC_ARGL:
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365 | a171fe39 | balrog | s->arg &= 0xffff0000;
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366 | a171fe39 | balrog | s->arg |= value & 0x0000ffff;
|
367 | a171fe39 | balrog | break;
|
368 | a171fe39 | balrog | |
369 | a171fe39 | balrog | case MMC_TXFIFO:
|
370 | a171fe39 | balrog | while (s->ac_width -- && s->tx_len < 0x20) |
371 | a171fe39 | balrog | s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
|
372 | a171fe39 | balrog | (value >> (s->ac_width << 3)) & 0xff; |
373 | a171fe39 | balrog | s->intreq &= ~INT_TXFIFO_REQ; |
374 | a171fe39 | balrog | pxa2xx_mmci_fifo_update(s); |
375 | a171fe39 | balrog | break;
|
376 | a171fe39 | balrog | |
377 | a171fe39 | balrog | case MMC_RDWAIT:
|
378 | a171fe39 | balrog | case MMC_BLKS_REM:
|
379 | a171fe39 | balrog | break;
|
380 | a171fe39 | balrog | |
381 | a171fe39 | balrog | default:
|
382 | a171fe39 | balrog | cpu_abort(cpu_single_env, "%s: Bad offset " REG_FMT "\n", |
383 | a171fe39 | balrog | __FUNCTION__, offset); |
384 | a171fe39 | balrog | } |
385 | a171fe39 | balrog | } |
386 | a171fe39 | balrog | |
387 | a171fe39 | balrog | static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset) |
388 | a171fe39 | balrog | { |
389 | a171fe39 | balrog | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
390 | a171fe39 | balrog | s->ac_width = 1;
|
391 | a171fe39 | balrog | return pxa2xx_mmci_read(opaque, offset);
|
392 | a171fe39 | balrog | } |
393 | a171fe39 | balrog | |
394 | a171fe39 | balrog | static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset) |
395 | a171fe39 | balrog | { |
396 | a171fe39 | balrog | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
397 | a171fe39 | balrog | s->ac_width = 2;
|
398 | a171fe39 | balrog | return pxa2xx_mmci_read(opaque, offset);
|
399 | a171fe39 | balrog | } |
400 | a171fe39 | balrog | |
401 | a171fe39 | balrog | static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset) |
402 | a171fe39 | balrog | { |
403 | a171fe39 | balrog | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
404 | a171fe39 | balrog | s->ac_width = 4;
|
405 | a171fe39 | balrog | return pxa2xx_mmci_read(opaque, offset);
|
406 | a171fe39 | balrog | } |
407 | a171fe39 | balrog | |
408 | a171fe39 | balrog | static CPUReadMemoryFunc *pxa2xx_mmci_readfn[] = {
|
409 | a171fe39 | balrog | pxa2xx_mmci_readb, |
410 | a171fe39 | balrog | pxa2xx_mmci_readh, |
411 | a171fe39 | balrog | pxa2xx_mmci_readw |
412 | a171fe39 | balrog | }; |
413 | a171fe39 | balrog | |
414 | a171fe39 | balrog | static void pxa2xx_mmci_writeb(void *opaque, |
415 | a171fe39 | balrog | target_phys_addr_t offset, uint32_t value) |
416 | a171fe39 | balrog | { |
417 | a171fe39 | balrog | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
418 | a171fe39 | balrog | s->ac_width = 1;
|
419 | a171fe39 | balrog | pxa2xx_mmci_write(opaque, offset, value); |
420 | a171fe39 | balrog | } |
421 | a171fe39 | balrog | |
422 | a171fe39 | balrog | static void pxa2xx_mmci_writeh(void *opaque, |
423 | a171fe39 | balrog | target_phys_addr_t offset, uint32_t value) |
424 | a171fe39 | balrog | { |
425 | a171fe39 | balrog | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
426 | a171fe39 | balrog | s->ac_width = 2;
|
427 | a171fe39 | balrog | pxa2xx_mmci_write(opaque, offset, value); |
428 | a171fe39 | balrog | } |
429 | a171fe39 | balrog | |
430 | a171fe39 | balrog | static void pxa2xx_mmci_writew(void *opaque, |
431 | a171fe39 | balrog | target_phys_addr_t offset, uint32_t value) |
432 | a171fe39 | balrog | { |
433 | a171fe39 | balrog | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
434 | a171fe39 | balrog | s->ac_width = 4;
|
435 | a171fe39 | balrog | pxa2xx_mmci_write(opaque, offset, value); |
436 | a171fe39 | balrog | } |
437 | a171fe39 | balrog | |
438 | a171fe39 | balrog | static CPUWriteMemoryFunc *pxa2xx_mmci_writefn[] = {
|
439 | a171fe39 | balrog | pxa2xx_mmci_writeb, |
440 | a171fe39 | balrog | pxa2xx_mmci_writeh, |
441 | a171fe39 | balrog | pxa2xx_mmci_writew |
442 | a171fe39 | balrog | }; |
443 | a171fe39 | balrog | |
444 | aa941b94 | balrog | static void pxa2xx_mmci_save(QEMUFile *f, void *opaque) |
445 | aa941b94 | balrog | { |
446 | aa941b94 | balrog | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
447 | aa941b94 | balrog | int i;
|
448 | aa941b94 | balrog | |
449 | aa941b94 | balrog | qemu_put_be32s(f, &s->status); |
450 | aa941b94 | balrog | qemu_put_be32s(f, &s->clkrt); |
451 | aa941b94 | balrog | qemu_put_be32s(f, &s->spi); |
452 | aa941b94 | balrog | qemu_put_be32s(f, &s->cmdat); |
453 | aa941b94 | balrog | qemu_put_be32s(f, &s->resp_tout); |
454 | aa941b94 | balrog | qemu_put_be32s(f, &s->read_tout); |
455 | aa941b94 | balrog | qemu_put_be32(f, s->blklen); |
456 | aa941b94 | balrog | qemu_put_be32(f, s->numblk); |
457 | aa941b94 | balrog | qemu_put_be32s(f, &s->intmask); |
458 | aa941b94 | balrog | qemu_put_be32s(f, &s->intreq); |
459 | aa941b94 | balrog | qemu_put_be32(f, s->cmd); |
460 | aa941b94 | balrog | qemu_put_be32s(f, &s->arg); |
461 | aa941b94 | balrog | qemu_put_be32(f, s->cmdreq); |
462 | aa941b94 | balrog | qemu_put_be32(f, s->active); |
463 | aa941b94 | balrog | qemu_put_be32(f, s->bytesleft); |
464 | aa941b94 | balrog | |
465 | aa941b94 | balrog | qemu_put_byte(f, s->tx_len); |
466 | aa941b94 | balrog | for (i = 0; i < s->tx_len; i ++) |
467 | aa941b94 | balrog | qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]);
|
468 | aa941b94 | balrog | |
469 | aa941b94 | balrog | qemu_put_byte(f, s->rx_len); |
470 | aa941b94 | balrog | for (i = 0; i < s->rx_len; i ++) |
471 | aa941b94 | balrog | qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]);
|
472 | aa941b94 | balrog | |
473 | aa941b94 | balrog | qemu_put_byte(f, s->resp_len); |
474 | aa941b94 | balrog | for (i = s->resp_len; i < 9; i ++) |
475 | aa941b94 | balrog | qemu_put_be16s(f, &s->resp_fifo[i]); |
476 | aa941b94 | balrog | } |
477 | aa941b94 | balrog | |
478 | aa941b94 | balrog | static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id) |
479 | aa941b94 | balrog | { |
480 | aa941b94 | balrog | struct pxa2xx_mmci_s *s = (struct pxa2xx_mmci_s *) opaque; |
481 | aa941b94 | balrog | int i;
|
482 | aa941b94 | balrog | |
483 | aa941b94 | balrog | qemu_get_be32s(f, &s->status); |
484 | aa941b94 | balrog | qemu_get_be32s(f, &s->clkrt); |
485 | aa941b94 | balrog | qemu_get_be32s(f, &s->spi); |
486 | aa941b94 | balrog | qemu_get_be32s(f, &s->cmdat); |
487 | aa941b94 | balrog | qemu_get_be32s(f, &s->resp_tout); |
488 | aa941b94 | balrog | qemu_get_be32s(f, &s->read_tout); |
489 | aa941b94 | balrog | s->blklen = qemu_get_be32(f); |
490 | aa941b94 | balrog | s->numblk = qemu_get_be32(f); |
491 | aa941b94 | balrog | qemu_get_be32s(f, &s->intmask); |
492 | aa941b94 | balrog | qemu_get_be32s(f, &s->intreq); |
493 | aa941b94 | balrog | s->cmd = qemu_get_be32(f); |
494 | aa941b94 | balrog | qemu_get_be32s(f, &s->arg); |
495 | aa941b94 | balrog | s->cmdreq = qemu_get_be32(f); |
496 | aa941b94 | balrog | s->active = qemu_get_be32(f); |
497 | aa941b94 | balrog | s->bytesleft = qemu_get_be32(f); |
498 | aa941b94 | balrog | |
499 | aa941b94 | balrog | s->tx_len = qemu_get_byte(f); |
500 | aa941b94 | balrog | s->tx_start = 0;
|
501 | aa941b94 | balrog | if (s->tx_len >= sizeof(s->tx_fifo) || s->tx_len < 0) |
502 | aa941b94 | balrog | return -EINVAL;
|
503 | aa941b94 | balrog | for (i = 0; i < s->tx_len; i ++) |
504 | aa941b94 | balrog | s->tx_fifo[i] = qemu_get_byte(f); |
505 | aa941b94 | balrog | |
506 | aa941b94 | balrog | s->rx_len = qemu_get_byte(f); |
507 | aa941b94 | balrog | s->rx_start = 0;
|
508 | aa941b94 | balrog | if (s->rx_len >= sizeof(s->rx_fifo) || s->rx_len < 0) |
509 | aa941b94 | balrog | return -EINVAL;
|
510 | aa941b94 | balrog | for (i = 0; i < s->rx_len; i ++) |
511 | aa941b94 | balrog | s->rx_fifo[i] = qemu_get_byte(f); |
512 | aa941b94 | balrog | |
513 | aa941b94 | balrog | s->resp_len = qemu_get_byte(f); |
514 | aa941b94 | balrog | if (s->resp_len > 9 || s->resp_len < 0) |
515 | aa941b94 | balrog | return -EINVAL;
|
516 | aa941b94 | balrog | for (i = s->resp_len; i < 9; i ++) |
517 | aa941b94 | balrog | qemu_get_be16s(f, &s->resp_fifo[i]); |
518 | aa941b94 | balrog | |
519 | aa941b94 | balrog | return 0; |
520 | aa941b94 | balrog | } |
521 | aa941b94 | balrog | |
522 | a171fe39 | balrog | struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
|
523 | 87ecb68b | pbrook | BlockDriverState *bd, qemu_irq irq, void *dma)
|
524 | a171fe39 | balrog | { |
525 | a171fe39 | balrog | int iomemtype;
|
526 | a171fe39 | balrog | struct pxa2xx_mmci_s *s;
|
527 | a171fe39 | balrog | |
528 | a171fe39 | balrog | s = (struct pxa2xx_mmci_s *) qemu_mallocz(sizeof(struct pxa2xx_mmci_s)); |
529 | a171fe39 | balrog | s->irq = irq; |
530 | a171fe39 | balrog | s->dma = dma; |
531 | a171fe39 | balrog | |
532 | a171fe39 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_mmci_readfn,
|
533 | a171fe39 | balrog | pxa2xx_mmci_writefn, s); |
534 | 187337f8 | pbrook | cpu_register_physical_memory(base, 0x00100000, iomemtype);
|
535 | a171fe39 | balrog | |
536 | a171fe39 | balrog | /* Instantiate the actual storage */
|
537 | c81b7401 | pbrook | s->card = sd_init(bd, 0);
|
538 | a171fe39 | balrog | |
539 | aa941b94 | balrog | register_savevm("pxa2xx_mmci", 0, 0, |
540 | aa941b94 | balrog | pxa2xx_mmci_save, pxa2xx_mmci_load, s); |
541 | aa941b94 | balrog | |
542 | a171fe39 | balrog | return s;
|
543 | a171fe39 | balrog | } |
544 | a171fe39 | balrog | |
545 | 02ce600c | balrog | void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly, |
546 | 02ce600c | balrog | qemu_irq coverswitch) |
547 | a171fe39 | balrog | { |
548 | e1dad5a6 | balrog | sd_set_cb(s->card, readonly, coverswitch); |
549 | a171fe39 | balrog | } |